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MSP50C6xx Mixed-Signal Processor

User’s Guide

Mixed Signal Products

SPSU014A

Printed on Recycled Paper

Summary of content (390 pages)

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MSP50C6xx Mixed-Signal Processor User’s Guide Mixed Signal Products SPSU014A Printed on Recycled Paper
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete.
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Preface Read This First About This Manual This user’s guide gives information for the MSP50C6xx mixed-signal processor. This information includes a functional overview, a detailed architectural description, device peripheral functional description, assembly language instruction listing, code development tools, applications, customer information, and electrical characteristics (in data sheet).
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Notational Conventions Here is a sample program listing: 0011 0012 0013 0014 0005 0005 0005 0006 0001 0003 0006 .field .field .field .even 1, 2 3, 4 6, 3 Here is an example of a system prompt and a command that you might enter: - C: csr –a /user/ti/simuboard/utilities In syntax descriptions, the instruction, command, or directive is in a bold typeface font and parameters are in an italic typeface.
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Information About Cautions and Warnings .byte value1 [, ... , valuen ] This syntax shows that .byte must have at least one value parameter, but you have the option of supplying additional value parameters, separated by commas. Information About Cautions and Warnings This book may contain cautions and warnings. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment. This is an example of a warning statement.
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Contents Contents 1 Introduction to the MSP50C6xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features of the MSP50C6xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Development Device: MSP50P614 . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents 3 Peripheral Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.1.1 General-Purpose I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.1.2 Dedicated Input Port F . . . . . . . . . . . . . . . . . . . . . . .
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Contents 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 5 Instruction Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 4.4.2 Class 2 Instructions: Accumulator and Constant Reference . . . . . . . . . . . . . . 4-28 4.4.3 Class 3 Instruction: Accumulator Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 4.4.4 Class 4 Instructions: Address Register and Memory Reference . . . . . . . . . . . 4-34 4.4.
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Contents 5.6 5.7 5.8 5.9 Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.1 Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.2 Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.3 Function Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Figures Figures 1–1 1–2 1–3 Functional Block Diagram for the MSP50C614/MSP50P614 . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Oscillator and PLL Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 RESET Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 2–9 2–10 MSP50C6xx Core Processor Block Diagram . . . . . . . .
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Tables Tables 2–1 2–2 2–3 2–4 2–5 2–6 Signed and Unsigned Integer Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Summary of MSP50C614’s Peripheral Communications Ports . . . . . . . . . . . . . . . . . . . . . 2-17 Programmable Bits Needed to Control Reduced Power Modes . . . . . . . . . . . . . . . . . . . . . 2-36 Status of Circuitry When in Reduced Power Modes (Refer to Table 2–3) . . . . . . . . . . . .
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Tables 4–28 4–29 4–30 4–31 4–32 4–33 4–34 4–35 4–36 4–37 4–38 4–39 4–40 4–41 4–42 4–43 4–44 4–45 4–46 4–47 4–48 Class 6a Instruction Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 6a Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 6b Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 1 Introduction to the MSP50C6xx The MSP50C6xx is a low cost, mixed signal controller, that combines a speech synthesizer, general-purpose input/output (I/O), onboard ROM, and direct speaker-drive in a single package. The computational unit utilizes a powerful new DSP which gives the MSP50C6xx unprecedented speed and computational flexibility compared with previous devices of its type.
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Features of the MSP50C6xx 1.1 Features of the MSP50C6xx - 1-2 Advanced, integrated speech synthesizer for high quality sound Operates up to 12.32 MHz (performs up to 12.32 MIPS) Very low-power operation, ideal for hand-held devices Low voltage operation, sustainable by three batteries Reduced power stand-by modes, less than 10 µA in deep-sleep mode Supports high-quality synthesis algorithms such as MELP, CELP, LPC, and ADPCM Contains 32K words onboard ROM (2K words reserved) Up to 2.
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Applications 1.
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Development Device: MSP50P614 1.3 Development Device: MSP50P614 The MSP50P614 is an EPROM based version of the MSP50C614, and is available in a 120-pin windowed ceramic pin grid array. This EPROM based version of the device is only available in limited quantities to support software development. Since the MSP50P614 program memory is EPROM, each person doing software development should have several of these PGA packaged devices.
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Functional Description for the MSP50C614 1.4 Functional Description for the MSP50C614 The MSP50C614 device consists of a micro-DSP core, embedded program and data memory, and a self-contained clock generation system. General-purpose periphery is comprised of 64 bits of flexible I/O. The block diagram appearing in Figure 1–1 gives an overview of the MSP50C614/MSP50P614 functionality. Figure 1–1.
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Functional Description for the MSP50C614 The core processor is a general-purpose 16 bit micro-controller with DSP capability. The basic core block includes a computational unit (CU), data address unit, program address unit, two timers, eight level interrupt processor, and several system and control registers. The core processor provides break-point capability to the MSP50C6xx code development software (EMUC6xx). The processor is a Harvard type for efficient DSP algorithm execution.
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Functional Description for the MSP50C614 Figure 1–2. Oscillator and PLL Connection a) Crystal Reference Oscillator Connections MSP50P614 MSP50C6xx OSCIN OSCOUT PLL 10 MΩ† 32.768 kHz† 10 MΩ† 22 pF† 22 pF† C(PLL) = 3300 pF† † Keep these components as close as possible to the OSCIN, OSCOUT, and PLL pins.
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Functional Description for the MSP50C614 Rounding out the MSP50C6xx periphery is a built in pulse-density-modulated (PDM) digital-to-analog converter (DAC) with direct speaker-drive capability. Typical connections to implement reset functionality are shown in Figure 1–3. An external reset circuit is required to hold the reset pin low until the MSP50C6xx power supply has stabilized in the specified voltage range. In some cases, a simple reset circuit (as shown in Figure 1–3) can be used for this purpose.
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MSP50C601, MSP50C604, and MSP50C605 1.5 MSP50C601, MSP50C604, and MSP50C605 Related products, the MSP50C601, MSP50C604, and MSP50C605 use the MSP50C6xx core. The MSP50C601 has a 128K byte data ROM built into the chip and 32 I/O port pins. The MSP50C605 has a 224K byte data ROM built into the chip and 32 I/O port pins. The MSP50C604 has a 64K byte data ROM built into the chip and 16 I/O port pins.
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1-10
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Chapter 2 MSP50C6xx Architecture A detailed description of the MSP50C6xx architecture is included in this chapter. After reading this chapter, the reader will have in-depth knowledge of internal blocks, memory organization, interrupt system, timers, clock control mechanism, and various low power modes. Topic Page 2.1 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2 2.2 Computation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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2.1 Architecture Overview The core processor in the C6xx is a medium performance mixed signal processor with enhanced microcontroller features and a limited DSP instruction set. In addition to its basic multiply/accumulate structure for DSP routines, the core provides for a very efficient handling of string and bit manipulation. A unique accumulator-register file provides additional scratch pad memory and minimizes memory thrashing for many operations.
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Figure 2–1.
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Figure 2–2.
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Computation Unit 2.2 Computation Unit The computational unit (CU) is comprised of a (17-bit by 17-bit) Booth’s algorithm multiplier and a 16-bit arithmetic logic unit (ALU). The block diagram of the CU is shown in Figure 2–2. The multiplier block is served by 4 system registers: a 16-bit multiplier register (MR), a 16-bit write-only multiplicand register, a 16-bit high word product register (PH), and a 4-bit shift value register (SV).
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Computation Unit The multiplicand source can be either data memory, an accumulator, or an accumulator offset. The multiplier source can be either the 16-bit multiplier register (MR) or the 4-bit shift value (SV) register. For all multiply operations, the MR register stores the multiplier operand. For barrel shift instructions, the multiplier operand is a 4-to-16-bit value that is decoded from the 4-bit shift value register (SV).
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Computation Unit Figure 2–3. Overview of the Multiplier Unit Operation MULTIPLIER UNIT INPUTS Multiplicand 16-bit X Multiplier - latched in a write-only register from one of the following sources ... Data Memory Accumulator Offset Accumulator - writeable and readable by Data Memory as one of the following ...
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Computation Unit The all-zero values are necessary for data transfers and unitary operations. All-zeros also serve as default values for the registers, which helps to minimize residual power consumption. The databus path through ALU-A is used to input memory values (RAM) and constant values (program memory) to the ALU. The PH and PL inputs are useful for supporting multiply-accumulate operations (refer to Section 2.2.1, Multiplier).
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Computation Unit Figure 2–4. Overview of the Arithmetic Logic Unit ALU INPUTS ALU-A 16-bit ALU-B 16-bit - selects between ... (PH) (PL) - selects between ... all 0’s Offset Accumulator Register Data Memory Program Memory Product High† Product Low† all 0’s Accumulator Register ARITHMETIC LOGIC UNIT performs arithmetic, comparison, and logic ALU OUTPUTS THE ACCUMULATOR BLOCK Accumulator Register OFFSET Accumulator Register 16 × 16-bit registers ... 16 × 16-bit registers ...
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Computation Unit When writing an accumulator-referenced instruction, therefore, the working accumulator address is stored in one of AP0 to AP3. The C6xx instruction set provides a two-bit field for all accumulator referenced instructions. The two-bit field serves as a reference to the accumulator pointer which, in turn, stores the address of the actual 16-bit accumulator. Some MOV instructions store the contents of the APn directly to memory or load from memory to the APn register.
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Data Memory Address Unit For some instructions, the 5-bit string processor can also preincrement or predecrement the AP pointer-value by +1 or –1, before being used by the accumulator register block. This utility can be effectively used to minimize software overhead in manipulating the accumulator address. The premodification of the address avoids the software pipelining effect that post-modification would cause.
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Data Memory Address Unit Figure 2–6. Data Memory Address Unit Arithmetic Block RAM Address R0 R1 R2 R3 R4 R5 R6 R7 LOOP INDEX PAGE STACK Register Addressing Mode Internal Databus Internal Program Bus 2.3.1 RAM Configuration The data memory block (RAM) is physically organized into 17-bit parallel words. Within each word, the extra bit (bit 16) is used as a flag bit or tag for op-codes in the instruction set.
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Data Memory Address Unit There are two-byte instructions, for example MOVB, which cause the processor to read or write data in a byte (8-bit) format. (The B appearing at the end of MOVB designates it as an instruction that uses byte-addressable arguments.) The byte-addressable mode causes the hardware to read/write either the upper or lower 8 bits of the 16-bit word based on the LSB of the address. In this case, the address is a byte address, rather than a word address.
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Program Counter Unit 2.4 Program Counter Unit The program counter unit provides addressing for program memory (onboard ROM). It includes a 16-bit arithmetic block for incrementing and loading addresses. It also consists of the program counter (PC), the data pointer (DP), a buffer register, a code protection write-only register, and a hardware loop counter (for strings and repeated-instruction loops). The program counter unit generates a ROM address as output.
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Memory Organization: RAM and ROM 2.6 Memory Organization: RAM and ROM Data memory (RAM) and program memory (ROM) are each restricted to internal blocks on the C6xx. The program memory is read-only and limited to 32K, 17-bit words. The lower 2048 of these words is reserved for an internal test code and is not available to the user. The data memory is static RAM and is limited to 640, 17-bit words. 16 bits of the 17-bit RAM are used for the data value, while the extra bit is used as a status flag.
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Memory Organization: RAM and ROM Figure 2–7.
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Memory Organization: RAM and ROM When writing to any of the locations in the I/O address map, therefore, the bit-masking need only extend as far as width of location. Within a 16-bit accumulator, the desired bits (width of location) should be right-justified. The write operation is accomplished using the OUT instruction, with the address of the I/O port as an argument. A read from these locations is accomplished using the IN instruction, with the address of the I/O port as an argument.
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Memory Organization: RAM and ROM Table 2–2.
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Memory Organization: RAM and ROM The branch to the program location that is specified in the interrupt vector is, of course, contingent on the occurrence of the trigger event. Refer to Section 3.1.5, Internal and External Interrupts, for more information regarding the specific conditions for each interrupt-trigger event. The branch operation, however, is also contingent on whether the interrupt service has been enabled.
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Memory Organization: RAM and ROM Note: Instructions with References Care must be taken when employing instructions that have either long string constant references or look-up table references. These instructions will execute properly only if the address of the instruction and the address of the data reference are within the same block. The protection modes are implemented on the C6xx as follows. Within the ROM is a dedicated storage for the block protection word (address 0x7FFE).
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Memory Organization: RAM and ROM [(NTM + 1) * 512 – 1] = highest ROM address within the block to be protected = lowest ROM address which is left unprotected (NTM + 1) * 512 = the value programmed at TM5…TM0 (true NTM protection marker) ≡ the binary complement of NTM NFM NFM = the value programmed at FM5…FM0 (false protection marker) The purpose of the true and false protection markers is to provide parity. An erased P614 EPROM cell defaults to the value 1.
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Interrupt Logic When the device is powered up, the hardware initialization circuit reads the value stored in the block protection word. The value is then loaded to an internal register and the security state of the ROM is identified. Until this occurs, execution of any instructions is suspended. The same initialization sequence is executed before entry into the special test-modes available on the P614 and C6xx (EPROM mode, emulation mode, and trace mode).
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Interrupt Logic automatically SET in the interrupt flag register (IFR). The IFR is an 8-bit wide port-addressed register; wherein, each interrupt level is represented. A set bit in the IFR indicates that the interrupt is pending and waiting to be serviced. A clear bit indicates that the interrupt is not currently pending. The address of the IFR is 0x39. After a RESET low, the IFR is left in the same state it was before the RESET low, assuming there is no interruption in power.
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Interrupt Logic Note: Setting a Bit in the IFR Using the OUT Instruction Setting a bit within the IFR using the OUT instruction is a valid way of obtaining a software interrupt. An IFR bit may also be cleared, using OUT, at any time. Assuming the global interrupt enable is set and the specific bit within the IMR is set, then, at the time of the interrupt-trigger event, an interrupt service branch is initiated. (The trigger event is marked by a 0-to-1 transition in the IFR bit).
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Interrupt Logic Figure 2–8 provides an overview of the interrupt control sequence. INT0 is the highest priority interrupt, and INT7 is the lowest priority interrupt. Figure 2–8.
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Clock Control In addition to being individually enabled, all interrupts must be GLOBALLY enabled before any one can be serviced. Whenever interrupts are globally disabled, the interrupt flag register may still receive updates on pending trigger events. Those trigger events, however, are not serviced until the next INTE instruction is encountered. After an interrupt service branch, it is the responsibility of the programmer to re-SET the global interrupt enable, using the INTE instruction. 2.
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Clock Control therefore, is 131.07 kHz, and the multiplier operates in increments of this base frequency. The minimum multiplication of the base frequency is 1, and the maximum multiplication is 256. The resulting master clock frequency, therefore, can be varied from a minimum of 131.07 kHz to a maximum of 33.554 MHz, in 131.07 kHz steps. From the master clock to the CPU clock, there is a divide-by-two in frequency. The CPU clock, therefore, can be set to run between 65.
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Clock Control 2.8.3 Clock Speed Control Register The ClkSpdCtrl is a 16-bit memory mapped register located at address 0x3D. The reference oscillator (RTO or CRO) is selected by setting one of the two control bits located at bits 8 and 9. Setting bit 8 configures the C6xx for the RTO reference option and simultaneously starts that oscillator. Setting bit 9 configures the C6xx for the CRO reference option and simultaneously pulses the crystal, which starts that oscillator.
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Clock Control The configuration of bits in the clock speed control register appears below: ClkSpdCtrl register address 0x3D (16-bit wide location) WRITE only 15 14 13 12 11 T5 T4 T3 T2 T1 10 09 08 07 06 05 04 03 02 01 00 I C or T0 R M M M M M M M M T : RTO oscillator-Trim adjust R : enable Resistor-trimmed oscillator I : Idle State clock Control M : PLLM multiplier bits for MC C : enable Crystal oscillator (or T0 if R is set 0x0000 : default state after RESET LOW Bit
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Clock Control RTRIM Register (Read Only) (Applies to MSP50C6xx Device Only) I/O Address 0x2Fh (17-bit wide location) 16 15 14 13 12 11 10 09 08 07 06 R R R R R R R R R R R 3 05 04 03 02 01 00 T5 T4 T3 T2 T1 T0 2 0 T: RTO oscillator-trim storage (device specific) R: reserved for Texas Instruments use ClkSpdCtrl Value Copied (Shaded) 15 14 13 12 11 10 9 8 T5 T4 T3 T2 T1 I T0 1 7 6 5 4 1 M7 M6 M5 M4 M3 M2 M1 M0 When selecting and enabling the RTO oscil
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Timer Registers This software-controlled trim for the RTO is not a replacement for the external reference-resistor mounted at pins OSCIN and OSCOUT. Also, note that this adjustment has no effect on the rate of the CRO reference oscillator. 2.9 Timer Registers The C6xx contains two identical timers, TIMER1 and TIMER2. Each includes a period register and a count-down register.
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Timer Registers Reading from either the PRD or the TIM returns the current state of the register. This can be used to monitor the progress of the TIM register at any time. Writing to the PRD register does not change the TIM register until the TIM register has finished decrementing to 0x0000. The new value in the PRD register is then loaded to the TIM register, and counting resumes from the new value.
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Reduced Power Modes enable bit for TIMER2. Setting the enable bit enables the TIMER, i.e., starts count-down running. Clearing the enable bit disables the TIMER, i.e., stops the count-down. The default setting after a RESET LOW is zero: both TIMERs disabled. Refer to Section 3.4, Interrupt/General Control Register, for summary information regarding the IntGenCtrl. The TIMER enable bits may be used to start and stop the TIMERs repeatedly in software.
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Reduced Power Modes overall power consumption during that state. The various subsystems that determine (or are affected by) the depth of sleep include the: - Processor core, which is driven by the CPU clock PLL clock circuitry PLL reference oscillator C6xx periphery, which is driven by the master clock TIMER1 and TIMER2 PDM pulsing The deepest sleep achievable on the C6xx, for example, is a mode where all of the previously listed subsytems are stopped.
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Reduced Power Modes If either of bits 8 or 9 are set, then the reference oscillator enable is considered set. This enables the PLL circuitry to regulate to the reference frequency, 32 kHz (assuming the idle state clock control is clear). Whichever state the reference oscillator is in before idle, it remains in that state (running or stopped) after idle. If the reference oscillator is left running during sleep, however, it comes at a cost to power consumption.
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Reduced Power Modes Note: Idle State Clock Control Bit If the idle state clock control bit is set and the ARM bit is clear, the only event that can wake the C6xx after an IDLE instruction is a hardware RESET lowto-high. When at sleep, the device will not respond to the input ports, nor to the internal timers. Table 2–3.
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Reduced Power Modes Table 2–4.
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Reduced Power Modes either type of interrupt (internal or external). In most cases, the state of these bits should coincide. The interrupt-trigger event associated with each of the two internal TIMERs is the underflow condition of the TIMER. In order for a TIMER underflow to occur during sleep, the TIMER must be left running before going to sleep. In certain cases, however, the act of going to sleep can bring a TIMER to stop, thereby preventing a TIMER-induced wake-up.
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Reduced Power Modes Under normal operation the DAC timer, when IMR enabled, triggers an interrupt on underflow. Before any IDLE instruction, however, the entire DAC circuitry should be disabled. This ensures the effectiveness of the reduced power mode and prevents any wake-up from the DAC timer. In order to wake the device using a programmable interrupt, the interrupt mask register must have the respective bit set to enable interrupt service (see Section 2.7, Interrupt Logic).
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Execution Timing 2.11 Execution Timing For executing program code, the C6xx’s core processor has a three-level pipeline. The pipeline consists of instruction fetch, instruction decode, and instruction execution. A single instruction cycle is limited to one program Fetch plus one data memory read or write. The master clock consists of two phases with non-overlap protection. A fully static implementation eliminates precharge time on busses or in memory blocks.
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Chapter 3 Peripheral Functions This chapter describes in detail the MSP50C6xx peripheral functions, i.e., I/O control ports, general purpose I/O ports, interrupt control registers, comparator and digital-to-analog (DAC) control mechanisms. Topic Page 3.1 I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 3.2 Digital-to-Analog Converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9 3.3 Comparator . . .
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I/O 3.1 I/O This section discusses the I/O capabilities of the MSP50C6xx family. The following table shows the number and types of I/O available on each device. Please note that this section discusses all I/O ports, which are only available on the MSP50C614 device. All other devices have only a subset of the I/O that is available on the MSP50C614. Ports Available No. of General Purpose I/O No. of Dedicated Inputs No.
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I/O Port A Port B Port C Port D Port E Control register address 0x04h† 0x0Ch 0x14h 0x1Ch 0x24h Possible control values 0 = High-Z INPUT Value after RESET low Data register address Possible input data values 1 = TOTEM-POLE OUTPUT 0 = High-Z INPUT 0x00h 0x08h Low = 0 Possible output data values 0x10h 0x18h 0x20h High = 1 (don’t care on write) 0 = Low 1 = High † Each of these I/O ports is only 8 bits wide.
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I/O The following table shows the bit locations of the I/O port mapping: (8-bit wide location) 07 06 05 04 03 02 01 00 A port data register . . . . . address 0x00 A7 A6 A5 A4 A3 A2 A1 A0 A port control register . . . address 0x04 C B port data register . . . . . address 0x08 B7 B6 B5 B4 B3 B2 B1 B0 B port control register . . . address 0x0C C C port data register . . . . . address 0x10 C7 C6 C5 C4 C3 C2 C1 C0 C port control register . . . address 0x14 C D port data register . . . . .
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I/O and setting the EP bit enables the eight pullups. After RESET low, the default setting for the EP bit is 0 (F-port pullups disabled). Input Port F Data register address Possible input data values Possible output data values Value after RESET low 0x28h Low = 0 High = 1 N/A Pullup resistors DISABLED When reading from the 8-bit F-port data register to a 16-bit accumulator, the IN instruction automatically clears the extra bits in excess of 8.
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I/O Totem-Pole Output Port G Data register address 0x2Ch Possible input data values N/A Possible output data values 0 = Low Value after RESET low 1 = High 0 = Low The following table shows the bit locations of the port G address mapping: G port Data address 0x2C read and write (16-bit wide location) 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 0x0000 : default state of data register after RESET low 3.1.
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I/O 3.1.5 Internal and External Interrupts INT3, INT4, INT6, and INT7 are external interrupts which may be triggered by events on the PD2, PD3, PD4, and PD5 pins. These interrupts are supported whether the D-port pins are programmed as inputs or outputs. (When programmed as an output, the pin effectively triggers a software interrupt.) INT5 is an external interrupt triggered by a falling-edge event on any of the F-port inputs.
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I/O A summary of the interrupts is given in Table 3–1. Table 3–1. Interrupts Interrupt Vector Source INT0 0x7FF0 DAC Timer Trigger Event Priority Timer underflow Highest Comment Used to synch.
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Digital-to-Analog Converter (DAC) 3.2 Digital-to-Analog Converter (DAC) The MSP50C6xx incorporates a two-pin pulse-density-modulated DAC which is capable of driving a 32-Ω loudspeaker directly. To drive loud speakers other than 32 Ω, an external impedance-matching circuit is required. 3.2.1 Pulse-Density Modulation Rate The rate of the master clock (MC) determines the pulse-density-modulation (PDM) rate, and this governs the output sampling-rate and the achievable DAC resolution.
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Digital-to-Analog Converter (DAC) DAC Control register Address 0x34 (4-bit wide location) 03 02 01 00 Set DAC resolution to 8 bits: Set DAC resolution to 9 bits: Set DAC resolution to 10 bits: DM DM DM E E E 0 0 1 0 1 0 DM : Drive Mode selection (0 = C3x style : 1 = C5x style) E : pulse-density-modulation Enable (overall DAC enable) 0x0 : default state of register after RESET low Bit 2 in the DAC control register is used to enable/disable the pulse-density modulation.
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Digital-to-Analog Converter (DAC) style. Their selection is made at bit 3 of the DAC control register (0x34). The C3x style is selected by clearing bit 3, and the C5x style is selected by setting bit 3. The default value of the selection is zero which yields the C3x style. The overflow bits appear in the DAC data register (14 and 13) to the left of the MSB data bit (12). In the C3x style mode, the overflow bits serve as a 2-bit buffer to handle overflow in the value field (bits 12…3).
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Digital-to-Analog Converter (DAC) For a given sampling rate and DAC resolution, the CPU clock rate may be increased, if necessary, through the use of over-sampling. In the previous example, an original sampling rate of 8 kHz and a PDM rate of 4 MHz was used. A 2-times over-sampling, therefore, would require the PDM rate to be 8 MHz. This can be accomplished in two ways: PDM rate = 8 MHz : Set the master clock to 8 MHz also (ClkSpdCtrl). Set the PDMCD bit to 1: 1x master clock (IntGenCtrl).
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Digital-to-Analog Converter (DAC) Example 3–1. 8-kHz Sampling Rate 8 kHz Nominal Synthesis Rate 32.768 kHz Oscillator Reference ClkSpdCtrl PLLM Register Value (hex) Master Clock Rate (MHz) PDM Rate (MHz) CPU Clock Rate (MHz) Output Sampling Rate (kHz) Number of Instructs Between DAC Interrupts Number of Instructs Between 8 kHz Interrupts DAC Precision IntGenCtrl PDMCD Bit OverSampling Factor 8 bits 1 1x 0x 0F 2.10 2.10 1.05 8.19 128 128 2x 0x 1E 4.06 4.06 2.03 15.
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Digital-to-Analog Converter (DAC) Example 3–2. 10-kHz Sampling Rate 10 kHz Nominal Synthesis Rate 32.768 kHz Oscillator Reference DAC Precision IntGenCtrl PDMCD Bit OverSampling Factor ClkSpdCtrl PLLM Register Value (hex) 8 bits 1 1x 0x 13 0 9 bits 1 0 10 bits “1” “0” 3-14 Master Clock Rate (MHz) 2.62 Number of Instructs Between DAC Interrupts Number of Instructs Between 10 kHz Interrupts 10.24 128 128 PDM RATE (MHZ) CPU Clock Rate (MHz) Output Sampling Rate (kHz) 2.62 1.
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Comparator 3.3 Comparator The MSP50C6xx provides a simple comparator that is enabled by a control register option. The inputs of the comparator are shared with pins PD4 and PD5. PD5 is the noninverting input to the comparator, and PD4 is the inverting input. When the comparator is enabled, the conditional operation COND2 (normally associated with PD1) becomes associated with the comparator result.
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Comparator The INT6 Flag may also be SET or CLEARed deliberately, at any time, in software. Use the OUT instruction with the associated I/O port address (IFR, address 0x39). INT7 flag refers to bit 7 within the interrupt flag register. This bit is automatically SET anytime that an INT7 event occurs. This causes the device to branch to the INT7 vector if the associated mask bit is set (IntGenCtrl, address 0x38, bit 7).
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Comparator The function of pins PD4 and PD5, and the behavior of events COND2, INT6, INT7, and TIMER1 are different, depending on whether the comparator has been enabled or disabled. A summary of the various states appears in the following table: Comparator ENABLED SET bit 15 in the IntGenCtrl, address 0x38 . . .
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Interrupt/General Control Register 3.4 Interrupt/General Control Register The interrupt/general control (IntGenCtrl) is a 16-bit wide port-mapped register located at address 0x38. The primary component in the IntGenCtrl is the 8-bit interrupt mask register (IMR). The IMR is used to individually enable all interrupts except RESET. Each bit of the IMR is associated with one of the interrupts described in Section 3.1.5. An interrupt is enabled when the appropriate IMR bit is set.
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Interrupt/General Control Register The upper four bits in the IntGenCtrl have independent functions. Bit 12 is the enable bit for the pull-up resistors on port F. Setting this bit applies individual pull-up resistors to each of the F port pins (see Section 3.1.2, Dedicated Input Port F). Bit 13 is the PDMCD bit for the pulse-density modulation clock. Clearing this bit yields a PDM clock rate equal to one-half the frequency of the master clock (i.e., the CPU clock rate).
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Hardware Initialization States 3.5 Hardware Initialization States The RESET pin is configured at all times as an external interrupt. It provides for a hardware initialization of the MSP50C6xx. When the RESET pin is held low, the device assumes a deep sleep state and various control registers are initialized. After the RESET pin is taken high, the Program Counter is loaded with the value stored in the RESET Interrupt Vector.
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Hardware Initialization States Note: Internal RAM State after Reset The RESET low will not change the state of the internal RAM, assuming there is no interruption in power. This applies also to the interrupt flag register. The same applies to the states of the accumulators in the computational unit. When RESET is brought back high again, many of the programmable controls and registers are left in their default states: RESET high, just after low . . . - No reference oscillator is enabled.
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Hardware Initialization States Table 3–2.
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Chapter 4 Assembly Language Instructions This chapter describes in detail about MSP50P614/MSP50C614 assembly language. Instruction classes, addressing modes, instruction encoding and explanation of each instruction is described. Topic Page 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2 4.2 System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2 4.
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Introduction 4.1 Introduction In this chapter each MSP50P614/MSP50C614 class of instructions is explained in detail with examples and restrictions. Most instructions can individually address bits, bytes, words or strings of words or bytes. Usable program memory is 30K by 17-bit wide and the entire 17-bits are used for instruction set encoding. The execution of programs can only be executed from internal program memory. Usable program memory starts from location 800h.
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System Registers or by 2 for double word instructions) each execution cycle and points to the next program memory location to fetch. During a maskable interrupt, the next PC address is stored in the TOS register and is reloaded from TOS after the interrupt encounters an IRET instruction. Call and jump instructions also store the next instruction address by adding PC+2 and then storing the result in the TOS register. Upon encountering a RET instruction, the TOS value is reloaded to the PC.
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System Registers It is recommended to avoid using the TOS register altogether in applications and leave its operation to development tools only. 4.2.6 Product High Register (PH) This register holds the upper 16 bits of the 32-bit result of a multiplication, multiply-accumulate, or shift operation. The lower 16 bits of the result are stored in the PL register. The PH register can be loaded directly by MOV instructions.
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System Registers During accumulator read operations, both An and offset An~ are fetched. Depending on the instruction, either or both registers may be used. In addition, some write operations allow either register to be selected. The accumulator block can also be used in string operations. The selected accumulator (An or An~) is the least significant word (LSW) of the string and is restored at the end of the operation. String instructions are described in detail in section 4.8. 4.2.
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System Registers value of the STACK register should be stored before use and restored after use. This register must point to the beginning of the stack in the RESET initialization routine before any CALL instruction or maskable interrupts can be used. CALL instructions increment R7 by 2., RET instructions decrement R7 by 2. The stack in MSP50P614/MSP50C614 is positively incremented. 4.2.11 String Register (STR) The string register (STR) holds the length of the string used by all string instructions.
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System Registers Table 4–1. Status Register (STAT) Bit Name Function 0 XM Sign extended mode bit. This bit is one, if sign extension mode is enabled. See MSP50P614/MSP50C614 Computational Modes, Section 4.6. 1 UM Unsigned multiplier mode. This bit is one if unsigned multiplier mode is enabled. See MSP50P614/MSP50C614 Computational Modes, Section 4.6. 2 OM Overflow mode. This bit is one if overflow (saturation) mode is enabled. See MSP50P614/MSP50C614 Computational Modes, Section 4.6.
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Instruction Syntax and Addressing Modes 4.3 Instruction Syntax and Addressing Modes MSP50P614/MSP50C614 instructions can perform multiple operations per instruction. Many instructions may have multiple source arguments. They can premodify register values and can have only one destination. The addressing mode is part of the source and destination arguments.
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Instruction Syntax and Addressing Modes 4.3.2 Addressing Modes The addressing modes on the MSP50P614/MSP50C614 are immediate, direct, indirect with post modification, and three relative modes. The relative modes are: - Relative to the INDEX or R5 register. The effective address is (indirect register + INDEX). Short relative to the PAGE or R6 register. The effective address is (PAGE+7-bit positive offset). Long relative to Rx. The effective address is (indirect register Rx + 16-bit positive offset).
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Instruction Syntax and Addressing Modes Table 4–3. Rx Bit Description Rx Operation 0 0 0 R0 0 0 1 R1 0 1 0 R2 0 1 1 R3 1 0 0 R4 or LOOP 1 0 1 R5 or INDEX 1 1 0 R6 or PAGE 1 1 1 R7 or STACK Table 4–4.
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Instruction Syntax and Addressing Modes Table 4–5. MSP50P614/MSP50C614 Addressing Modes Summary ADDRESSING SYNTAX OPERATION Direct name [dest,] [src,] *dma16 [*2] [, next A] name *dma16 [*2] [,src] [, next A] Second word operand (dma16) used directly as memory address. Long Relative name [dest] [,src] ,*Rx+offset16 [, next A] name *Rx+offset16 [,src] [, next A] Selects one of 8 address registers as base value and adds the value in the second word operand. Does not modify the base address register.
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Instruction Syntax and Addressing Modes For any particular addressing mode, replace the {adrs} with the syntax shown in Table 4–4. To encode the instruction, replace the am, Rx and pm bits with the bits required by the addressing mode (Table 4–4).
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Instruction Syntax and Addressing Modes 4.3.3 Immediate Addressing The address of the memory location is encoded in the instruction word or the word following the opcode is the immediate value. Single word instructions take one clock cycle and double word instructions take two clock cycles. Syntax: name dest, [src,] imm [, next A] Where: imm is the immediate value of a 16-bit number. Example 4.3.1 ADD AP0, 0x1A Assume the initial processor state in Table 4–8 before execution of this instruction.
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Instruction Syntax and Addressing Modes 4.3.4 Direct Addressing Direct addressing always requires two instruction words. The second word operand is used directly as the memory address. The memory operand may be a label or an expression. Syntax: name [dest,] [src,] *dma16 [* 2] [, next A] name *dma16 [* 2] [, src] [, next A] Memory Operand Operand Note the multiplication by 2 with the data memory address. This only needs to be done for word addresses, i.e., the address that points to 16-bit words.
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Instruction Syntax and Addressing Modes 4.3.5 Indirect Addressing Indirect addressing uses one of 8 registers (R0...R7) to point memory addresses. The selected register can be post-modified. Modifications include increments, decrements, or increments by the value in the index register (R5). For post-modifications, the register increments or decrements itself by 2 for word operands and by 1 for byte operands. Syntaxes are shown in Table 4–9. Table 4–9.
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Instruction Syntax and Addressing Modes Example 4.3.12 MOV *R5++R5, A0~, ++A Refer to the initial processor state in Table 4–8 before execution of this instruction. Preincrement AP0. After preincrement, A0 is AC3 and A0~ is AC19. The contents of AC19 are stored in the data memory location in R5. R5 is then incremented by R5. Final result, AP0=3, R5 = 0x0004, *0x0002 = 0xFEED. Example 4.3.13 MOV A2, *R0 Refer to the initial processor state in Table 4–8 before execution of this instruction.
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Instruction Syntax and Addressing Modes Address Rx (x = 0 – 7) + Index Register (R5) Operand Example 4.3.17 AND A0, *R3+R5 Refer to the initial processor state in Table 4–8 before execution of this instruction. A0 is accumulator AC2. The contents of the data memory byte location pointed to by R3+R5 is ANDed with AC2. The result is stored in AC2. The values in R3 and R5 are unchanged. Final result, AC2 = AC2 AND *0x01F2 = 0x13F0 AND 0x12AC = 0x12A0. Example 4.3.
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Instruction Syntax and Addressing Modes Example 4.3.20 MOV A3, *R6+0x10 Refer to the initial processor state in Table 4–8 before execution of this instruction. Load A3 (AC29) with the contents of byte address, R6+0x10. The value of R6 is unchanged. Final result, AC29=0x0112. Example 4.3.21 ADD A0~, A0, *R6+0x10, ++A Refer to the initial processor state in Table 4–8 before execution of this instruction. Preincrement AP0. After preincrement, A0 is AC3 and A0~ is AC19.
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Instruction Syntax and Addressing Modes 4.3.7 Flag Addressing This addressing mode addresses only the 17th bit (the flag/tag bit) located in data memory. This addressing applies to Class 8a instructions as explained in section 4.4. Using flag addressing, the flag bit can be loaded or saved. In addition, various logical operations can be performed without affecting the remaining 16 bits of the selected word. Two addressing modes are provided.
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Instruction Syntax and Addressing Modes 4.3.8 Tag/Flag Bits The words TAG and flag may be used interchangeably in this manual. The TAG bit is the 17th bit of a word of data memory. There are 640 words of RAM, each 17 bits wide, on the C614. Therefore, there are 640 TAG bits on the C614. When an instruction of the format, MOV accumulator, RAM is performed, the STAT register is affected by various properties of this transfer.
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Instruction Syntax and Addressing Modes However, xFLAG instructions use {flagadrs} addressing modes. This includes global (dma6) and relative (R6 + 6–bit offset). Both take only one clock cycle.
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Instruction Classification 4.4 Instruction Classification The machine level instruction set is divided into a number of classes. The classes are primarily divided according to field references associated with memory, hardware registers, and control fields. The following descriptions give class-encode bit assignments, the OP code value within the class, and the abbreviated field descriptions.
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Instruction Classification Table 4–11. Symbols and Explanation (Continued) Symbol Explanation next A Accumulator control bits as described in Table 4–6. [next A] The preincrement (++A) or predecrement (– –A) operation on accumulator pointers An or An~. Not NOT condition on conditional jumps, conditional calls or test flag instructions. nR Value in the repeat counter loaded by repeat instruction. ns Value in string register STR. offset[n] n bit offset from a reference register.
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Instruction Classification Table 4–11.
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Instruction Classification Table 4–12.
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Instruction Classification Class 1a provides the four basic instructions of load, store, add, and subtract between accumulator and data memory. Either the accumulator or the offset accumulator (A~ bit dependent) can be stored in memory with the MOV instruction. The MOV instruction can load the accumulator (or its offset) depending on the ~A bit. The ADD or SUB instructions add or subtract memory from an accumulator register and save the results in the accumulator register (~A=0) or its offset (~A=1).
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Instruction Classification Table 4–15. Class 1b Instruction Description C1b Mnemonic Description 0 0 0 0 OR An, {adrs} ORS An, {adrs} Logical OR the contents of the data memory location in {adrs} and the selected accumulator. Result(s) stored in accumulator(s). ALU status is modified 0 0 0 1 AND An, {adrs} ANDS An, {adrs} Logical AND the contents of the data memory location in {adrs} and the accumulator. Result(s) stored in accumulator(s).
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Instruction Classification Table 4–15. Class 1b Instruction Description (Continued) C1b Mnemonic Description 1 0 1 1 MULAPL An, {adrs} MULAPLS An, {adrs} Multiply the MR register by the addressing mode {adrs} and add the lower 16 bits of the product to the accumulator. Latch the upper 16 bits into the PH register. ALU status is modified. 1 1 0 0 SHLTPL An, {adrs} SHLTPLS An, {adrs} Shift left n bits (SV reg).
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Instruction Classification constants. Long constants (16 bits) and long string constants differ in that references are made to constants in the second word of the two-word instruction word. References made to a single 16-bit integer constant are immediate. That is, the actual constant value follows the first word opcode in memory.
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Instruction Classification Table 4–18. Class 2b Instruction Description C2b Mnemonic Description 0 0 0 ADD An[~], An[~], imm16 [, next A] ADDS An[~], An[~], pma16 Add long constant to accumulator (or offset accumulator if A~=1) and store result to accumulator (~A=0) or offset accumulator (~A=1). ALU status modified. 0 0 1 MOV An[~], imm16 [, next A] MOVS An[~], pma16 Load long constant to accumulator (~A=0 or 1). ALU status is modified.
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Instruction Classification between the accumulator and the MR, SV, or PH register. As with all accumulator referenced instructions, string operations are possible as well as premodification of one of 4 indirectly referenced accumulator pointer registers (AP). Table 4–19. Class 3 Instruction Encoding Bit 16 15 14 13 12 Class 3 1 1 1 0 0 11 10 9 next A 8 7 An 6 5 C3 4 3 2 1 0 0 A~ ~A Table 4–20.
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Instruction Classification Table 4–20. Class 3 Instruction Description (Continued) C3 Mnemonic Description 0 1 0 0 0 XOR An[~], An~, An [, next A] XORS An[~], An~, An Logically exclusive OR accumulator with offset accumulator and store the results in accumulator (~A=0 or 1). ALU status is modified. 0 1 0 0 1 OR An[~], An~, An [, next A] ORS An[~], An~, An Logically OR accumulator with offset accumulator and store results into accumulator (~A=0 or 1). ALU status is modified.
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Instruction Classification Table 4–20. Class 3 Instruction Description (Continued) C3 Mnemonic Description 1 0 1 0 0 MOV SV, An[~] [, next A] MOVS SV, An[~] Transfer accumulator(A~=0) or offset accumulator (A~=1) to SV register. Transfer status is modified. 1 0 1 0 1 MOV PH, An[~] [, next A] MOVS PH, An[~] Transfer accumulator (A~=0) or offset accumulator (A~=1) to PH register. Transfer status is modified.
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Instruction Classification Table 4–20. Class 3 Instruction Description (Continued) C3 Mnemonic Description 1 1 1 1 0 MUL An[~] [, next A] MULS An[~] Multiply MR register by accumulator (A~=1) or offset accumulator (A~=0) and latch the rounded upper 16 bits of the resulting product into the PH register. 1 1 1 1 1 SHL An[~] [, next A] SHLS An[~] Barrel shift the accumulator (A~=1) or offset accumulator (A~=0) value n bits left (n stored in SV register).
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Instruction Classification Table 4–22. Class 4a Instruction Description C4a Mnemonic Description 0 MOV {adrs}, Rx Store Rx register to data memory referred by addressing mode {adrs}. Modify transfer status. 1 MOV Rx, {adrs} Load Rx with the value in data memory referred by addressing mode {adrs}. Modify transfer status. Table 4–23. Class 4b Instruction Description C4b Mnemonic Description 0 0 ADDB Rx, imm8 Add 8-bit positive constant to Rx register. Modify RX status.
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Instruction Classification 4.4.5 Class 5 Instructions: Memory Reference Class 5 instructions provide transfer to and from data memory and all registers except accumulators and Rx which are included in classes 1 and 4. The registers referenced for both read and write operations are the multiplier register (MR), the product high register (PH), the shift value register (SV), the status register (STAT), the top of stack (TOS), the string register (STR), and the four accumulator pointer registers AP0 to AP3.
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Instruction Classification Table 4–27. Class 5 Instruction Description (Continued) C5 Mnemonic Description 0 1 0 1 1 MOV {adrs}, TOS Store the contents of the top of stack (TOS) register to the data memory location referred by addressing mode {adrs}. Transfer status is modified. 0 1 1 0 0 STAG {adrs} Store 1 to the 17th bit of data memory location referred by {adrs}. Set the tag bit. 0 1 1 0 1 RTAG {adrs} Store 0 to the 17th bit of data memory location referred by {adrs}. Clear the tag bit.
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Instruction Classification Table 4–27. Class 5 Instruction Description (Continued) C5 Mnemonic Description 1 1 1 1 0 RPT {adrs}8 Load repeat counter with lower 8 bits of data memory location referred by addressing mode {adrs}. Interrupts are queued during execution. 1 1 1 1 1 MOV STAT, {adrs} Load status (STAT) register with effective data memory location referred by addressing mode {adrs} (17 bits with TAG). 4.4.
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Instruction Classification Table 4–30. Class 6b Instruction Description C6b Mnemonic Description 0 IN An[~], port6 INS An[~], port6 Transfer the port’s 16-bit value to an accumulator. Port addresses 0–63 are valid. ALU status is modified. 1 OUT port6, An[~] OUTS port6, An[~] Transfer a 16-bit accumulator value to the addressed port. Port addresses 0–63 are valid. Transfer status is modified. 4.4.
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Instruction Classification Table 4–31.
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Instruction Classification Table 4–31.
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Instruction Classification Table 4–33. Class 8a Instruction Description C8a Mnemonic Description 0 0 0 MOV TFn, {flagadrs} Load flag bit (17th bit) from data memory referred by flag addressing mode {flagadrs} to either TF1 or TF2 in status register. Load with inverted value if Not =1.
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Instruction Classification Table 4–35. Class 9a Instruction Encoding Bit 16 15 14 13 12 11 10 9 8 7 6 Class 9a 1 1 1 0 1 0 0 An Class 9b 1 1 1 1 1 1 0 C9a Class 9c 1 1 1 1 1 0 1 APn Class 9d 1 1 1 1 1 1 1 1 0 ENDLOOP n 1 1 1 1 1 1 1 1 0 0 0 0 NOP 1 1 1 1 1 1 1 1 1 1 1 1 C9a 5 4 0 3 2 Rx 1 0 1 1 imm8 0 C9c x imm5 C9d 0 0 0 0 1 0 0 0 n 1 1 1 1 1 Table 4–36.
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Bit, Byte, Word and String Addressing Table 4–38. Class 9c Instruction Description C9c Mnemonic Description 0 MOV APn, imm6 Load the accumulator pointer (AP) with a 5-bit constant. 1 ADD APn, imm5 Add a 5-bit constant imm5 to the referenced accumulator pointer(AP). Table 4–39. Class 9d Instruction Description C9d Mnemonic 0 0 0 0 BEGLOOP Description Marks the beginning of loop. Queue interrupts and pushes the next PC value onto a temporary stack location.
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Bit, Byte, Word and String Addressing is a string of bytes. The length of the byte string is stored in the string register (STR). To define the length of a string, the STR register should hold the length of the string minus 2. For example, if the length of a byte string is 10, then STR should be 8. A byte string address can be even or odd. Byte string data is fetched from the lower address (starting address) one byte at a time to consecutive addresses.
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Bit, Byte, Word and String Addressing Flag Address: The flag (or TAG) address uses linear addressing from 0 to the size of data memory in 17-bit wide words (0 to 639 for MSP50P614/ MSP50C614). Only the 17th bit is accessible. When a word memory location is read, the corresponding flag for that location is always loaded into the TAG bit of the status register (STAT). The flag address always corresponds to a 17-bit wide word address.
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Bit, Byte, Word and String Addressing Figure 4–4. Data Memory Example Absolute Word Memory Location Data Memory Location (even) = 2 * (Absolute word memory location) MS Byte LS Byte Data Memory Location (odd) 0x0000 0x0000 0x12 0x34 0x0001 0x0001 0x0002 0x56 0x78 0x0003 0x0002 0x0004 0x9a 0xbc 0x0005 0x0003 0x0006 0xde 0xf0 0x0007 0x0004 0x0008 0x11 0x22 0x0009 0x0005 0x000a 0x33 0x44 0x000b Example 4.5.
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Bit, Byte, Word and String Addressing Example 4.5.7 MOV STR, 4–2 MOV AP0, 2 MOV R0, 0x0001 * 2 MOVBS A0, *R0++ Refer to Figure 4–4 for this example. The word-string length is 4. AP0 points to AC2 accumulator. R0 is loaded with 0x0002. The fourth instruction loads the value of the word-string at the RAM address in R0, 0x0002. R0 autoincrements by 2 after each fetch and stores them into four consecutive accumulators starting from AC2. The result is, AC2 = 0x5678, AC3 = 0x9ABC, AC4 = 0xDEF0, AC5 = 0x1122.
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MSP50P614/MSP50C614 Computational Modes Example 4.5.10 MOV STR, 0 SFLAG *0x00032 MOVS A0, *0x0031 * 2 RFLAG *0x00032 MOVS A0, *0x0031 * 2 Refer to Figure 4–4 for this example. This example is to illustrate the effect of the tag/flag bit when used with a string instruction. The string register (STR) is loaded with 0 (string length of 2). The second instruction sets the flag bit to 1 at flag address 0x0032.
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MSP50P614/MSP50C614 Computational Modes Table 4–41. MSP50P614/MSP50C614 Computational Modes Computational Mode Setting Instruction Resetting Instruction Function Sign extension SXM RXM STAT.XM = 1 produces sign extension on data as it is passed into accumulators. This mode copies the 16th bit of the data in the multiplier/multiplicand to the 17th bit. This causes signed multiplication of two signed numbers. STAT.XM = 0 suppresses sign extension. Unsigned none none STAT.
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MSP50P614/MSP50C614 Computational Modes Example 4.6.2 SXM MOV STR, 2–2 ; string length=2 MOV MR, 0x8000 MOV A0, 0x8000, ++A ; load MS Byte MOV A0, 0x0000, ––A ; load LS Byte MULTPLS A0, A0 This example illustrates the sign extension mode on a string during multiplication. Here, two negative numbers 0x80000000 and 0x8000 are multiplied to obtain a positive number 0x400000000000. If the signs were not extended, we would have obtained 0xC00000000000, a negative number.
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MSP50P614/MSP50C614 Computational Modes Example 4.6.1 SOVM MOV A0, 0x7FFE ADD A0, 5 In this example, we set the overflow mode (OM = 1 of STAT). Adding 0x7FFE with 5 causes an overflow (OF = 1 of STAT). Since the expected result is a positive value, the accumulator saturates to the largest representable value, 0x7FFF. If overflow mode was not set before the ADD instruction, then the accumulator would overflow. Therefore, the result, 0x8003, would be a negative value. Example 4.6.
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Hardware Loop Instructions high word of the result is stored in the PH register and is 0x3FFF. The low word is stored in A0~ as 0x0001. If the two numbers are considered as Q15 fractional numbers (all bits are to the right of the decimal point), then the result will be a Q30 number. To translate a Q30 number back to a Q15 number, first left shift the number (MOV A0,PH, SHL A0,A0), and then truncate the lower word (ignore A0~). When fractional mode is set, the left shift is done automatically (MOV A0,PH).
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Hardware Loop Instructions the execution of a string instruction, interrupts are queued. Queued interrupts are serviced according to their priority after the string operation is complete. In addition to repeat and string instructions, the combination of repeated string instructions has a very useful function. Since there is only one counter to control the hardware repeat count, it is not possible to nest repeats and strings.
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String Instructions 4.8 String Instructions Class 1, 2, 3, and 6 instructions can have string modes. During the execution of string instruction, STR register value plus 2 is assumed as string length. An accumulator string is a group of consecutive accumulators spanning from An to the next N consecutive accumulators (N is the length of the string). The STR register should be loaded with N–2 to define a string length, N.
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String Instructions A1 string is 0x233EFBCA1223 and *0x200 = 0x9086EE3412AC. STR = 3–2=1, defines a string length of 3. Final result, A1~ string = 0x233EFBCA1223 + 0x9086EE3412AC = 0xB3C5E9FE24CF, AC5=0x24CF, AC6=0xE9FE, AC7=0xB3C5, STR=2 (unchanged). Notice that this instruction has accumulated a carry. Special String Sequences: There are two string instructions that have a special meaning.
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Lookup Instructions 4.9 Lookup Instructions Table lookup instructions transfer data from program memory (ROM) to data memory or accumulators. These instructions are useful for reading permanent ROM data into the user program for manipulation. For example, lookup tables can store initial filter coefficients, characters for an LCD display which can be read for display in the LCD screen, etc. There are four lookup instructions as shown in Table 4–44.
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Lookup Instructions Lookup instructions make use of the data pointer (DP) internally. The DP stores the address of the program memory location, loads the value to the destination, and increments it automatically after every load. Thus, the value of the DP is always the last used program memory address plus one. The content of DP changes after the execution of lookup instructions. If filter instructions FIRK and CORK are used, it is required to context save DP in the interrupt service routine.
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Input/Output Instructions 4.10 Input/Output Instructions The MSP50P614/MSP50C614 processor communicates with other on-chip logic as well as external hardware through a parallel I/O interface. Up to 40 I/O ports are addressable with instructions that provide bidirectional data transfer between the I/O ports and the accumulators. Data input is performed with the IN instruction (Class 6). This instruction uses a memory address and a 4-bit port address.
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Special Filter Instructions N tap filters ideally require 2N multiply–accumulates. Four instructions are provided to compute this equation: FIR, FIRK, COR and CORK. All filter instructions require overflow modes to be reset since these instructions have built in overflow hardware. In addition, these instructions must be used with a RPT instruction. FIR and FIRK instructions perform 16-x-16 bit multiplies and 32-bit accumulation in 2 clock cycles (per tap).
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Special Filter Instructions theory requires). The second to last RAM location in the circular buffer is tagged using an STAG instruction. Below is an example of how to set up circular buffering with FIR or COR. When using the FIR or COR instruction with circular buffering, RAM needs to be allocated for the circular buffer and the filter coefficients.
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Special Filter Instructions After the FIR or COR instruction executes, the new startOfBuff will be the last location in the circular buffer. After another FIR/COR instruction, the new startOfBuff will be the second to last location in the circular buffer, and so on. The second detail is the STAT register. The STAT register must be saved immediately after every FIR or COR instruction. Consequently, this saved value must be loaded before every FIR or COR instruction.
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Special Filter Instructions mov mov mov A0,*nextSample ;Replace last sample with newest sample *R0,A0 ; and update the start of the *startOfBuff,R0 ; circular buffer to here (R0) First, the overflow mode must be reset. Next, R5 must be loaded with the wrap around value of the circular buffer. Wrap around happens automatically. This tells the processor how many words to step back when the end of the circular buffer is reached.
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Special Filter Instructions Any combination of registers different from the above will yield incorrect results with the FIR/COR instruction. tag 0x0106 0x010 x[k–3] x[k–2] x[k] x[k–1] Use R5 to wrap around R0 0x0100 0x0102 After FIR/COR execution The STAT register is saved in the filterSTAT_tag location. The output of the filtering operation in the example is located in AC0 (lower word) and AC1 (high word). This 32-bit result is stored in the SampleOut RAM location.
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Special Filter Instructions Important Note About Setting the STAT Register It is very important to consider the initial value of the filterSTAT_tag variable. Failure to set up the filterSTAT_tag variable can cause incorrect results in FIR/ COR operations. Overflow mode must always be reset. The overflow bit of the STAT register may not be set. For samples or filter coefficients that are signed, the sign extension mode bit must also be set.
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Special Filter Instructions mov STAT,*filterSTAT_tag rpt firk mov N–2 A0,*R0++ ;Do one sample ––> 32 bit result *filterSTAT_tag,STAT ;save STAT with last filter tag status ;R0 now points to the last sample *ySampleOut,A0 ;FIR outputs bits 0–15 in AC0, 16–32 in AC1 movs mov A0,*nextSample mov mov *R0,A0 *startOfBuff,R0 ;load STAT with last filter tag status ;Replace last sample with newest sample and update ; the start of the ; circular buffer to here (R0) The set up for the FIRK/CORK instruction
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Special Filter Instructions Figure 4–6.
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Special Filter Instructions Figure 4–7.
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Conditionals 4.12 Conditionals The condition bits in the status register (STAT) are used to modify program control through conditional branches and calls. Various combinations of bits are available to provide a rich set of conditional operations. These condition bits can also be used in Boolean operations to set the test flags TF1 and TF2 in the status register.
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Legend 4.13 Legend All instructions of the MSP50P614/MSP50C614 use the following syntax: name [dest] [, src] [, src1] [, mod] name Name of the instruction. Instruction names are shown in bold letter through out the text. dest Destination of the data to be stored after the execution of the instruction. Optional for some instructions or not used. Destination is also used as both source and destination for some instructions. src Source of the first data. Optional for some instructions or not used.
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Legend Symbol Meaning A~ Select offset accumulator as the source if this bit is 1. Used in opcode encoding only. ~A Select offset accumulator as the destination accumulator if this bit is 1. Used in opcode encoding only. A~ Select offset accumulator as the source if this bit is 0. Used in opcode encoding only. ~A~ Can be either ~A or A~ based on opcode (or instruction). Used in Opcode encoding only. An[~] Can be either An or An~ where n = 0...3 APn Accumulator Pointer register where n = 0..3.
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Legend Symbol Meaning nR Value in repeat counter loaded by RPT instructions ns Value in string register STR OF Overflow flag offset[n] n bit offset from a reference register. OM Overflow mode PC Program counter, 16 bits pma[n] n bit program memory address. For example, pma8 means 8-bit program memory address. If n is not specified, defaults to pma16. port[n] n bit I/O port address. Certain instructions multiply this port address by 4.
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Legend Table 4–45. Auto Increment and Decrement Operation next A No modification b9 b8 0 0 Auto increment ++A 0 1 Auto Decrement – –A 1 0 Table 4–46.
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Individual Instruction Descriptions 4.14 Individual Instruction Descriptions In this section, individual instructions are discussed in detail. Use the conditionals in Section 4.12 and the legend in Section 4.13 to help with individual instruction descriptions.
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Individual Instruction Descriptions 4.14.1 ADD Add word Syntax [label] name dest, src [, src1] [,mod] Clock, clk Words, w With RPT, clk Class ADD An[~], An, {adrs} [, next A] Table 4–46 Table 4–46 Table 4–46 1a ADD An[~], An[~], imm16 [, next A] 2 2 N/R 2b ADD An[~], An[~], PH [, next A] 1 1 nR+3 3 ADD An[~], An~, An [, next A] 1 1 nR+3 3 ADD Rx, imm16 2 2 N/R 4c ADD Rx, R5 1 1 nR+3 4d ADD† APn, imm5 1 1 N/R 9c † Does not affect the status flags.
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Individual Instruction Descriptions Description Syntax Description ADD dest, src ADD src with dest and store the result to dest. ADD dest, src, src1 [,mod] ADD src1 with src and store the result to dest. Premodify the mod before execution. (if provided) See Also ADDB, ADDS, SUB, SUBB, SUBS Example 4.14.1.1 ADD A2~, A2, *R2++R5, ––A Decrement accumulator pointer AP2. Add word at address in R2 to A2, put result in A2~. Add value in R5 to R2 and store in R2. Example 4.14.1.
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Individual Instruction Descriptions 4.14.
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Individual Instruction Descriptions Example 4.14.3.3 ADDS A1, A1~, A1 Add accumulator string A1 to accumulator string A1~, put result in accumulator string A1. Example 4.14.3.4 MULAPL A0, A0~ ADDS A0, A0~, PH The first instruction multiplies MR and A0~, adds PL to A0, and stores the result in A0. The second instruction adds PH to the second word of memory string A0 and puts the result in accumulator string A0. Note that MULAPL and ADDS constitute a special sequence.
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Individual Instruction Descriptions See Also ANDS, ANDB, OR, ORB, ORS, XOR, XORB, XORS Example 4.14.4.1 AND A3, *R4— – And word at address in R4 to A3, store result in A3. Decrement value in R4 by 2 (word mode) after the AND operation. Example 4.14.4.2 AND A0~, A0, 0xff0f, – –A Predecrement accumulator pointer AP0. And immediate value 0xff0f to register accumulator A0, store result in accumulator A0~. Example 4.14.4.3 AND TF2, *0x0020 AND global flag bit at RAM word location 0x0020 to TF2 in the STAT.
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Individual Instruction Descriptions 4.14.5 ANDB Bitwise AND Byte Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class ANDB An, imm8 1 1 N/R 2a Execution dest ⇐ dest AND src byte PC ⇐ PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 ANDB An, imm8 1 0 1 0 1 0 1 9 8 7 6 An 5 4 3 2 1 0 imm8 Description Bitwise AND src byte and byte stored in dest register and store result in dest register.
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Individual Instruction Descriptions 4.14.
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Individual Instruction Descriptions 4.14.7 BEGLOOP Begin Loop Syntax [label] name Clock, clk Word, w With RPT, clk Class 1 1 N/R 9d BEGLOOP† † Loop must end with ENDLOOP.
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Individual Instruction Descriptions 4.14.
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Individual Instruction Descriptions Note: You can not RET to a RET. For example, the following code can cause problems: CALL RET my sub To eliminate any problem, a NOP (or other code) should be inserted between the CALL and the RET.
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Individual Instruction Descriptions 4.14.9 Ccc Conditional Subroutine Call Syntax [label] name address Ccc† pma16 Clock, clk Word, w With RPT, clk Class 2 2 N/R 7c † Cannot immediately follow a CALL instruction with a return instruction.
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Individual Instruction Descriptions Table 4–48.
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Individual Instruction Descriptions Description If cc condition in Table 4–48 is true, PC + 2 is pushed onto the stack and the second word operand is loaded into the PC. If the condition is false, execution defaults to a NOP. A Ccc instruction cannot be followed by a return (RET) instruction. No restriction applies if IRET is used instead of RET.
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Individual Instruction Descriptions Syntax Alternate Syntax Description CRC pma16 Conditional call on RCF = 1 CRNC pma16 Conditional call on RCF = 0 CRE pma16 CRZ pma16 Conditional call on RZF = 1 (equal)† CRNE pma16 CRNZ pma16 Conditional call on RZF = 0 (not equal)† CXG pma16 CXNLE pma16 Conditional call on transfer greater (signed)† CXNG pma16 CXLE pma16 Conditional call on transfer not greater (signed)† CXS pma16 Conditional call on XSF = 1 CXNS pma16 Conditional call on XSF = 0
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Individual Instruction Descriptions Example 4.14.10.3 CMP R2, 0xfe20 Compare value at R2 to immediate value 0xfe20 and change the STAT flags accordingly. Example 4.14.10.4 CMP R0, R5 Compare value at R0 to R5 and change the STAT flags accordingly.
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Individual Instruction Descriptions 4.14.15 ENDLOOP End Loop Syntax [label] name # Clock, clk Word, w With RPT, clk Class ENDLOOP [n] 1 1 N/R 9d Execution If (R4 ≥ 0) decrement R4 by n (1 or 2) PC ⇐ first address after BEGLOOP else NOP PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENDLOOP n 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 n Description This instruction marks the end of a loop defined by BEGLOOP.
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Individual Instruction Descriptions 4.14.16 EXTSGN Sign Extend Word Syntax [label] name EXTSGN dest [, mod] Clock, clk Word, w With RPT, clk Class 1 1 nR+3 3 An[~] [, next A] Execution [premodify AP if mod specified] new most significant word of dest ⇐ STAT.
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Individual Instruction Descriptions 4.14.17 EXTSGNS Sign Extend String Syntax [label] name EXTSGNS dest Clock, clk Word, w With RPT, clk Class nR+3 1 nR+3 3 An[~] Execution new most significant word of dest ⇐ STAT.SF PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 EXTSGNS An[~] 1 1 1 0 0 1 1 Description 9 8 An 7 6 5 4 3 2 1 0 0 1 1 1 1 0 0 A~ Extend the sign bit (SF) of most significant word an additional 16 bits to the left.
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Individual Instruction Descriptions MOV AP1, 3 ; Point to loc corresponding to ; extended word in acc MOVS A0, *R0 ; R0 POINTS TO VALUE IN MEMORY EXTSGN A1 ; not string version as above Alternatively, the following code can do the same thing but requires more code: MOV AP0, 0 ; POINT TO LSW OF ACCUM STRING MOV AP1, 3 ; Point to loc corresponding to ; extended word in acc ZAC A1 ; INITIALIZE EXTENDED SIGN VALUE as positive MOVS A0, *R0 ; R0 POINTS TO VALUE IN MEMORY JNS POSITIVE ; branch around
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Individual Instruction Descriptions See Also Example 4.14.18.1 RPT, FIRK, COR, CORK RPT 0 FIR A0, *R0 Computes the calculation for 2 tap FIR filter with 32-bit accumulation. See section 4.11 for more detail on the setup of coefficients and sample data.
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Individual Instruction Descriptions 4.14.20 IDLE Halt Processor Syntax [label] name Clock, clk Word, w With RPT, clk Class IDLE 1 1 N/R 9d Execution Stop processor clocks PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IDLE 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 Description Halts execution of processor. An external interrupt wakes the processor.
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Individual Instruction Descriptions 4.14.22 INS Input From Port Into String Syntax [label] name INS src, src1 Clock, clk Word, w With RPT, clk Class nS+2 1 nR+2 6b An[~], port6 Execution dest ⇐ content of port6 PC ⇐ PC + 1 Flags Affected dest is An: OF, SF, ZF, CF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 INS An[~], port6 1 1 1 0 1 1 1 9 8 An 7 6 5 4 port6 3 2 1 0 0 ~A Description Input string from same port, port6, to accumulator string.
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Individual Instruction Descriptions 4.14.23 INTD Interrupt Disable Syntax [label] name Clock, clk Word, w With RPT, clk Class INTD 1 1 N/R 9d Execution STAT.IM ⇐ 0 PC ⇐ PC + 1 Flags Affected None (IM is STAT bit 4) Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTD 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0 0 Description Disables interrupts. Resets bit 4 (the IM, interrupt mask bit) of status register (STAT) to 0. See Also INTE, IRET Example 4.
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Individual Instruction Descriptions 4.14.24 INTE Interrupt Enable Syntax [label] name Clock, clk Word, w With RPT, clk Class INTE 1 1 N/R 9d Execution STAT.IM ⇐ 1 PC ⇐ PC + 1 Flags Affected None (IM is STAT bit 4) Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTE 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 Description Enables interrupts. Sets bit 4 (the IM, interrupt mask bit) of status register (STAT) to 1. See Also INTD, IRET Example 4.
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Individual Instruction Descriptions 4.14.25 IRET Return From Interrupt Syntax [label] name Clock, clk Word, w With RPT, clk Class IRET 2 1 N/R 5 Execution PC ⇐ TOS R7 ⇐ R7 – 2 TOS ⇐ *R7 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRET 1 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 0 See Also RET, CALL, Ccc, INTE, INTD Description Return from interrupt. Pop top of stack to program counter. Example 4.
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Individual Instruction Descriptions Opcode Instructions 16 15 14 13 12 11 10 Jcc pma16 1 0 0 0 0 0 Not x Jcc pma16, Rx++ 1 1 0 0 0 0 0 Not 1 0 0 0 0 0 Not 0 0 0 0 0 Not 5 4 3 2 1 0 0 0 0 0 0 Rx 0 1 Rx 1 0 Rx 1 1 cc cc cc pma16 cc names cc name 6 pma16 x cc 7 cc pma16 x Jcc pma16, Rx++R5 8 pma16 x Jcc pma16, Rx–– 9 Description True condition (Not true condition) Not cc name 0 0 0 0 0 Z NZ Conditional on ZF=1 (Not condition ZF=0)
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Individual Instruction Descriptions cc names cc cc name Description True condition (Not true condition) Not cc name 1 1 1 0 0 reserved 1 1 1 0 1 reserved 1 1 1 1 0 reserved 1 1 1 1 1 reserved Description PC is replaced with second word operand if condition is true (or unconditional). If test condition is false, a NOP is executed.
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Individual Instruction Descriptions Syntax Alternate Instruction Description JRNLZP pma16 [, Rmod] Conditional jump on Rx ≥ 0 after post-mod JRZP pma16 [, Rmod] Conditional jump on Rx = 0 after post-mod JRNZP pma16 [, Rmod] Conditional jump on Rx ≠ 0 after post-mod JS pma16 [, Rmod] Conditional jump on SF = 1 JNS pma16 [, Rmod] Conditional jump on SF = 0 JTAG pma16 [, Rmod] Conditional jump on TAG = 1 JNTAG pma16 [, Rmod] Conditional jump on TAG = 0 JTF1 pma16 [, Rmod] Conditional jump on
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Individual Instruction Descriptions [label] name dest, src, [, next A] Clock, clk Word, w With RPT, clk Class MOV TFn, {cc} [, Rx] 1 1 N/R 8b MOV STR, imm8 1 1 N/R 9b MOV SV, imm4 1 1 N/R 9b MOV APn, imm5 1 1 N/R 9c Execution [premodify AP if mod specified] dest ⇐ src PC ⇐ PC + w Flags Affected dest is An: dest is Rx: dest is {adrs}: src is {adrs} src is {flagadrs} OF, SF, ZF, CF are set accordingly RCF, RZF are set accordingly XSF, XZF are set accordingly TAG bit is set a
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Individual Instruction Descriptions Instructions 16 15 14 13 12 11 10 9 8 7 6 5 MOV Rx, R5 1 1 1 1 1 1 1 0 0 1 1 0 MOV SV, imm4 1 1 1 1 1 1 0 1 0 0 0 0 MOV SV, {adrs}4 1 1 0 1 1 0 0 0 0 x MOV PH, {adrs} 1 1 MOV APn, {adrs} 1 1 0 1 0 1 0 1 MOV {adrs}, PH 1 1 0 1 0 1 0 1 1 0 1 MOV {adrs}, DP 1 1 0 1 0 1 0 1 MOV {adrs}, TOS 1 1 0 1 0 1 0 1 adrs 1 1 1 0 0 0 adrs 1 1 0 1 APn adrs 1 1 1 1 1 1 adrs 1 1
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Individual Instruction Descriptions Description Copy value of src to dest. Premodification of accumulator pointers is allowed with some operand types.
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Individual Instruction Descriptions Syntax Description MOV STR, imm8 Move immediate byte to String Register (STR) MOV APn, imm5 Move immediate 5-bit value to APn register † Accumulator condition flags are modified to reflect the value loaded into either An or An~. ‡ Signed multiplier mode resets UM (bit 1 in status register) to 0 ¶ Load the logic value of the test condition to the TFn bit in the status register (STAT). If the condition is true, TFn=1, else TFn=0.
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Individual Instruction Descriptions Example 4.14.28.13 MOV R1, 0x0200 * 2 Load immediate word memory address 0x0200 to R1. Example 4.14.28.14 MOV R7, (0x0280 – 32) * 2 Load R7 (stack register) with the starting value of stack, i.e., 0x0260. Example 4.14.28.15 MOV *0x0200 * 2, R0 Store R0 to data memory word location 0x0200. Example 4.14.28.16 Transfer R5 to R0. MOV R0, R5 Example 4.14.28.17 MOV AP2, *R3 Copy content of data memory location stored in R3 to accumulator pointer AP2. Example 4.14.28.
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Individual Instruction Descriptions Example 4.14.29.2 MOVB *R2, A0 Copy lower 8 bits of accumulator A0 to the data memory byte pointed by R2. Example 4.14.29.3 MOVB A0, 0xf2 Load accumulator A0 with value of 0xf2. Example 4.14.29.4 MOVB MR, 34 Load MR register with immidiate value of 34 (decimal). Example 4.14.29.5 MOVB R2, 255 Load R2 with immidiate value of 255 (decimal).
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Individual Instruction Descriptions Description Copy value of src string to dest string. Premodification of accumulator pointers is allowed with some operand types.
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Individual Instruction Descriptions 4.14.36 MOVT Move Tag From Source to Destination Syntax [label] name dest, src Clock, clk MOVT {adrs}, TFn Execution dest ⇐ src PC ⇐ PC + w Flags Affected None Word, w Table 4–46 With RPT, clk Class Table 4–46 5 Opcode Instructions 16 15 14 13 12 11 10 9 8 MOVT {adrs}, TFn 1 1 0 1 0 1 1 1 fig x 7 6 5 4 3 2 1 0 adrs dma16 (for direct) or offset16 (long relative) [see section 4.
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Individual Instruction Descriptions Figure 4–8. Valid Moves/Transfer in MSP50P614/MSP50C614 Instruction Set B MR/SV I/O xxxxxx PH xxxx00 S B Immediate B An B Rx S S B ROM B RAM APn STR NOTE: B = Byte move possible. S = String move possible.
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Individual Instruction Descriptions 4.14.39 MULR Multiply (Rounded) With No Data Transfer Syntax [label] name src Clock, clk MULR {adrs} Word, w Table 4–0–46 Execution PH,PL ⇐ MR * src PC ⇐ PC + 1 Flags Affected TAG bit is set accordingly With RPT, clk Class Table 4–0–46 5 Opcode Instructions 16 15 14 13 12 11 10 9 8 MULR [adrs] 1 1 0 1 1 1 0 1 0 x 7 6 5 4 3 2 1 0 adrs dma16 (for direct) or offset16 (long relative) (see Section 4.
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Individual Instruction Descriptions 4.14.40 MULS Multiply String With No Data Transfer Syntax [label] name src MULS An [~] Execution PH,PL ⇐ MR * src string PC ⇐ PC + 1 Flags Affected None Clock, clk Word, w With RPT, clk Class nS+3 1 nR+3 3 Opcode Instructions 16 15 14 13 12 11 10 MULS An[~] 1 1 1 0 0 1 1 9 8 An 7 6 5 4 3 2 1 0 1 1 1 1 0 0 A~ 0 Description Multiply MR and the value in src.
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Individual Instruction Descriptions 4.14.49 NOP No Operation Syntax [label] name Clock, clk Word, w With RPT, clk Class NOP 1 1 nR+3 9d Execution PC ⇐ PC + 1 Flags Affected None (No operation) Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOP 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Description This instruction performs no operation. It consumes 1 clock of execution time and 1 word of program memory. See Also RPT Example 4.14.49.
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Individual Instruction Descriptions See Also ORB, ORS, AND, ANDS, XOR, XORS, NOTAC, NOTACS Example 4.14.52.1 OR A0, *R0++R5 OR accumulator A0 with the value in data memory address stored in R0 and store result in accumulator A0, Add R5 to R0 after execution. Example 4.14.52.2 OR A1, A1, 0xF0FF, ++A Preincrement pointer AP1. OR immediate 0xF0FF to accumulator A1. Store result in accumulator A1. Example 4.14.52.3 OR A1, A1~, A1, ––A Pre–decrement accumulator pointer AP1.
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Individual Instruction Descriptions 4.14.53 ORB Bitwise OR Byte Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class ORB An, imm8 1 1 N/R 2a Execution dest ⇐ dest OR src PC ⇐ PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 ORB An, imm8 1 0 1 0 1 0 0 9 8 An 7 6 5 4 3 2 1 0 imm8 Description Bitwise OR byte of src and dest. Result is stored in dest. Only lower 8 bits of accumulator is affected.
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Individual Instruction Descriptions 4.14.56 OUTS Output String to Port Syntax [label] name dest, src OUTS port6, An[~] Execution port6 ⇐ src PC ⇐ PC + 1 Flags Affected XSF, XZF are set accordingly Clock, clk Word, w With RPT, clk Class nR+2 1 nR+2 6b Opcode Instructions 16 15 14 13 12 11 10 OUTS port6, An[~] 1 1 1 0 1 1 1 9 8 An 7 6 5 4 port6 3 2 1 0 1 ~A Description Output to I/O port.
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Individual Instruction Descriptions 4.14.57 RET Return From Subroutine (CALL, Ccc) Syntax [label] name Clock, clk Word, w With RPT, clk Class RET 1 1 N/R 5 Execution PC ⇐ TOS TOS ⇐ *R7 R7 ⇐ R7 – 2 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RET 1 1 0 1 1 1 1 0 0 0 1 1 1 1 1 1 0 Description Return from call or vectored call. Pop stack to program counter, continue execution.
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Individual Instruction Descriptions 4.14.58 RFLAG Reset Memory Flag Syntax [label] name src RFLAG Clock, clk Word, w With RPT, clk Class 1 1 N/R 8a {flagadrs} Execution memory flag bit at {flagadrs} data memory location ⇐ 0 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 RFLAG {flagadrs} 1 0 0 1 0 0 0 0 1 1 6 5 4 3 2 1 0 flagadrs Description Reset flag at addressed memory location to 0.
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Individual Instruction Descriptions 4.14.59 RFM Reset Fractional Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class RFM 1 1 N/R 9d Execution STAT.FM ⇐ 0 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFM 1 1 1 1 1 1 1 1 0 1 1 0 1 0 0 0 0 Description Resets fractional mode. Clears bit 3 in status register (STAT). Disable multiplier shift mode for unsigned fractional or integer arithmetic.
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Individual Instruction Descriptions 4.14.60 ROVM Reset Overflow Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class ROVM 1 1 N/R 9d Execution STAT.OM ⇐ 0 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFM 1 1 1 1 1 1 1 1 0 1 1 0 1 0 0 0 0 Description Resets overflow mode in status register bit 2 (the OM bit). Disable ALU saturation output (normal mode). See Also SOVM Example 4.14.60.
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Individual Instruction Descriptions 4.14.61 RPT Repeat Next Instruction Syntax [label] name src Clock, clk RPT {adrs}8 RPT imm8 Word, w With RPT, clk Class N/R 5 N/R 9b Table 4–46 1 1 Execution IF RPT {adrs}8 load src to repeat counter. ELSE load imm8 to repeat counter. (mask interrupt) repeat next instruction (repeat counter value + 2) times.
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Individual Instruction Descriptions 4.14.62 RTAG Reset Tag Syntax [label] name dest RTAG {adrs} Clock, clk Word, w Table 4–46 Execution memory tag bit at {adrs} data memory location ⇐ 0 PC ⇐ PC + 1 Flags Affected None With RPT, clk Class Table 4–46 5 Opcode Instructions 16 15 14 13 12 11 10 9 8 RTAG {adrs} 1 1 0 1 0 1 1 0 1 x 7 6 5 4 3 2 1 0 adrs dma16 (for direct) or offset16 (long relative) [see section 4.
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Individual Instruction Descriptions 4.14.63 RXM Reset Extended Sign Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class RXM 1 1 N/R 9d Execution STAT.XM ⇐ 0 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXM 1 1 1 1 1 1 1 1 0 1 0 1 1 0 0 0 0 Description Reset extended sign mode status register bit 0 (the XM bit) to 0. See Also SXM Example 4.14.63.
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Individual Instruction Descriptions 4.14.64 SFLAG Set Memory Flag Syntax [label] name dest SFLAG Clock, clk Word, w With RPT, clk Class 1 1 N/R 8a {flagadrs} Execution memory flag bit at {flagadrs} data memory location ⇐ 1 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 SFLAG {flagadrs} 1 0 0 1 1 1 0 1 0 1 6 5 4 3 2 1 0 flagadrs Description Set flag at addressed memory location.
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Individual Instruction Descriptions 4.14.65 SFM Set Fractional Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class SFM 1 1 N/R 9d Execution STAT.FM ⇐ 1 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXM 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 Description Sets bit 3 (the FM bit) in status register (STAT) to 1. Enable multiplier shift mode for signed fractional arithmetic. Example 4.14.65.
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Individual Instruction Descriptions 4.14.
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Individual Instruction Descriptions 4.14.
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Individual Instruction Descriptions 4.14.
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Individual Instruction Descriptions 4.14.
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Individual Instruction Descriptions 4.14.78 SOVM Set Overflow Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class SOVM 1 1 N/R 9d Execution STAT.OM ⇐ 1 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOVM 1 1 1 1 1 1 1 1 0 1 1 0 1 0 0 0 0 Description Sets overflow mode in status register (STAT) bit 2 to 1. Enable ALU saturation output (DSP mode). See Also ROVM Example 4.14.78.
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Individual Instruction Descriptions 4.14.79 STAG Set Tag Syntax [label] name dest STAG {adrs} Clock, clk Word, w Table 4–46 Execution memory tag bit at address adrs ⇐ 1 PC ⇐ PC + w Flags Affected None With RPT, clk Class Table 4–46 5 Opcode Instructions 16 15 14 13 12 11 10 9 8 STAG {adrs} 1 1 0 1 0 1 1 0 0 x 7 6 5 4 3 2 1 0 adrs dma16 (for direct) or offset16 (long relative) [see section 4.13] Description Sets the tag bit at the addressed memory location.
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Individual Instruction Descriptions 4.14.
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Individual Instruction Descriptions Syntax Description SUB An[~], An, {adrs} [, next A] Subtract effective data memory word from An[~], store result in An SUB An[~], An[~], imm16 [, next A] Subtract immediate word from An[~], store result in An[~] SUB An[~], An[~], PH [, next A] Subtract Product High (PH) register from An[~], store result in An[~] SUB An[~], An, An~ [, next A] Subtract An~ word from An word, store result in An[~] SUB An[~], An~, An [, next A] Subtract An word from An~ word, stor
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Individual Instruction Descriptions Syntax Description SUBS An[~], An, {adrs} Subtract data memory string from An string, store result in An[~] string SUBS An[~], An[~], pma16 Subtract program memory string from An[~] string, store result in An[~] string SUBS An[~], An, An~ Subtract An~ string from An string, store result in An[~] string SUBS An[~], An~, An Subtract An string from An~ string, store result in An[~] string SUBS An[~], An[~], PH Subtract product high (PH) register from An[~] string
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Individual Instruction Descriptions 4.14.83 SXM Set Extended Sign Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class SXM 1 1 N/R 9d Execution STAT.XM ⇐ 1 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SXM 1 1 1 1 1 1 1 1 0 1 0 1 0 0 0 0 0 Description Sets extended sign mode status register (STAT) bit 0 to 1. See Also RXM Example 4.14.83.1 SXM Set XM bit of STAT to 1.
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Individual Instruction Descriptions 4.14.84 VCALL Vectored Call Syntax [label] name dest VCALL Clock, clk Word, w With RPT, clk Class 2 1 N/R 7a vector8 Execution Push PC + 1 PC ⇐ *(0x7F00 + vector8) R7 ⇐ R7 + 2 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 VCALL vector8 1 1 1 1 1 1 1 0 1 7 6 5 4 3 2 1 0 vector8 Description Unconditional vectored call (Macro call).
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Individual Instruction Descriptions 4.14.
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Individual Instruction Descriptions See Also XORB, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, NOTACS Example 4.14.85.1 XOR A1, A1, 0x13FF XOR immediate value 0x13FF to A1 and store result in A1. Example 4.14.85.2 XOR A0, A0, 2, ++A Pre–increment pointer AP0, then XOR immediate value 2 to new A0 and store result in A0. Example 4.14.85.3 XOR A1, A1~, A1 XOR accumulator A1 to accumulator A1~, put result in accumulator A1. Example 4.14.85.
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Individual Instruction Descriptions 4.14.86 XORB Logical XOR Byte Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class XORB An, imm8 1 1 N/R 2a Execution An ⇐ An XOR imm8 PC ⇐ PC + 1 (for two operands) Flags Affected dest is An: OF, SF, ZF, CF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 XORB An, imm8 0 0 1 0 1 1 0 9 8 7 6 5 An 4 3 2 1 0 imm8 Description Bitwise logical XOR lower 8 bits of An and dest byte.
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Individual Instruction Descriptions 4.14.
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Individual Instruction Descriptions 4.14.88 ZAC Zero Accumulator Syntax [label] name dest [, mod] ZAC An[~] [, next A] Execution [premodify AP if mod specified] dest ⇐ 0 PC ⇐ PC + 1 Flags Affected ZF = 1 Instructions 16 15 14 13 12 ZAC An[~] [, next A] 1 1 1 0 0 11 Clock, clk Word, w With RPT, clk Class 1 1 nR+3 3 10 next A 9 8 An 7 6 5 4 3 2 1 0 0 0 0 1 1 0 0 ~A Description Zero the specified accumulator.
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Individual Instruction Descriptions 4.14.89 ZACS Zero Accumulator String Syntax [label] name dest Clock, clk Word, w With RPT, clk Class ZAC An nS+3 1 nR+3 3 Execution dest ⇐ 0 PC ⇐ PC + 1 Flags Affected ZF = 1 Instructions 16 15 14 13 12 11 10 ZACS An[~] 1 1 1 0 0 1 1 9 8 An Description Zero the specified accumulator string. See Also ZAC 7 6 5 4 3 2 1 0 0 0 0 1 1 0 0 ~A Example 4.14.89.
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Instruction Set Encoding 4.
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Instruction Set Encoding Instructions 16 15 14 13 12 11 10 CMP An, {adrs} 0 1 0 1 1 0 0 x CMP An[~], imm16 [, next A] 1 9 8 7 6 5 4 An 3 2 1 0 adrs dma16 (for direct) or offset16 (long relative) [see section 4.
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Instruction Set Encoding Instructions 16 15 14 13 12 11 10 9 8 7 6 5 1 0 JMP pma16, Rx–– 1 0 0 0 0 0 0 1 0 1 0 1 Rx 1 0 JMP pma16, Rx++R5 1 0 0 0 0 0 0 1 0 1 Rx 1 1 0 0 x 1 0 0 0 1 0 0 Jcc pma16 1 0 0 0 0 0 Not 0 An 0 0 0 0 0 Not 1 MOV {adrs}, An[~] [, next A] 0 0 0 0 0 0 0 0 0 0 1 1 A~ 0 MOV An[~], imm16 [, next A] 0 0 0 0 0 Rx 0 1 0 Not Rx 1 0 Rx 1 1 cc 0 Not cc pma16 next A An adrs dma16 (for d
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Instruction Set Encoding Instructions 16 15 14 13 12 11 10 9 8 MOV PH, {adrs} 1 1 0 1 1 0 0 0 1 MOV MR, {adrs} 1 1 0 x 1 1 MOV TOS, {adrs} 1 MOV {adrs}, PH 1 1 0 1 0 1 0 1 0 MOV {adrs}, STR 1 MOV {adrs}, DP 1 1 0 1 0 1 0 1 0 MOV {adrs}, TOS 1 MOV STR, {adrs} 1 1 0 0 0 1 0 1 1 0 1 APn 0 adrs 1 1 1 1 1 1 adrs 1 1 0 0 1 0 adrs 1 0 0 0 0 1 adrs 1 0 1 0 0 0 adrs 1 0 0 0 1 0 adrs 1 0 0 0 1 1 adrs 1 0 1
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Instruction Set Encoding Instructions 16 15 14 MOVB {adrs}, An x MOVB An, imm8 1 0 1 0 0 0 1 An imm8 MOVB MR, imm8 1 0 1 0 1 1 1 An imm8 MOVB Rx, imm8 1 0 1 1 1 0 k4 MOVBS An, {adrs} 0 1 0 0 1 1 1 0 0 1 0 0 0 1 0 9 8 7 6 5 4 3 2 1 0 k3 k2 k7 k6 k5 An Rx k1 k0 adrs 1 0 0 1 An adrs 0 A~ 1 1 An adrs dma16 (for direct) or offset16 (long relative) [see section 4.
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Instruction Set Encoding Instructions 16 15 14 13 12 11 10 9 8 MUL {adrs} 1 1 0 1 1 1 0 1 1 MULR {adrs} 1 1 0 x 7 6 5 4 3 2 1 0 A~ 0 adrs dma16 (for direct) or offset16 (long relative) [see section 4.13] x 1 1 1 0 1 0 adrs dma16 (for direct) or offset16 (long relative) [see section 4.13] MULS An[~] 1 1 1 0 0 1 1 An MULAPL An, {adrs} 0 1 1 0 1 1 0 An x 1 1 1 1 0 0 adrs dma16 (for direct) or offset16 (long relative) [see section 4.
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Instruction Set Encoding Instructions 16 15 14 13 12 11 10 7 6 5 4 3 2 ORS An[~], An[~], pma16 1 1 1 0 0 1 1 An 1 0 0 0 0 1 A~ ~A ORS An[~], An~, An 1 1 1 0 0 1 1 An 0 1 0 0 1 0 A~ ~A OUT port4, {adrs} 1 1 0 0 1 x 9 8 port4 1 0 adrs dma16 (for direct) or offset16 (long relative) [see section 4.
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Instruction Set Encoding Instructions 16 15 14 13 12 11 10 7 6 5 4 3 2 SHLTPLS An[~], An[~] 1 1 1 0 0 1 1 An 1 1 0 1 0 0 A~ ~A SHLAC An[~], An[~] [, next A] 1 1 1 0 0 next A An 0 0 1 1 0 0 A~ ~A SHLACS An[~], An[~] 1 1 1 0 0 1 1 An 0 0 1 1 0 0 A~ ~A SHRAC An[~], An[~] [, next A] 1 1 1 0 0 next A An 0 1 0 1 1 0 A~ ~A SHRACS An[~], An[~] 1 1 1 0 0 1 1 0 1 0 1 1 0 A~ ~A STAG {adrs} 1 1 0 1 0 1 1 x 9 8 An 0 0
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Instruction Set Encoding Instructions 16 15 14 13 12 11 7 6 5 4 3 2 1 0 ZAC An[~] [, next A] 1 1 1 0 0 next A An 0 0 0 1 1 0 0 ~A ZACS An[~] 1 1 1 0 0 1 An 0 0 0 1 1 0 0 ~A cc names cc 10 1 9 8 Description Tr e condition (Not True (N t true tr e condition) cc name Not cc name Z NZ Conditional on ZF=1 (Not condition ZF=0) 0 0 0 0 0 0 0 0 0 1 S NS Conditional on SF=1 (Not condition SF=0) 0 0 0 1 0 C NC Conditional on CF=1 (Not cond
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Instruction Set Summary 4.16 Instruction Set Summary Use the legend in Section 4.13 and the following table to obtain a summary of each instruction and its format. For detail about the instruction refer to the detail description of the instruction.
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Instruction Set Summary name dest [, src] [, src1] [,mod] Clock, clk Words, w With RPT, clk CMP Rx, imm16 2 2 N/R 2b CMP An[~], An[~] [, next A] 1 1 N/R 3 CMP An[~], imm16 [, next A] 2 2 N/R 4c CMP Rx, R5 1 1 N/R 4d CMPB An, imm8 1 1 N/R 2a CMPB Rx, imm8 1 1 N/R 4b CMPS An, {adrs} Table 4–46 1b CMPS An[~], pma16 Table 4–46 Class nS+4 2 N/R 2b nS+3 1 nR+3 3 CMPS An, An~ CMPS An~, An COR An, *Rx 3 1 3(nR+2) 9a CORK An, *Rx 3 1 3(nR+2) 9a
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Instruction Set Summary name dest [, src] [, src1] [,mod] Clock, clk MOV {adrs}, An[~] [, next A] Table 4–46 Table 4–46 1a MOV An[~], {adrs} [, next A] Table 4–46 Table 4–46 1a MOV {adrs}, *An Table 4–46 Table 4–46 1b MOV An[~], imm16 [, next A] 2 2 N/R 2b MOV MR, imm16 [, next A] 2 2 N/R 2b MOV An, An~ [, next A] 1 1 nR+3 3 MOV An[~], PH [, next A] 1 1 nR+3 3 MOV SV, An[~] [, next A] 1 1 nR+3 3 MOV PH, An[~] [, next A] 1 1 nR+3 3 MOV An[~], *An[~] [,
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Instruction Set Summary name dest [, src] [, src1] [,mod] MOV {adrs}, SV Table 4–46 Table 4–46 5 MOV {adrs}, APn Table 4–46 Table 4–46 5 MOV {adrs}, TOS Table 4–46 Table 4–46 5 MOV STR, {adrs} Table 4–46 Table 4–46 5 MOV {flagadrs}†, TFn 1 1 nR+3 8a MOV TFn, {flagadrs}† 1 1 nR+3 8a MOV TFn, {cc} [, Rx] 1 1 N/R 8b MOV STR, imm8 1 1 N/R 9b MOV APn, imm5 1 1 N/R 9c MOVB An, {adrs}† Table 4–46 Table 4–46 1b MOVB {adrs}†, An Table 4–46 Table 4–46 1b
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Instruction Set Summary name dest [, src] [, src1] [,mod] MOVU MR, {adrs} Table 4–46 Table 4–46 5 MOVAPH An, MR, {adrs} Table 4–46 Table 4–46 1b MOVAPHS An, MR, {adrs} Table 4–46 Table 4–46 1b MOVSPH An, MR, {adrs} Table 4–46 Table 4–46 1b MOVSPHS An, MR, {adrs} Table 4–46 Table 4–46 1b MUL An[~] [, next A] nR+3 3 MUL {adrs} Table 4–46 Table 4–46 5 MULR {adrs} Table 4–46 Table 4–46 5 MULS An[~] nR+3 3 MULAPL An, {adrs} Table 4–46 1b MULAPL An[~], An[~] [, n
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Instruction Set Summary name dest [, src] [, src1] [,mod] Clock, clk Words, w With RPT, clk OR TFn, {flagadrs} 1 1 nR+3 8a OR TFn, {cc} [, Rx] 1 1 N/R 8b ORB An, imm8 1 1 N/R 2a ORS An, {adrs} Table 4–46 1b ORS An[~], An[~], pma16 nS+4 2 N/R 2b ORS An[~], An~, An nS+3 1 nR+3 3 OUT port4, {adrs} nR+3 6a OUTS port6, An[~] nR+3 6b RPT {adrs}8 N/R 5 RPT imm8 Table 4–46 Table 4–46 nS+3 1 Table 4–46 Class 1 1 N/R 9b 1 1 N/R 5 1 1 nR+3 8a RFM
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Instruction Set Summary name dest [, src] [, src1] [,mod] SHLTPLS An, {adrs} SHLTPLS An[~], An[~] SHLAC An[~], An[~] [, next A] SHLACS An[~], An[~] SHRAC An[~], An[~] [, next A] SHRACS An[~], An[~] STAG {adrs} SOVM Clock, clk Words, w Table 4–46 With RPT, clk Class Table 4–46 1b nS+3 1 nR+3 3 1 1 nR+3 3 nS+3 1 nR+3 3 1 1 nR+3 3 nS+3 1 nR+3 3 Table 4–46 5 N/R 9d Table 4–46 1a Table 4–46 1 1 SUB An[~], An, {adrs} [, next A] SUB An[~], An[~], imm16 [, nex
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Instruction Set Summary name dest [, src] [, src1] [,mod] XORS An, {adrs} XORS An[~], An[~], pma16 nS+4 XORS An[~], An~, An ZAC An[~] [, next A] ZACS An[~] cc names Clock, clk Words, w With RPT, clk Class Table 4–46 1b 2 N/R 2b nS+3 1 nR+3 3 1 1 nR+3 3 nS+3 1 nR+3 3 Table 4–46 Description p True Condition (Not true condition) cc name Not cc name Z NZ Conditional on ZF=1 (Not condition ZF=0) S NS Conditional on SF=1 (Not condition SF=0) C NC Conditional on CF=1
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Assembly Language Instructions Address Bits Name R/W 0x00 8 Port A Data ( (bidirectional) ) R/W Port A Control R/W 0x04 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 After RESET A7 A6 A5 A4 A3 A2 A1 A0 external input states C C 0x00 B1 B0 external i input states C C 0x00 C1 C0 external input states C C 0x00 D1 D0 external input states bit Ax = 0 ⇒ PAx low bit Ax = 1 ⇒ PAx high C C bit C = 0 ⇒ PAx as input 0x08 0x0C 8 8 Port B Data (bidi i l) (bidirec
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MSP50C614 (MSP50P614) IO Port Description Address Bits Name R/W 0x34 4 DAC Control R/W 0x38 16 Interrupt G General Control R/W 15 14 13 12 11 R/W 7 6 5 4 3 2 1 0 After RESET DM E P1 P0 0x0 DA 0x0000 DA left unchanged E Function P1 P0 DAC bits 0 1 3x Style y DAC 5x Style DAC 0 1 Disable DAC Enable DAC 0 1 0 1 0 8 bit 9 bits 10 bits bi PF D3 CE AR EP AR CE Interrupt Flag Register 8 Drive Mode PD EP F port Pullup Arm bit Comparator PD 0 1 8 9 DM E2
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Assembly Language Instructions Vector Source Trigger Event Priority Comment INT0 0x7FF0 DAC Timer timer underflow used to synch.
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10 kHz Nominal Synthesis Rate (32.768 kHz oscillator reference) DAC Precision IntGenCtrl PDMCD Bit 8 bits 1 0 9 bits 1 0 1 0 Master Clock Rate (Hz) PDM Rate (Hz) CPU Clock Rate (Hz) O tp t Output Sampling Rate (Hz) N mber of Number Instructs btwn DAC Interrupts N mber of Number Instructs btwn 10 kHz Interrupts 1x 0x 13 2.62 M 2.62 M 1.31 M 10.24 k 128 128 2x 0x 26 5.11 M 5.11 M 2.56 M 19.97 k 128 256 4x 0x 4D 10.22 M 10.22 M 5.11 M 39.94 k 128 512 8x 0x 9B 20.
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Instruction Set Summay 4-210 Assembly Language Instructions
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Chapter 5 Code Development Tools This chapter describes the code development tools for the MSP50C6xx family of devices. The MSP50C6xx code development tool is used to compile, assemble, link, and debug programs. A reduced function C compiler, (called C––) is also part of the code development tool. Topic Page 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2 5.2 MSP50C6xx Development Tools Guidelines . . . . . . . . . . . . . . . .
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Introduction 5.1 Introduction The MSP50C6xx code development tool is a system made up of a personal computer (PC), the EMUC6xx software, an MSP scanport interface, and a MSP50P614 connected to the application circuits. EMUC6xx is the software that executes on the PC and provides a user interface to the compiler, assembler, linker, debugger, and MSP50P614 programmer. This software gains access to the MSP50P614 and MSP50C6xx devices through a serial interface, called scanport.
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Introduction Figure 5–1. 10-Pin IDC Connector (top view looking at the board) 10-PIN HEADER (3M PART# 2510–6002UB) 0.35I IDC2X5M IDC2X5M VPP 1 2 RESET PGMPULSE 3 4 SCANCLK GND 5 6 SYNC SCANIN 7 8 N/C SCANOUT 9 10 VDD PAD DIA 0.060I 0.800I HOLE DIA 0.038I 0.1I 0.1I PINOUT DETAILS LAYOUT DETAILS It is also recommended that all production boards provide a method for connecting the MSP50C6xx code development tool to the scanport.
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MSP50C6xx Development Tools Guidelines amplifiers, an 8-position DIP switch and two momentary switches connected to I/O pins. These boards are discussed more in Sections 5.2.2 and 5.2.4. 5.2 MSP50C6xx Development Tools Guidelines This is a summary of the tools needed for code development and speech editing for the MSP50C6xx family of speech processors (MSP50C614, MSP50C605, MSP50C601, and MSP50C604). 5.2.1 Categories of MSP50Cxx Development Tools There are two kinds of tools: 5.2.1.
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MSP50C6xx Development Tools Guidelines - If the user is developing host code to be used with a catalog MSP50C604 operating in slave mode: J Hardware Catalog device SPEECH-EVM† PC50C604† H H H † These items are not needed if the customer designs their own preproduction application boards. ‡ Speech-EVM and EVA50C605 have similar functionality. They both function as basic target boards that support code development. For more information about these boards refer to Section 5.2.2. 5.2.1.
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MSP50C6xx Development Tools Guidelines The emulation personality card, for the speech-EVM, that supports code development on the MSP50C614, MSP50C605, MSP50C601, and MSP50C604 (being used in master mode). A MSP50P614 is used on this board to emulate the MSP50C6xx core. An EPROM is used on the SPEECH-EVM board to emulate the data ROM of the MSP50C601 and the MSP50C605.
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MSP50C6xx Development Tools Guidelines - EVA50C605 (see the following note) Same as SPEECH-EVM. Note: The SPEECH-EVM and EVA50C605 have similar functionality. They both function as basic target boards that support code development. One of the differences is that the SPEECH-EVM has a battery holder, and the EVA50C605 does not. The SPEECH-EVM also has the hardware circuits to drive an 8-Ω speaker using the LM386 or H-bridge option. However, the EVA50C605 can only be used with a 32-Ω speaker (direct drive).
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MSP50C6xx Development Tools Guidelines 5.2.3 Documentation - MSP50C6xx Product Folders http://www.ti.com/sc/docs/products/speechh/index.htm - MSP50C6xx User’s Guide - Datasheet MSP50C614: MSP50C605: MSP50C601: MSP50C604: - Applications Notes Documents that help users in developing code for MSP50C6xx devices are available. - SDS6000 Speech Editing Tool manual Schematics Reference designs/schematics for the daughter cards. Schematics of the SPEECH–EVM and the EVA50C605 are also available. 5.
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MSP50C6xx Development Tools Guidelines 5.3.2 Hardware Tools Setup Step 1: Plug in an appropriate personality card (see the following note) on the SPEECH-EVM or EVA50C605. Note: EPC50C605: developing code for MSP50C604 (in master mode, MSP50C601, MSP50C605, or MSP50C614). EPC50C604: developing code for a custom MSP50C604 used in slave mode. PC50C604: developing host code to be used with a catalog MSP50C604 (slave mode) device.
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MSP50C6xx Development Tools Guidelines Note: There is a three-way switch at the edge of the SPEECH-EVM board. After you apply power to the SPEECH-EVM, you have to turn on the SPEECHEVM. There are two ways to turn on the board depending on the power sources: - If you are using the on board with AAA batteries as the power source, you have to slide the switch to the BATT position to turn on the board.
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Assembler 5.4 Assembler 5.4.1 Assembler Directives Assembler directives are texts which have special meaning to the assembler. Some of these directives are extremely helpful during conditional compiling, debugging, adding additional features to existing codes, multiple hardware development, code release etc. Other directives are an essential part of the assembler to initialize variables with values, assigning symbols to memory locations, assigning origin of a program, etc.
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Assembler | (expression) (~ indicates bitwise complement) symbol is any alphanumeric text starting with an alphabetic character, a number, or an expression. Examples: SYM1 EQU (12 * 256) SYM2 EQU SYM1 * (32 / 4) SYM3 EQU SYM1 * SYM2 – *0x200 From the above example SYM1, SYM2 and SYM3 are symbols for some expression. The grammar for a Symbol is as follows: symbol: expression | symbol Expression Restrictions: It is recommended that a space be inserted between the operator (i.e.
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Assembler #IF expression: The start of a conditional assembly structure expression is an arithmetic expression that can contain symbols. Caution: since conditional assembly is resolved during the first pass of the assembler, no forward referenced symbols should be used in a conditional assembly expression. If an expression is TRUE (non zero), then the lines following this directive are assembled until a #ELSE or a #ENDIF directive is encountered.
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Assembler Example: #IFDEF symbol ; do something here #ELSE ; do other things here #ENDIF #IFNDEF symbol ; do something here #ELSE ; do other things here #ENDIF #START_FT: This directive is created by the C– – compiler when it outputs assembly code to a file. It marks the beginning of the function table used to track function calls and C– – variables in the emulator. Users should NEVER use this directive in an assembly language program. AORG expression: Marks the start of an ABSOLUTE segment code, i.e.
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Assembler END expression: Expression defines the start vector for the current assembly program. This directive generates the following assembly code; AORG 0xFFFF DATA expression which defines the start vector of the program, i.e., the program address where execution begins when the chip is installed. label EQU expression: Associates the value of expression with label. EXTERNAL symbol[,symbol]: This directive is used to indicate to the assembler that one or more symbols are external references, i.e.
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C– – Compiler label RESW expression: This directive is used to reserve the number of words indicated by expression, starting at the current RAM address. label is given the value of the current RAM address. If the current RAM address is not EVEN, the assembler increments it by 1 before allocating the desired amount. (Note that RAM locations are accessed by their BYTE address in MSP50C6xx assembly language, i.e., word 1 is at address 2, etc...) RORG expression: Marks the start of a RELATIVE segment code, i.
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C– – Compiler 5.5.
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C– – Compiler 5.5.4 C– – Directives C– – has a limited number of directives and some additional directives not found in ANSI C compilers. The following directives are recognized by the compiler. 5.5.4.1 #define This directive is used to introduce 2 types of macros, in typical C fashion: Without Arguments: defines a replacement string for a given string Example: #define PI 3.1415926535 Every occurrence of the token PI will henceforth be replaced with the string 3.1415926535.
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C– – Compiler Example: #include “file.h” #include The include directories are defined on the cmm_input structure passed to the compiler. There is no limit to the nesting of include files. 5.5.4.4 #asm All text following this directive is inserted as is in the output file, and is considered as assembly language (hence not compiled). The insertion continues until a #endasm directive is found.
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C– – Compiler /********************************/ /* Prototypes for C– –functions */ /********************************/ cmm_func add_string(int *result,int *str1,int *str2,int lg); cmm_func sub_string(int *result,int *str1,int *str2,int lg); cmm_func mul_string(int *result,int *str1,int mult,int lg1,int lgr); cmm_func umul_string(int *result,int *str1,unsigned int mult,int lg1,int lgr); cmm_func or_string(int *result,int *str1,int *str2,int lg); cmm_func and_string(int *result,int *str1,int *str2,int lg);
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C– – Compiler Although we have tried to keep the differences between regular C and C– – to a minimum, there are still a few that require explanation. 5.5.6 Function Prototypes and Declarations C– – function prototypes and declarations MUST be preceded with the keyword cmm_func. Since all functions return through accumulator A0, all functions are of type integer. The function type may be omitted in the function declaration. If present, it is ignored anyway.
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C– – Compiler 5.5.9 String Functions Arithmetic string functions are special functions that perform string arithmetic. The functions currently implemented are shown in Table 5–1. Table 5–1. String Functions add_string(int *result,int *str1,int *str2,int lg)adds strings str1 and str2, of length lg (+2), and puts the result in string result sub_string(int *result,int *str1,int *str2,int lg) subtracts strings str2 from str1, of length lg (+2), and puts the result in string result.
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C– – Compiler the MSP50C6xx length of the string. It is included in the cmm_macr.h file, and is called STR_LENGTH(lstr). For example, STR_LENGTH(8) is 8–2 = 6. Also note that the user has to supply the length of the input string and the length of the output string in the string multiply operations: the result of multiplying a string by an integer can be one word longer than the input string. Unpredictable results may occur if parameter lgr is not at least equal to lgr+1. 5.5.
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Implementation Details 5.6 Implementation Details This section is C– – specific. 5.6.1 Comparisons We use the CMP instruction for both signed and unsigned comparisons. The two integers a and b to be compared are in A0 and A0~.
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Implementation Details - Unsigned comparison of a and b. (a is in A0, b is in A0~) Assembly Test Condition _ult a= b !AULT _ugt a>b AUGT The small number of comparisons was an invitation to use them as vector calls. We return a 1 or 0 in A0 as the result of the comparison, and also set flag 2 if the comparison is true. The flag is not currently used by the compiler.
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Implementation Details 5.6.2 Division Integer division currently requires the use of several accumulator pointers. We divide a 16 bit integer located in A0 by a 16 bit integer located in A0~. We return the quotient in A0~, and the remainder in A0. We make use of A3~ and A3 for scratch pads. We also set flag 1 if a division by zero is attempted, and zero out the quotient and the remainder in this case. We also use PH for temporary storage of the divisor. 5.6.
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Implementation Details declarations ( or function prototypes) are introduced by the mnemonic cmm_func. We only allow the new style of function declarations /prototypes, where the type of the arguments is declared within the function’s parentheses. For example: cmm_func bidon(int i1,char *i2) is valid, but: cmm_func bidon(i1,i2) int i1,char *i2; is invalid.
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Implementation Details #include “cmm_macr.
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Implementation Details add_string(p,pp,p,lgm1+i+1); } if(sign == –1) { neg_string(pp,p,STR_LENGTH((lgp+2))); copy_string(p,pp,STR_LENGTH((lgp+2))); } free(mm1); free(mm2); free(pp); } cmm_func main(int argc,char *argv) { int m1[4],m2[4],product[9]; xfer_const(m1,M1,STR_LENGTH(4)); xfer_const(m2,M2,STR_LENGTH(4)); string_multiply(product,STR_LENGTH(9),m1,STR_LENGTH(4),m2,STR_LENGTH(4)); } 5.6.
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Implementation Details Here the sub files are inter_ram.irx and asm_ram.irx. The allocation for inter_ram.irx begins at memory location 2. This is because the memory location 0 is reserved for use by the C– – compiler. The allocation for asm_ram.irx begins where the allocation ended for inter_ram.irx. More .irx files can be chained on in this manner, and all of the allocation is kept organized.
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Implementation Details | | | | | | |–––––––––––––––| |–––––––––––––––| |–––––––––––––––| | | | | | | |–––––––––––––––| |–––––––––––––––| |–––––––––––––––| | | | | | | |–––––––––––––––| |–––––––––––––––| |–––––––––––––––| | | | | | | |–––––––––––––––| |–––––––––––––––| |–––––––––––––––| | | | | | | |–––––––––––––––| |–––––––––––––––| |–––––––––––––––| | | | | | | |–––––––––––––––| |–––––––––––––––| |–––––––––––––––| | | | | | |–––––––––––––––| |–––
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Implementation Details | | |––––––––––––––| | R7 |––––––––––––––| | | |––––––––––––––| |R5,R7 | | |––––––––––––––| |––––––––––––––| |––––––––––––––| | | | | | | |––––––––––––––| |––––––––––––––| |––––––––––––––| | | |(old)R5 | R5 | |<– This is the SP |––––––––––––––| |––––––––––––––| |––––––––––––––| before the | | |(old)R5 | R5 | |C function call.
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Implementation Details C to C function return (in ronco_return).
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Implementation Details |––––––––––––––| | | |––––––––––––––| | | |––––––––––––––| | | |––––––––––––––| |(old)R5 | |––––––––––––––| |(old)R5 | |––––––––––––––| |Return Addr | |––––––––––––––| |Return Addr | |––––––––––––––| |Param 2 | |––––––––––––––| |Param 2 | |––––––––––––––| |Param 1 | |––––––––––––––| |Param 1 | |––––––––––––––| R7,R5 |Stack data | |––––––––––––––| SUBB R7,4 5-34
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Implementation Details C to ASM function call. The stack is shown after the operation on the bottom is performed.
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Implementation Details | | |––––––––––––––| | | |––––––––––––––| | | | | |––––––––––––––| | | |––––––––––––––| R7 |Return Addr | |––––––––––––––| |Return Addr | |––––––––––––––| |Param 2 | |––––––––––––––| |Param 2 | |––––––––––––––| |Param 1 | |––––––––––––––| |Param 1 | |––––––––––––––| R5 |Stack data | |––––––––––––––| Function call 5-36
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C– – Efficiency C to ASM function return | | |––––––––––––––| | | | | |––––––––––––––| |––––––––––––––| | | | | |––––––––––––––| |––––––––––––––| | | | | |––––––––––––––| |––––––––––––––| | | | | |––––––––––––––| |––––––––––––––| |Return Addr |Return Addr | | |––––––––––––––| |––––––––––––––| |Return Addr |Return Addr | |Param 2 | | |––––––––––––––| |Param 2 | |––––––––––––––| |––––––––––––––| |Param 2 |Param 2 | | |––––––––––––––| |––––––––––––––| |Param 1
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C– – Efficiency repetition), but for loops are implemented with much greater overhead (one conditional jump and three unconditional jumps per repetition.) For this reason, it is best to replace for loops with while loops. (This was not done in the example projects for the sake of readability and to provide an example of a C– – for loop.) If the number of repetitions is both fixed and small, the code will execute faster if the loop is unwrapped. Switch statements and if-else blocks have similar overhead.
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C– – Efficiency 5.7.1 Real Time Clock Example The C– – clock works as follows. The Timer2 ISR is set to fire at 1-second intervals. Inside the ISR a counter is incremented by one each time it fires. An assembly routine in cmm1.asm (_getSecondsPassed) disables the interrupts, retrieves the counter, resets it, and turns the interrupts back on. The C– – program calls getSecondsPassed() whenever it is not busy and uses the return value to update the clock.
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C– – Efficiency - [Root] cmm1.asm cmm1_ram.irx flags.irx main.cmm main.irx main_ram.irx mainasm.asm vroncof2.asm rtc.rpj [modules] [general] init.asm io_ports.irx [isr] tim2_isr.asm J J J J J J J J J J H H - [ram] cmm1.asm cmm1_ram.asm flags.asm main.cmm main.irx main_ram.irx vroncof2.asm rtc.rpj [modules] [general] init.asm io_ports.irx [isr] tim2_isr.asm [ram] ram.h ram.irx 5-40 H H ram.h ram.irx Assembly to support C– – function calls Allocates RAM for use in cmm1.asm Flags used in init.
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C– – Efficiency Seven of the files are important to the functionality of this project. The Timer2 ISR (tim2_isr.asm) forms the basis for the RTC so it will be discussed first.
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C– – Efficiency change is the table of interrupt vectors. At the top of the file is a list of interrupt labels. The ones that are not used are commented out with a semicolon. ; ; ; ; ; ; ; external external external external external external external external DAC_ISR timer1_isr timer2_isr pd2 pd3 portF pd4 pd5 At the bottom of the file are a dummy interrupt routine and the interrupt vector table.
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C– – Efficiency Mainasm.asm contains the most complex assembly. It is responsible for initializing assembly variables, enabling or disabling interrupts, and setting up any timers or I/O ports. It also enables the interrupts. The part that is important to the project, _goasm, is called at the beginning of the C– – main routine.
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C– – Efficiency mov *seconds_passed, a0 inte mov a0, a0~ ret The file only has one C– – callable function, getSecondsPassed. The function reads the value in seconds_passed and returns it in A0. All C– – functions have an underscore preceding their name in assembly. The underscore is ignored when programming in C– –. In C– – a call to this function would look like int result = getSecondsPassed(); Notice that the underscore is not used here because C– – is being used instead of assembly.
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C– – Efficiency ; MAIN.CMM ; Revision 1.00 ****************************************************************/ #include ”ram\ram.h” cmm_func goasm(); // an pseudo main asm routine cmm_func getSecondsPassed(); // Retrieves the counter maintained // by the Timer2 ISR and resets the // counter. int days=0; int hours=12; int minutes=0; int seconds=0; int ampm=0; /************************************************ / Updates time variables for clock ticks that / have occured.
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C– – Efficiency assembly divided by two because C– – integers are 16 bit. The perl script in the main project directory can be used to resize bogus automatically or it can be done manually. To use the perl script, build the project after making any changes to assembly ram allocation. Run the perl script and then rebuild the project. To manually adjust bogus, build the project and then examine the list file mainasm.lst.
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C– – Efficiency - [Root] cmm1.asm cmm1_ram.irx flags.irx main.cmm main.irx main_ram.irx mainasm.asm vroncof2.asm rtc.rpj [dsp] [celp] celp.irx celp4.obj [common] util.obj util2.obj [general] dsp_var.irx dsputil.asm getbits.asm speak.asm speak.irx spk_ram.irx [melp] melp.irx melp.obj [modules] [general] init.asm io_ports.irx sleep.asm [isr] tim2_isr.asm dac_isr.asm tim1_isr.asm [speech] [celp] ampm.qfm days.qfm ones.qfm teens.
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C– – Efficiency tens.qfm H [melp] ampm.qfm days.qfm ones.qfm teens.qfm tens.qfm J [ram] ram.h ram.irx Descriptions of files that are also in Project 1 have been omitted. [dsp] Directory holding files for speech synthesis. [celp] celp.irx celp4.obj [common] util.obj util2.obj [general] dsp_var.irx dsputil.asm getbits.asm speak.asm speak.irx speak_ram.irx [melp] melp.irx melp.obj sleep.asm dac_isr.asm tim1_isr.asm [speech] [celp] [melp] ampm.qfm days.qfm ones.qfm teens.qfm tens.
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C– – Efficiency In main_ram.irx, two variables were added to save and restore r3 and r5 when speaking. These registers are used by C– – so it is a good idea to save and restore them in case they are modified by the speech routines. This is a good example of adding RAM for use by cmm1.asm. ;**************************************************************** ; MAIN_RAM.IRX ; ; Start of memory for MAIN module is defined in ; include ”..\ram\ram.
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C– – Efficiency inte iret Cmm1.asm was modified to include routines for sleeping and speaking from C––. global global global global global global global global _inportD _getSecondsPassed _sleepQuarterSec _speakDays _speakOnes _speakTens _speakTeens _speakAMPM external external sleep_light speak New C– – callable functions were declared global. Assembly routines that will be called are declared external. include include include include include ”speech\celp\days.qfm” ”speech\celp\ones.
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C– – Efficiency DATA DATA DATA DATA DATA DATA DATA MON TUE WED THU FRI SAT SUN ;0 ;1 ;2 ;3 ;4 ;5 ;6 C–– callable speech routines, like the above for speaking days were added. An integer phrase number is passed on the stack. The routines get this value from the stack and do a table lookup to get the address of the correct phrase. The address is loaded into a0 and a0~ is cleared to indicate that the speech data is in internal ROM. Then speak, which is located in speak.asm, is called.
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C– – Efficiency playing. In some cases speech files can be played to debounce keys. This is why there is no delay in the main() function. Pressing SW2 calls a function, but the switch will not be read again until the time has been spoken so there is no need for a delay there. Example 5–3. Third Project (C–– with an LCD) The main difference between this project and the second project is the addition of an LCD display.
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C– – Efficiency melp.irx melp.obj J [modules] H [general] init.asm io_ports.irx sleep.asm H [isr] tim2_isr.asm dac_isr.asm tim1_isr.asm H [lcd] lcd.asm lcd.irx lcd_ram.irx J [speech] H [celp] ampm.qfm days.qfm ones.qfm teens.qfm tens.qfm H [melp] ampm.qfm days.qfm ones.qfm teens.qfm tens.qfm J [ram] ram.h ram.
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C– – Efficiency Descriptions of files that are also in Project 2 have been omitted. [lcd] lcd.asm lcd.irx lcd_ram.irx Directory holding files for writing to an LCD screen. Routines for writing to an LCD screen. Mnemonics used by lcd.asm. Allocates RAM for lcd.asm. The only changes to the assembly are in mainasm.asm and in cmm1.asm. In mainasm.asm, two calls are made to setup and initialize the lcd. To allow this, the labels for the routines were declared external.
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C– – Efficiency writeCharacter(’:’); writeNum(time[WIDTH*0+2]); //seconds writeCharacter(’ ’); if(time[WIDTH*1+1]==0){ //ampm writeCharacter(’A’); } else{ writeCharacter(’P’); } writeCharacter(’M’); writeCharacter(’ ’); switch(time[WIDTH*1+0]){ //days case 0: writeCharacter(’M’); writeCharacter(’O’); writeCharacter(’N’); break; case 1: writeCharacter(’T’); writeCharacter(’U’); writeCharacter(’E’); break; case 2: writeCharacter(’W’); writeCharacter(’E’); writeCharacter(’D’); break; case 3: writeCharacter(’
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C– – Efficiency writeCharacter(’ ’); break; case 1: writeCharacter(’ ’); writeCharacter(’(’); rowOne(); for(temp=0; temp<17; temp++) writeCharacter(’ ’); writeCharacter(’o’); break; case 2: writeCharacter(’ ’); writeCharacter(’|’); rowOne(); for(temp=0; temp<16; temp++) writeCharacter(’ ’); writeCharacter(’o’); writeCharacter(’ ’); break; case 3: writeCharacter(’ ’); writeCharacter(’)’); rowOne(); for(temp=0; temp<15; temp++) writeCharacter(’ ’); writeCharacter(’o’); writeCharacter(’ ’); writeCharacter(’ ’
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Beware of Stack Corruption 5.8 Beware of Stack Corruption MSP50C614/MSP50P614 stack (pointed by R7 register) can easily get corrupted if care is not taken. Notice the following table read code: SUBB R7, 4 MOV A0, *R7–– ADD A0, address MOV A0, *A0 ADD A0, *R7–– MOV A0, *A0 RET This code will work perfectly well if no interrupts happen before SUBB and MOV instruction.
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Reported Bugs With Code Development Tool 5.9 Reported Bugs With Code Development Tool The following are reported bugs for code development tool version 2.39. Breakpoint: Placement of hardware breakpoints is important for reliable operation. Pipeline latency and sleep modes affect the scan logic and prevent hardware breakpoints from working in the following cases. Placing a breakpoint within two cycles of an IDLE instruction causes a breakpoint while the part is still in a low power mode.
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Chapter 6 Applications This chapter contains application information on application circuits, processor initialization sequence, resistor trim setting, synthesis code, memory overlays, and ROM usage. Topic Page 6.1 Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2 6.2 Initializing the MSP50C6xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4 6.3 TI-TALKS Example Code . . . . . . . . . . . . . . . . . . . . .
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Application Circuits 6.1 Application Circuits Figure 6–1. Minimum Circuit Configuration for the C614/P614 Using a Resistor-Trimmed Oscillator To pin 1 of Scan Port Connector† 5V (optional ) To pin 2 of Scan Port Connector† 0.
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Application Circuits It is of particular importance to provide a separate decoupling capacitor for the VDD, VSS pair which services the DAC. These pins are pad numbers 21 and 19, respectively. The relatively high current demands of the digital-to-analog circuitry make this a requirement. An alternate circuit, for better clock-precision and better battery life, includes a crystal oscillator. See Figure 6–2. Figure 6–2.
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Initializing the MSP50C6xx In any MSP50C614 application, it is important for certain components to be located as close as possible to the MSP50C614 die or package. These include any of the decoupling capacitors at VDD (0.1 µF). It also includes all of the components in the crystal-reference network between OSCIN and OSCOUT (22 pF, 10 MΩ, 32 kHz). 6.2 Initializing the MSP50C6xx The initialization code for the MSP50C6xx is in the file INIT.
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Initializing the MSP50C6xx 6.2.1 File init.asm ;**************************************************************** ; INIT.ASM ; ; Revision 1.04 ; ; Modified from revision 1.03: if not CRO, we check port 0x2F ; to distinguish between P and ; C parts. ; ; Turn off TIMER 2 rather than leave it running. ; ; Modified to cope with 6 bit trim value. Top 5 bits go to bits ; 15–11 in ClkSpdCtrl, LSB of trim goes to bit 9 in ClkSpdCtrl. ; ; A fairly basic but compact initialization routine for the 614.
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Initializing the MSP50C6xx mov ap0,0 mov ap1,0 mov ap2,0 mov ap3,0 ;clear ;clear ;clear ;clear accum accum accum accum pointer pointer pointer pointer 0 1 2 3 mov r0,0 mov r1,0 mov r2,0 mov r3,0 mov r4,0 mov r5,0 mov r6,0 mov r7,0 ;clear ;clear ;clear ;clear ;clear ;clear ;clear ;clear register register register register register register register register mov sv,0 ;clear shift value register mov TOS,*0x000 mov PH,*0x000 mov MR,*0x000 ;clear top of stack register ;clear product high register ;cl
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Initializing the MSP50C6xx orb a0,0x7c ;set PLLM for CPU clock of 8 MHz mov *save_clkspdctrl,a0 ;save the ClkSpdCtrl value for later, when ;waking up from mid or deep sleep mov a0~,TIM2REFOSC + TIM2IMR ;disable TIMER 2 out IntGenCtrl,a0~ mov a0~,6553 ;setup a 200 ms period out TIM2,a0~ ;load TIM2 and PRD2 in one fell swoop mov a0~,TIM2ENABLE + TIM2REFOSC + TIM2IMR out IntGenCtrl,a0~ ;use 32 kHz crystal as source, wake up from TIM2 out ClkSpdCtrl,a0 idle nop nop nop ;set clock to full speed! ;go to sleep
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TI-TALKS Example Code 6.3 TI-TALKS Example Code The TI-TALKS code contains the four vocoders (MELP, CELP, ADPCM, and LPC) and demonstrates how to use the interrupts to scan the keys and flash the LEDs. An LCD driver module is also included. TI-TALKS should be used as a starting point for code development. Updates to the vocoders and other modules are sent out by Texas Instruments as necessary. Please contact the TI speech applications group (email: Speak2Me@list.ti.
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RAM Overlay Creating a New Project The easiest way to create a new project is to copy the entire TI–TALKS604 directory into another directory and renaming the project file as desired. It is not necessary to change the paths of the files in the project – this will be done automatically by the code development tool. Note that TI-TALKS604 indicates version 604 of TI-TALKS code. 6.4 RAM Overlay The RAM map for the MSP50C6xx family is quite complex.
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RAM Overlay 6.4.2 RAM Overlay RAM is reserved for variables in the following way. The start address of the variable is equal to the address of the previous variable, plus the size of that variable. The size of VAR1 thus depends on the start address of the next variable. In the example below, dac_buffer starts 2 bytes (one word) after current_buffer. This means that current_buffer must be one word long. The variable after dac_buffer, save_dac_r0, starts 2 bytes (one word) after dac_buffer.
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RAM Overlay save_tim2_stat save_tim2_a0 save_tim2_a0a equ equ equ save_tim1_a0a + 2 * 1 save_tim2_stat + 2 * 1 save_tim2_a0 + 2 * 1 equ equ save_tim2_a0a RAMEND_CUSTOMER – ;End of RAM RAMEND_CUSTOMER RAMLENGTH_CUSTOMER RAMSTART_CUSTOMER After adding new_var the MAIN_RAM.IRX file would look like this: ;**************************************************************** ; MAIN_RAM.IRX ; ; Start of memory for MAIN module is defined in ; include”..\ram\ram.
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6-12
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Chapter 7 Customer Information Customer information regarding package configurations, development cycle, and ordering forms are included in this chapter. Topic Page 7.1 Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2 7.2 Customer Information Fields in the ROM . . . . . . . . . . . . . . . . . . . . . . . 7–11 7.3 Speech Development Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12 7.
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Mechanical Information 7.1 Mechanical Information The MSP50C614, MSP50C605, and the MSP50C601 are normally sold in die form, but are also available in a 100-pin QFP package. The MSP50C604 is a available in die form and in a 64-pin QFP package. The MSP50P614 is available in a 120-pin, PGA-windowed ceramic package. NOTE: Scan Port Bond Out The scan port interface on the MSP50C6xx devices has five dedicated pins and one shared pin that need to be used by the MSP50Cxx code development tools.
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Mechanical Information Table 7–1.
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Mechanical Information Table 7–2.
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Mechanical Information Table 7–3.
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Mechanical Information Table 7–4.
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Mechanical Information Figure 7–1. 100-Pin QFP Mechanical Information 0,38 0,22 0,65 80 0,13 M 51 50 81 12,35 TYP 100 14,20 13,80 17,45 16,95 31 1 30 18,85 TYP 20,20 19,80 23,45 22,95 0,16 NOM Gage Plane 2,90 2,50 0,25 0,25 MIN 0°– 7° 1,03 0,73 Seating Plane 3,40 MAX 0,10 4040022 / B 03/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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Mechanical Information Figure 7–2. 64-Pin QFP Mechanical Information 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP 10,20 SQ 9,80 12,20 SQ 11,80 Gage Plane 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 1,60 MAX 0,08 4040152 / C 11/96 NOTES: A. B. C. D. 7-8 All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 May also be thermally enhanced plastic with leads connected to the die pads.
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Mechanical Information The MSP50C614 is available in a windowed-ceramic, 120-pin, grid array (PGA) packaged for use in software development and prototyping. This PGA package is shown in Figure 7–3. Figure 7–3.
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Mechanical Information Figure 7–4.
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Customer Information Fields in the ROM 7.2 Customer Information Fields in the ROM Customer code information is inserted in the ROM by Texas Instruments. This information appears as seven distinct fields within the ROM test-area. The ROM test-area extends from address 0x0000 to 0x07FF. The code-release information is stored in locations 0x0006 through 0x000C. Assuming these addresses are not specifically read-protected by the ROM security, they are read-accessible to the programmer.
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Speech Development Cycle 7.3 Speech Development Cycle A sample speech development cycle is shown in Figure 7–5. Some of the components, such as speech recording, speech analysis, speech editing, and speech evaluation, require different hardware and software. TI provides a speech development tool, called the SDS6000, which allows the user to perform speech analysis using various algorithms, speech editing for certain algorithms, and to evaluate synthesis results through playback of encoded speech.
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Device Production Sequence TI generates the prototype photomask, then processes, manufactures, and tests prototype devices for shipment to the customer. The number of prototypes is 25, for package sales and 200 for die sales, plus additional units if requested. All prototype devices are shipped with the following disclaimer: It is understood that, for expediency purposes, the initial 25 prototype devices (and any additional prototype devices purchased) were assembled on a prototype (i.e.
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Ordering Information 7.5 Ordering Information Because the MSP50C6xx are custom devices, they receive a distinct identification, as follows: CSM 6xx Gate Code CSM: Custom Synthesizer With Memory Family Member (614, 605, etc.) XXX ROM Code X Revision Letter X Package or Die PJM: Loopin 100-Pin QFP PM: 64-Pin QFP (MSP50C604) Y: Die 7.
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New Product Release Forms (NPRF) NEW PRODUCT RELEASE FORM FOR MSP50C614 SECTION 1. OPTION SELECTION This section is to be completed by the customer and sent to TI along with the microprocessor code and speech data.
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New Product Release Forms (NPRF) 2) The customer approves of the symbolization format in Section 2B. (Applies to packaged devices only). I hereby certify that the TI generated verification data has been checked and found to be correct, and I authorize TI to generate masks, prototypes, and risk units in accordance with purchase order in section 1 above. In addition, in the instance that this is a packaged device, I also authorize TI to use the symbolization format illustrated in section 2B on all devices.
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New Product Release Forms (NPRF) NEW PRODUCT RELEASE FORM FOR MSP50C604 SECTION 1. OPTION SELECTION This section is to be completed by the customer and sent to TI along with the microprocessor code and speech data.
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New Product Release Forms (NPRF) data matches the original data. 2) The customer approves of the symbolization format in Section 2B. (Applies to packaged devices only). I hereby certify that the TI generated verification data has been checked and found to be correct, and I authorize TI to generate masks, prototypes, and risk units in accordance with purchase order in section 1 above.
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New Product Release Forms (NPRF) NEW PRODUCT RELEASE FORM FOR MSP50C605 SECTION 1. OPTION SELECTION This section is to be completed by the customer and sent to TI along with the microprocessor code and speech data.
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New Product Release Forms (NPRF) 2) The customer approves of the symbolization format in Section 2B. (Applies to packaged devices only). I hereby certify that the TI generated verification data has been checked and found to be correct, and I authorize TI to generate masks, prototypes, and risk units in accordance with purchase order in section 1 above. In addition, in the instance that this is a packaged device, I also authorize TI to use the symbolization format illustrated in section 2B on all devices.
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New Product Release Forms (NPRF) NEW PRODUCT RELEASE FORM FOR MSP50C601 SECTION 1. OPTION SELECTION This section is to be completed by the customer and sent to TI along with the microprocessor code and speech data.
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New Product Release Forms (NPRF) 2) The customer approves of the symbolization format in Section 2B. (Applies to packaged devices only). I hereby certify that the TI generated verification data has been checked and found to be correct, and I authorize TI to generate masks, prototypes, and risk units in accordance with purchase order in section 1 above. In addition, in the instance that this is a packaged device, I also authorize TI to use the symbolization format illustrated in section 2B on all devices.
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Appendix AppendixAA Additional Information This appendix contains additional information for the MSP50C6xx mixed-signal processor. Topic A.1 Page Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Additional Information A.1 Additional Information For current information regarding the MSP50C6xx devices (data sheets, development tools, etc.), visit the TI Speech Web site: http://www.ti.