Implementation Guide August 2000 PCI Bus Solutions SCPU007
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete.
Notational Conventions Preface Read This First About This Manual This manual is intended to assist the designer who is attempting to implement a solution using the PCI4450 or PCI4451. Much, but not all, of the information contained herein can also be found elsewhere. However, the smaller size of this manual, as well as its organization by topics of primary interest to the hardware designer, make it a much more usable source regarding those problems most likely to be encountered in the design process.
Contents enter from items that the system displays (such as prompts, command output, error messages, etc.). Here is a sample program listing: 0011 0012 0013 0014 0005 0005 0005 0006 0001 0003 0006 .field .field .field .even 1, 2 3, 4 6, 3 Here is an example of a system prompt and a command that you might enter: C: csr –a /user/ti/simuboard/utilities In syntax descriptions, the instruction, command, or directive is in a bold typeface font and parameters are in an italic typeface.
Trademarks This syntax shows that .byte must have at least one value parameter, but you have the option of supplying additional value parameters, separated by commas. Related Documentation From Texas Instruments PCI4450 GFN/GJG PC Card and OHCI Controller Data Sheet, SCPS046 PCI4451 GFN/GJG PC Card and OHCI Controller Data Manual, SCPS054 OHCI.Lynx Configuration Information Application Report, SLLA077 PHY Layout Recommendations Application Report, SLLA020A TSB41LV03A Data Sheet, SLLS364 http://www.ti.
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Contents Contents 1 PCI445X Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 1.1 System Features Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.1.1 Package Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.1.2 G_RST and PRST . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents A Global Reset Only Bits, PME Context Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.1 Global Reset Only Bits/PME Context Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 B PME and RI Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 B.1 PME and RI Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents Figures 1–1 1–2 1–3 1–4 1–5 1–6 1–7 Typical System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Serialized Interrupt Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 EEPROM 2-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 TPS22X6 Power Switch Interface . . . . . . . . . . . . .
Contents Tables 1–1 1–2 1–3 1–4 1–5 A–1 A–2 B–1 B–2 C–1 C–2 x Registers and Bits Loadable Through Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 PC Card Interface Pullup Register List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 PCI Bus Interface Pullup Register List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 Miscellaneous Terminals Pullup Register List . . . . . . . . . . . . . . . . . .
Chapter 1 PCI445X Device This implementation guide assists platform hardware developers designing with the PCI445X dual socket PC card and 1394 open host controller interface (OHCI) link layer controller (LLC). The PCI445X designation refers to any device in the PCI445X family, for example, the PCI4450 or PCI4451 device.
Figure 1–1 illustrates a platform using the PCI445X device along with the TSB41LV03 3-port PHY, which provides the necessary interface to implement a 3-port IEEE1394 node. Figure 1–1.
System Features Selection 1.1 System Features Selection This section explains selectable system features. Feature selection is required for GPIO and MFUNC terminal assignments and PCI445X register initialization. Detailed system implementation methods are described in the following sections. All functions cannot necessarily be used at the same time, because of the limitations of programmable multifunction terminals (i.e., MFUNC7–MFUNC0). 1.1.
System Features Selection automatically assigned on the dedicated SDA and SCL terminals. A pullup resistor (typically 10 kΩ) must be added on SDA and SCL when using an EEPROM. The value of the pullup resistor can vary for different EEPROMs. Refer to the EEPROM data sheet or contact the manufacturer for the recommended pullup resistor value. 1.1.
System Features Selection 1.1.10 Socket Activity LEDs Socket activity signals can be assigned on MFUNC4 (slot 1), MFUNC3 (slot 2), MFUNC5 (OHCI_LED), MFUNC6 (OHCI_LED), and MFUNC7 (OHCI_LED). 1.1.11 MFUNC7–MFUNC0 Terminal Assignments After selecting required functions for the system, multifunction terminals MFUNC7–MFUNC0 are ready to be assigned. Texas Instruments offers Windows-based software, named TIROUTE.EXE, to assist with terminal assignment. 1.1.12 Miscellaneous Functions Description 1.1.12.
System Features Selection 1.1.12.3 Asynchronous CSC Interrupt Generation The ASYNC_CSC bit (diagnostic register, PCI offset 93h, bit 0) controls the CSC interrupt signaling method. If this bit is set to 0, then CSC is generated synchronously to PCLK (recommended). By default this bit is set to 1, which is the asynchronous mode. 1.1.12.4 CardBus Reserved Terminal Signaling The CardBus interface has reserved terminals. Usually the CardBus controller drives these terminals low.
System Features Selection CCLK can be slowed down rather than stopped by CCLKRUN. If CCLKRUN is set, the CLKCTRLEN (CardBus socket 20h, bit 16) and CLKCTR (CardBus socket 20h, bit 0) bits are both set to 1. The clock is slowed down to 1/16. In this mode the PCI clock is not allowed to stop. 1.1.12.9 SMI A PC card power change event can be reported to the system as SMI (IRQ2 or CSC).
System Implementation 1.2 System Implementation This section describes signal connection for each interface, PCI bus, PC card interface, I2C interface, P2C interface, ZV interface, interrupt interface (parallel and serial), miscellaneous signals, and the PHY-Link interface. It also explains pullup/pulldown resistor requirements. 1.2.1 Clamping Rails The PCI445X device has three clamping rails: VCCA, VCCB, and VCCP. VCCA and VCCB are not power supplies for PC cards.
System Implementation IDSEL, there is no alternative. If another AD line is to be used for IDSEL, then the system designer must leave the pullup off LATCH and use MFUNC7 to route IDSEL. Also, if AD23 is used, then the resistive coupling should not be used. Refer to the Implementation Note: System Generation of IDSEL in the PCI Local Bus Specification, Revision 2.2 (section 3.2.2.3.5). PCI Local Bus Specification, Revision 2.2 (section 4.2.6, footnote 31) recommends resistive coupling.
System Implementation 1.2.3 PC Card Interface The PC Card interface has two modes: the 16-bit interface mode and the CardBus 32-bit interface mode. Damping resistor on CCLK terminal A series-damping resistor is recommended on the CCLK signal. The damping resistor is system dependent. If line impedance is in the 60 – 90-Ω range, a 47-Ω resistor is recommended (see PC Card Standard, Revision 7). CD line filtering PCI445X device has the advanced CDx line filtering circuit.
System Implementation Table 1–1.
System Implementation 1.
System Implementation 1D 0xFF ;11111111 1E 0xFF ;11111111 1F 0xFF ;11111111 20 and 1) 0x00 ;00000000 21 0x12 ;00010010 SubSys Byte 3 ** Insert your SSVID MSB 22 0x34 ;00110100 SubSys Byte 2 ** Insert your SSVID LSB 23 0x56 ;01010110 SubSys Byte 1 ** Insert your SSID MSB 24 0x78 ;01111000 SubSys Byte 0 ** Insert your SSID LSB 25 0x60 ;01100000 SysCtrl Byte 0 26 0xB0 ;10110000 SysCtrl Byte 1 27 0x44 ;01000100 SysCtrl Byte 2 28 0x08 ;00001000 SysCtrl Byte 3 29
System Implementation 1.3.1 P2C Interface for TPS22X6 Power Switch The interface between the PCI445X device and TPS22X6 power switch is serialized to reduce the number of signal lines. The P2C interface requires only three lines to control the switch. As a PCI445X default, the CLOCK signal is selected from an external source. It is usually provided from RTC, 32.768 kHz. The PCI445X device can also generate this clock from an internal ring oscillator.
System Implementation If the third ZV source is not implemented, ZVPCLK and ZVSTAT are not required. To support ZV audio, an audio codec device is required for L and R sound decoding. 1.3.3 Interrupt Signaling Interface Serialized Interrupt Interface The serialized interrupt (ISA and PCI) interface is a single-line interface, IRQSER. A pullup resistor is required on this terminal. The signal is synchronous to PCLK, so PCLK is a required signal. Please remember that SUSPEND gates PCLK internally.
System Implementation Figure 1–6. Distributed DMA Signal Connection PCREQ PCI445X South Bridge PCGNT (ex., PIIX4) 1.3.5 Requirement of Pullup/Pulldown Resistors Note: The PCI445X device has integrated pullup resistors and does not require external pullups. Table 1–2.
System Implementation Table 1–3. PCI Bus Interface Pullup Resistor List PCI Signal Pull-Up Voltage FRAME VCCP TRDY VCCP IRDY VCCP DEVSEL VCCP STOP VCCP SERR VCCP PERR VCCP LOCK VCCP INTA INTB INTC VCCP CLKRUN VCCP PRST VCCP G_RST VCCP PME System dependent The pullup/pulldown on MFUNC depends on how it is implemented. Some signals may require pullups, others pulldowns, and for a GPI or GPO only the system designer would know how that line should be pulled. Table 1–4.
System Implementation Table 1–5. Required Pullup/Pulldown Resistors Signal Resistor Recommended Value (Ω) Condition LPS Pulldown (Default) 1.0 k Required Note: 1-18 All pullup/pulldown resistor value recommendations are provided as guidelines only. The best value for an individual design varies depending upon board characteristics, standard design rules and practices, etc.
System Implementation 1.4 BIOS Considerations 1.4.1 Initialization This section explains which registers require initialization, but does not discuss detailed information about the registers themselves. Refer to the corresponding specifications. Reference white paper: http://www.microsoft.com/hwdev/busbios/cardbus1.htm 1.4.1.
System Implementation against unexpected overwriting. The values are system and vendor dependent. PC Card 16-bit I/F legacy mode base address register (PCI offset 44h: 32-bit) Set to 0000 03E1h (16-bit mode) and set to 0000 0001 (CardBus mode) in response to a disable call. Power management capabilities register (PCI offset A2h: 16-bit) If the system does not support VAUX in D3cold state, then clear bit 15.
System Implementation 2) Register save/restore Register content is not preserved in the sleeping state (it depends on the system implementation). Therefore, BIOS should restore the register content. Under Windows98, most of the register content is saved and restored by the pci.vxd and cbss.vxd.
Important Information 1.5 Important Information This section clarifies important system implementation. 1.5.1 G_RST Clamping Rail G_RST is clamped to VCCP, so removing VCCP causes assertion of G_RST. Figure 1–7. G_RST and VCCP Relationship VCCP VCCP removed VCCP = 0 G_RST G_RST All other signals with clamping rails behave the same way. 1.5.2 PME/RI_OUT Bit Definition If PME is selected, only PME is signaled on the PME/RI_OUT terminal. If RI_OUT is selected, only RI_OUT is signaled.
Global Reset Only Bits/PME Context Bits Appendix A Global Reset Only Bits, PME Context Bits Topic A.
Global Reset Only Bits/PME Context Bits A.1 Global Reset Only Bits/PME Context Bits Table A–1.
Global Reset Only Bits/PME Context Bits Table A–2.
A-4
Appendix B PME and RI Behavior This appendix clarifies PME and RI signal behavior. These signals are important to support the wake-up event from a PC Card (CardBus and 16-bit cards.) Topic B.
B.1 PME and RI Behavior Table B–1.
PCI445X Buffer Types Appendix C PCI445X Buffer Types Topic C.
PCI445X Buffer Types C.1 PCI445X Buffer Types Table C–1.
PCI445X Buffer Types Table C–1.
PCI445X Buffer Types Table C–1.
PCI445X Buffer Types Table C–1.
PCI445X Buffer Types Table C–1. PCI445X Terminal Function Assignment and Buffer Types (Continued) Signal Name Terminal Type Signal Name Terminal Type VCC3.3 U6 P ZV_UV4 W1 TSO VCC3.3 U10 P ZV_UV5 Y1 TSO VCC3.
PCI445X Buffer Types Table C–2. Buffer Type Abbreviations Buffer Type Description I/O Standard input/output I Standard input only O Standard output only OD Open drain P Power, GND, or clamp rail STS Sustained 3-state bidirectional. An active-low signal must be driven high for one cycle before deasserting.
C-8
