User's Manual

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PRODUCT PREVIEW
7.14.3 EMAC Electrical Data/Timing
MRCLK
(Input)
2 3
1
4
4
MTCLK
(Input)
2 3
1
4
4
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
7.14.3.1 EMAC MII and GMII Electrical Data/Timing
Table 7-75. Timing Requirements for MRCLK - MII and GMII Operation (see Figure 7-59 )
-720
-850
-1000
NO. UNIT
1000 Mbps
100 Mbps 10 Mbps
(GMII Only)
MIN MAX MIN MAX MIN MAX
1 t
c(MRCLK)
Cycle time, MRCLK 8 40 400 ns
2 t
w(MRCLKH)
Pulse duration, MRCLK high 2.8 14 140 ns
3 t
w(MRCLKL)
Pulse duration, MRCLK low 2.8 14 140 ns
4 t
t(MRCLK)
Transition time, MRCLK 1 3 3 ns
Figure 7-59. MRCLK Timing (EMAC – Receive) [MII and GMII Operation]
Table 7-76. Timing Requirements for MTCLK - MII and GMII Operation (see Figure 7-60 )
-720
-850
-1000
NO. UNIT
100 Mbps 10 Mbps
MIN MAX MIN MAX
1 t
c(MTCLK)
Cycle time, MTCLK 40 400 ns
2 t
w(MTCLKH)
Pulse duration, MTCLK high 14 140 ns
3 t
w(MTCLKL)
Pulse duration, MTCLK low 14 140 ns
4 t
t(MTCLK)
Transition time, MTCLK 3 3 ns
Figure 7-60. MTCLK Timing (EMAC – Transmit) [MII and GMII Operation]
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