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TMS320C64x DSP

Video Port/VCXO Interpolated Control (VIC) Port

Reference Guide

Literature Number: SPRU629

April 2003

Summary of content (306 pages)

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TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide Literature Number: SPRU629 April 2003
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
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Preface Read This First About This Manual This document describes the video port and VCXO interpolated control (VIC) port in the digital signal processors (DSPs) of the TMS320C6000 DSP family. Notational Conventions This document uses the following conventions. - Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. Related Documentation From Texas Instruments The following documents describe the C6000 devices and related support tools.
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Trademarks Related Documentation From Texas Instruments / Trademarks Code Composer Studio Application Programming Interface Reference Guide (literature number SPRU321) describes the Code Composer Studio application programming interface (API), which allows you to program custom plug-ins for Code Composer. TMS320C6x Peripheral Support Library Programmer’s Reference (literature number SPRU273) describes the contents of the TMS320C6000 peripheral support library of functions and macros.
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Contents Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Provides an overview of the video port peripheral in the digital signal processors (DSPs) of the TMS320C6000 DSP family. Included are an overview of the video port functions, FIFO configurations, and signal mapping. 1.1 1.2 1.3 1.4 2 Video Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents 2.6 2.7 3 2-13 2-13 2-15 2-16 2-17 2-20 2-21 2-24 Video Capture Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Discusses operation of the video capture port. 3.1 3.2 3.3 3.4 3.5 3.6 3.7 vi Video Port Throughput and Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.1 Video Capture Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents 3.8 3.9 3.10 3.11 3.12 3.13 3.14 SPRU629 TSI Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.1 TSI Capture Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.2 TSI Data Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.3 TSI Capture Error Detection . . . . . . . . . . . . . . . . . . . . . . . .
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Contents 4 viii Video Display Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Discusses the video display port. 4.1 Video Display Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.1 Image Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.2 Video Display Counters . . . . . . . .
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Contents 4.13 4.14 5 4.12.6 Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) . . . . . . . . 4.12.7 Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) . . . . . . . 4.12.8 Video Display Field 2 Vertical Blanking End Register (VDVBLKE2) . . . . . . . . 4.12.9 Video Display Field 1 Image Offset Register (VDIMGOFF1) . . . . . . . . . . . . . . 4.12.10 Video Display Field 1 Image Size Register (VDIMGSZ1) . . . . . . . . . . . . . . . . 4.12.
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Contents 6 VCXO Interpolated Control Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Provides an overview of the VCXO interpolated control (VIC) port. 6.1 6.2 6.3 6.4 6.5 A 6-2 6-3 6-3 6-5 6-5 6-6 6-8 6-9 Video Port Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Describes how to configure the video port in different modes with the help of examples.
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Figures Figures 1–1 1–2 1–3 1–4 1–5 1–6 1–7 1–8 1–9 1–10 2–1 2–2 2–3 2–4 2–5 2–6 3–1 3–2 3–3 3–4 3–5 3–6 3–7 3–8 3–9 3–10 3–11 3–12 3–13 3–14 3–15 3–16 3–17 3–18 3–19 3–20 Video Port Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 BT.656 Video Capture FIFO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 8/10-Bit Raw Video Capture and TSI Video Capture FIFO Configuration . . . . .
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Figures 3–21 3–22 3–23 3–24 3–25 3–26 3–27 3–28 3–29 3–30 3–31 3–32 3–33 3–34 3–35 3–36 3–37 3–38 3–39 3–40 3–41 3–42 3–43 3–44 3–45 3–46 3–47 3–48 4–1 4–2 4–3 4–4 4–5 4–6 4–7 4–8 4–9 4–10 4–11 4–12 4–13 4–14 4–15 4–16 xii 20-Bit Raw Data FIFO Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36 Parallel TSI Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Figures 4–17 4–18 4–19 4–20 4–21 4–22 4–23 4–24 4–25 4–26 4–27 4–28 4–29 4–30 4–31 4–32 4–33 4–34 4–35 4–36 4–37 4–38 4–39 4–40 4–41 4–42 4–43 4–44 4–45 4–46 4–47 4–48 4–49 4–50 4–51 4–52 4–53 4–54 4–55 4–56 4–57 4–58 4–59 4–60 10-Bit Y/C FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-Bit Y/C Dense FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chrominance Resampling . . . .
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Figures 4–61 4–62 4–63 4–64 4–65 4–66 4–67 5–1 5–2 5–3 5–4 5–5 5–6 5–7 5–8 5–9 5–10 5–11 5–12 6–1 6–2 6–3 6–4 6–5 xiv Video Display Clipping Register (VDCLIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-85 Video Display Default Display Value Register (VDDEFVAL) . . . . . . . . . . . . . . . . . . . . . . . . 4-86 Video Display Default Display Value Register (VDDEFVAL)—Raw Data Mode . . . . . . . 4-87 Video Display Vertical Interrupt Register (VDVINT) . . . . . . . . .
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Tables Tables 1–1 1–2 1–3 1–4 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 2–9 3–1 3–2 3–3 3–4 3–5 3–6 3–7 3–8 3–9 3–10 3–11 3–12 3–13 3–14 3–15 3–16 3–17 3–18 3–19 3–20 3–21 3–22 3–23 Video Capture Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Video Display Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 VDIN Data Bus Usage for Capture Modes . . . . . . . . . . . . . . . . . .
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Tables 3–24 3–25 3–26 3–27 3–28 3–29 3–30 3–31 3–32 3–33 3–34 3–35 4–1 4–2 4–3 4–4 4–5 4–6 4–7 4–8 4–9 4–10 4–11 4–12 4–13 4–14 4–15 4–16 4–17 4–18 4–19 4–20 4–21 4–22 4–23 4–24 4–25 xvi TSI Capture Control Register (TSICTL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 3-73 TSI Clock Initialization LSB Register (TSICLKINITL) Field Descriptions . . . . . . . . . . . . . 3-74 TSI Clock Initialization MSB Register (TSICLKINITM) Field Descriptions . . . . . . . . . . . .
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Tables 4–26 4–27 4–28 4–29 4–30 4–31 4–32 4–33 4–34 4–35 4–36 5–1 5–2 5–3 5–4 5–5 5–6 5–7 5–8 5–9 5–10 5–11 5–12 5–13 6–1 6–2 6–3 6–4 6–5 6–6 Video Display Counter Reload Register (VDRELOAD) Field Descriptions . . . . . . . . . . . . 4-83 Video Display Display Event Register (VDDISPEVT) Field Descriptions . . . . . . . . . . . . . 4-84 Video Display Clipping Register (VDCLIP) Field Descriptions . . . . . . . . . . . . . . . . . . . . . .
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Chapter 1 Overview This chapter provides an overview of the video port peripheral in the digital signal processors (DSPs) of the TMS320C6000 DSP family. Included are an overview of the video port functions, FIFO configurations, and signal mapping. Topic Page 1.1 Video Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Video Port FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.
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Video Port 1.1 Video Port The video port peripheral can operate as a video capture port, video display port, or transport stream interface (TSI) capture port. It provides the following functions: - Video capture mode: J Capture rate up to 80 MHz. J Two channels of 8/10-bit digital video input from a digital camera or analog camera (using a video decoder). Digital video input is in YCbCr 4:2:2 format with 8-bit or 10-bit resolution multiplexed in ITU-R BT.656 format.
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Video Port - TSI capture mode: Transport stream interface (TSI) from a front-end device such as demodulator or forward error correction device in 8-bit parallel format at up to 30 Mbytes/sec. - The port generates up to three events per channel and one interrupt to the DSP. A high-level block diagram of the video port is shown in Figure 1–1. The port consists of two channels: A and B. A 5120-byte capture/display buffer is splittable between the two channels.
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Video Port Figure 1–1. Video Port Block Diagram Internal peripheral bus 32 VCLK1 VCLK2 VCTL1 VCTL2 VCTL3 VDIN[19–0] 20 Timing and control logic Memory mapped registers DMA interface 64 BT.656 capture pipeline 10 Y/C video capture pipeline 20 Raw video capture pipeline 20 TSI capture pipeline 8 10 Capture/display buffer (2560 bytes) BT.656 display pipeline 20 Y/C video display pipeline 20 Raw video display pipeline VDOUT[19–0] 20 Channel A BT.
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Video Port FIFO 1.2 Video Port FIFO The video port includes a FIFO to store data coming into or out from the video port. The video port operates in conjunction with DMA transfers to move data between the video port FIFO and external or on-chip memory. You can program threshold settings so DMA events are generated when the video port FIFO reaches a certain fullness (for capture) or goes below a certain fullness (for display).
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Video Port FIFO 1.2.2 Video Capture FIFO Configurations During video capture operation, the video port FIFO has one of four configurations depending on the capture mode. For BT.656 operation, the FIFO is split into channel A and B, as shown in Figure 1–2. Each FIFO is clocked independently with the channel A FIFO receiving data from the VDIN[9–0] half of the bus and the channel B FIFO receiving data from the VDIN[19–10] half of the bus.
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Video Port FIFO For 8/10-bit raw video, the FIFO is split into channel A and B, as shown in Figure 1–3. Each FIFO is clocked independently with the channel A FIFO receiving data from the VDIN[9–0] half of the bus and the channel B FIFO receiving data from the VDIN[19–10] half of the bus. Each channel’s FIFO has a separate write pointer and read register (YSRCx). The FIFO configuration is identical for TSI capture, but channel B is disabled. Figure 1–3.
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Video Port FIFO For Y/C video capture, the FIFO is configured as a single channel split into separate Y, Cb, and Cr buffers with separate write pointers and read registers (YSRCA, CBSRCA, and CRSRCA). Figure 1–4 shows how Y data is received on the VDIN[9–0] half of the bus and Cb/Cr data is received on the VDIN[19–10] half of the bus and demultiplexed into the Cb and Cr buffers. Figure 1–4.
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Video Port FIFO For 16/20-bit raw video, the FIFO is configured as a single buffer, as shown in Figure 1–5. The FIFO receives 16/20-bit data from the VDIN[19–0] bus. The FIFO has a single write pointer and read register (YSRCA). Figure 1–5. 16/20-Bit Raw Video Capture FIFO Configuration Capture FIFO VDIN[19–0] 64 16/20 YSRCA Data Buffer (5120 bytes) 1.2.3 Video Display FIFO Configurations During video display operation, the video port FIFO has one of five configurations depending on the display mode.
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Video Port FIFO For 8/10-bit raw video, the FIFO is configured as a single buffer as shown in Figure 1–7. The FIFO outputs data on the VDOUT[9–0] half of the bus. The FIFO has a single read pointer and write register (YDSTA). Figure 1–7. 8/10-Bit Raw Video Display FIFO Configuration Display FIFO VDOUT[9–0] YDSTA 8/10 64 Data Buffer (5120 bytes) For locked raw video, the FIFO is split into channel A and B. The channels are locked together and use the same clock and control signals.
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Video Port FIFO Figure 1–8. 8/10 Bit Locked Raw Video Display FIFO Configuration Display FIFO A VDOUT[9–0] YDSTA 64 8/10 Buffer A (2560 bytes) Display FIFO B VDOUT[19–10] YDSTB 64 8/10 Buffer B (2560 bytes) For 16/20-bit raw video, the FIFO is configured as a single buffer, as shown in Figure 1–9. The FIFO outputs data on VDOUT[19–0]. The FIFO has a single read pointer and write register (YDSTA). Figure 1–9.
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Video Video Port Port Registers FIFO / Video Port Registers For Y/C video display, the FIFO is configured as a single channel split into separate Y, Cb, and Cr buffers with separate read pointers and write registers (YDSTA, CBDST, and CRDST). Figure 1–10 shows how Y data is output on the VDOUT[9–0] half of the bus and Cb/Cr data is multiplexed and output on the VDOUT[19–10] half of the bus. Figure 1–10.
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Video Port Pin Mapping 1.4 Video Port Pin Mapping The video port requires 21 external signal pins for full functionality. Pin usage and direction changes depend on the selected operating mode. Pin functionality detail for video capture mode is listed in Table 1–1. Pin functionality detail for video display mode is listed in Table 1–2. All unused port signals (except VCLK1 and VCLK2) can be configured as general-purpose I/O (GPIO) pins. Table 1–1. Video Capture Signal Mapping Usage BT.
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Video Port Pin Mapping Table 1–2. Video Display Signal Mapping Usage Raw Data Display Mode BT.
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Video Port Pin Mapping 1.4.1 VDIN Bus Usage for Capture Modes The alignment and usage of data on the VDIN bus depends on the capture mode as shown in Table 1–3. Table 1–3. VDIN Data Bus Usage for Capture Modes Capture Mode BT.
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Video Port Pin Mapping 1.4.2 VDOUT Data Bus Usage for Display Modes The alignment and usage of data on the VDOUT bus depends on the display mode as shown in Table 1–4. Table 1–4. VDOUT Data Bus Usage for Display Modes Display Mode BT.
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Chapter 2 Video Port This chapter discusses the basic operation of the video port. Included is a discussion of the sources and types of resets, interrupt operation, DMA operation, external clock inputs, video port throughput and latency, and the video port control registers. Topic Page 2.1 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Reset Operation 2.1 Reset Operation The video port has several sources and types of resets. The actions performed by these resets and the state of the port following the resets is described in the following sections. 2.1.1 Power-On Reset Power-on reset is an asynchronous hardware reset caused by a chip-level reset operation. The reset is initiated by a power-on reset input to the video port.
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Reset Operation If software sets the PEREN bit in PCR but the VPHLT bit in VPCTL remains set: - VCLK1, VCLK2, and STCLK are enabled to the port (allowing logic reset to complete). - Peripheral bus accesses are acknowledged (RREADY/WREADY returned) to prevent DMA lock-up. (Any value returned on reads, data accepted or discarded on writes.) - Peripheral bus MMR interface allows access to all registers.
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Reset Operation Once the port is configured and the VCEN bit is set, the setting of other VCxCTL bits (except VCEN, RSTCH, and BLKCAP) is prohibited and the capture counters begin counting. When BLKCAP is cleared, data capture and event generation may begin. 2.1.5 Display Channel Reset A software reset may be performed on the display channel by setting the RSTCH bit in VDCTL. This reset requires that the channel VCLKIN be transitioning. On display channel reset: - No new DMA events are generated.
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Interrupt Operation 2.2 Interrupt Operation The video port can generate an interrupt to the DSP core after any of the following events occur: - Capture complete (CCMPx) bit is set. Capture overrun (COVRx) bit is set. Synchronization byte error (SERRx) bit is set. Vertical interrupt (VINTxn) bit is set. Short field detect (SFDx) bit is set. Long field detect (LFDx) bit is set. STC absolute time (STC) bit is set. STC tick counter expired (TICK) bit is set. Display complete (DCMP) bit is set.
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DMA Operation 2.3 DMA Operation The video port uses up to three DMA events per channel for a total of six possible events. Each DMA event uses a dedicated event output. The outputs are: - 2.3.1 VPYEVTA VPCbEVTA VPCrEVTA VPYEVTB VPCbEVTB VPCrEVTB Capture DMA Event Generation Capture DMA events are generated based on the state of the capture FIFO(s). If no DMA event is currently pending and the FIFO crosses the value specified by VCTHRLDn, a DMA event is generated.
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DMA Operation Figure 2–1.
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DMA Operation Because the capture FIFOs may hold multiple thresholds worth of data, a problem arises at the boundaries between fields. Since Field 1 and Field 2 may have different threshold values, the amount of data in the FIFO required to generate the DMA event changes depending on the current capture field and the field of any outstanding DMA requests.
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DMA Operation Figure 2–2.
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DMA Operation A DMA event counter is used to track the number of DMA events generated in each field as programmed in the VDDISPEVT register. The DISPEVT1 or DISPEVT2 value (depending on the current display field) is loaded at the start of each field. The event counter then decrements with each DMA event generation until it reaches 0, at which point no more DMA events are generated until the next field begins.
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DMA Operation Similarly if a subhorizontal line length is desired (½ line, for example), then the line length and threshold must be chosen such that the threshold is divisible by 2. (This can also be stated as the line length must be an even multiple of #DMAs/line × 8). For the subline case, consider the 8-bit BT.656 capture mode with a line length of 624 (Y). If the threshold is set for ½ the line length, this results in VCTHRLD = (624/2)/8 = 39 doublewords.
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Clocks Clocks / Video Port Functionality Subsets 2.4 Clocks The video port has three external clock inputs as shown in Table 2–1. No synchronization is required between the clocks sourced by the external pins. VCLK1 and VCLK2 clock frequencies should be less than the DMA interface clock. On 64x devices, the DMA interface clock is typically ½ the CPU clock so this allows VCLK1 and VCLK2 to run at full frequency unless the 64x CPU is running at less than 220 MHz.
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Video Port Functionality Subsets / Video Port Throughput and Latency 2.5.2 FIFO Size Some low-cost device implementations with narrow video ports width or restricted to lower video frequency operations may use a reduced FIFO size. FIFO size does not affect the DMA request mechanism. The selection of 8-bit or 10-bit port width automatically cuts the FIFO size in half with support for only a single channel of operation. 2.
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Video Port Throughput and Latency Table 2–2. Y/C Video Capture FIFO Capacity Sample 8-Bit 10-Bit Dense 10-Bit Y Samples 2560 1920 1280 Cb Samples 1280 960 640 Cr Samples 1280 960 640 Using these values and the formula above, the maximum time to empty the FIFO (tO) may be calculated for each case. The DMA output rate (rO) is then calculated as the FIFO size divided by tO : 8-bit (n = 1): tO < tF + n(tH) tO < 2560/74.25 MHz + 1(3.77 µs) tO < 38.3 µs rO = tO/5120 = 7.
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Video Port Throughput and Latency 2.6.2 Video Display Throughput Video display throughput may be calculated in a manner similar to video capture. In this case, the time to fill the display FIFO must be less than the time to empty the FIFO or underflow occurs. The 110 MHz display rate supports a maximum display resolution of 1280 × 1024 at 63 Hz (frame rate). This means that the horizontal blanking time is ~3.88 µs.
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Video Port Control Registers A DMA write throughput of at least 330 MBytes/s is required for the highest display rate operation supported by 20-bit implementations of the video port. C64x devices including the video port typically have more than enough DMA bandwidth to support this throughput requirement. However when using multiple high-bandwidth peripherals together, it is important to consider the total DMA throughput required by the peripherals being used concurrently. 2.
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Video Port Control Registers 2.7.1 Video Port Control Register (VPCTL) The video port control register (VPCTL) determines the basic operation of the video port. The VPCTL is shown in Figure 2–3 and described in Table 2–5. Not all combinations of the port control bits are unique. The control bit encoding is shown in Table 2–6. Additional mode options are selected using the video capture channel A control register (VCACTL) and video display control register (VDCTL). Figure 2–3.
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Video Port Control Registers Table 2–5. Video Port Control Register (VPCTL) Field Descriptions (Continued) Bit field† 14 VPHLT 13–8 Reserved 7 VCLK2P 6 5 4 3 symval† Value Video port halt bit. This bit is set upon hardware or software reset. The other VPCTL bits (except VPRST) can only be changed when VPHLT is 1. VPHLT is cleared by writing a 1. Writing 0 has no effect. NONE 0 CLEAR 1 – 0 Reserved. The reserved bit location is always read as 0.
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Video Port Control Registers Table 2–5. Video Port Control Register (VPCTL) Field Descriptions (Continued) field† Bit 2 symval† Value TSI 1 TSI capture mode select bit. NONE 0 TSI capture mode is disabled. CAPTURE 1 TSI capture mode is enabled. DISP 0 Description Display mode select bit. VDATA pins are configured for output. VCLK2 pin is configured as VCLKOUT output. CAPTURE 0 Capture mode is enabled. DISPLAY 1 Display mode is enabled. DCHNL Dual channel operation select bit.
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Video Port Control Registers 2.7.2 Video Port Status Register (VPSTAT) The video port status register (VPSTAT) indicates the current condition of the video port. The VPSTAT is shown in Figure 2–4 and described in Table 2–7. Figure 2–4. Video Port Status Register (VPSTAT) 31 16 Reserved R-0 15 4 3 2 1 0 Reserved DCDIS HIDATA Reserved R-0 R-x R-x R-0 Legend: R = Read only; -n = value after reset; -x = value is determined by chip-level configuration Table 2–7.
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Video Port Control Registers 2.7.3 Video Port Interrupt Enable Register (VPIE) The video port interrupt enable register (VPIE) enables sources of the video port interrupt to the DSP. The VPIE is shown in Figure 2–5 and described in Table 2–8. Figure 2–5.
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Video Port Control Registers Table 2–8. Video Port Interrupt Enable Register (VPIE) Field Descriptions (Continued) Bit field† 20 VINTB1 19 18 17 16 0 Interrupt is disabled. ENABLE 1 Interrupt is enabled. Channel B synchronization error interrupt enable bit. DISABLE 0 Interrupt is disabled. ENABLE 1 Interrupt is enabled. Capture complete on channel B interrupt enable bit. DISABLE 0 Interrupt is disabled. ENABLE 1 Interrupt is enabled.
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Video Port Control Registers Table 2–8. Video Port Interrupt Enable Register (VPIE) Field Descriptions (Continued) Bit field† 10 STC 9–8 7 6 5 4 3 2 1 0 Reserved symval† Value Description System time clock interrupt enable bit. DISABLE 0 Interrupt is disabled. ENABLE 1 Interrupt is enabled. – 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. LFDA Long field detected on channel A interrupt enable bit.
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Video Port Control Registers 2.7.4 Video Port Interrupt Status Register (VPIS) The video port interrupt status register (VPIS) displays the status of video port interrupts to the DSP. The interrupt is only sent to the DSP if the corresponding enable bit in VPIE is set. All VPIS bits are cleared by writing a 1, writing a 0 has no effect. The VPIS is shown in Figure 2–6 and described in Table 2–9. Figure 2–6.
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Video Port Control Registers Table 2–9. Video Port Interrupt Status Register (VPIS) Field Descriptions (Continued) Bit field 22 SFDB symval Value Description Short field detected on channel B interrupt detected bit. BT.656 or Y/C capture mode – SFDB is set when short field detection is enabled and VCOUNT is reset before VCOUNT = YSTOP. Raw data mode, or TSI capture mode or display mode – Not used. 21 NONE 0 No interrupt is detected. CLEAR 1 Interrupt is detected. Bit is cleared.
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Video Port Control Registers Table 2–9. Video Port Interrupt Status Register (VPIS) Field Descriptions (Continued) Bit field 18 CCMPB symval Value Description Capture complete on channel B interrupt detected bit. (Data is not in memory until the DMA transfer is complete.) BT.656 or Y/C capture mode – CCMPB is set after capturing an entire field or frame (when F1C, F2C, or FRMC in VCBSTAT are set) depending on the CON, FRAME, CF1, and CF2 control bits in VCBCTL.
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Video Port Control Registers Table 2–9. Video Port Interrupt Status Register (VPIS) Field Descriptions (Continued) Bit field 13 DCMP symval Value Description Display complete. Indicates that the entire frame has been driven out of the port. The DMA complete interrupt can be used to determine when the last data has been transferred from memory to the FIFO.
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Video Port Control Registers Table 2–9. Video Port Interrupt Status Register (VPIS) Field Descriptions (Continued) Bit field 7 LFDA symval Value Description Long field detected on channel A interrupt detected bit. (A long field is only detected when the VRST bit in VCACTL is cleared to 0; when VRST = 1, a long field is always detected.) BT.656 or Y/C capture mode – LFDA is set when long field detection is enabled and VCOUNT is not reset before VCOUNT = YSTOP + 1.
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Video Port Control Registers Table 2–9. Video Port Interrupt Status Register (VPIS) Field Descriptions (Continued) Bit 3 field symval Value SERRA Description Channel A synchronization error interrupt detected bit. BT.656 or Y/C capture mode – Synchronization parity error on channel A. An SERRA typically requires resetting the channel (RSTCH) or the port (VPRST). Raw data mode or TSI capture mode – Not used. 2 NONE 0 No interrupt is detected. CLEAR 1 Interrupt is detected. Bit is cleared.
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Chapter 3 Video Capture Port Video capture works by sampling video data on the input pins and saving it to the video port FIFO. When the amount of captured data reaches a programmed threshold level, a DMA is performed to move data from the FIFO into DSP memory. In some cases, color separation is performed on the incoming video data requiring multiple FIFOs and DMAs to be used. The video port enables capture of both interlaced and progressive scan data.
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Video Capture Mode Selection 3.1 Video Capture Mode Selection The video capture module operates in one of nine modes as listed in Table 3–1. The transport stream interface (TSI) selection is made using the TSI bit in the video port control register (VPCTL). The CMODE bits are in the video capture channel x control register (VCxCTL). The Y/C and 16/20-bit raw capture modes may only be selected for channel A and only if the DCHNL bit in VPCTL is cleared to 0.
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BT.656 Video Capture Mode 3.2 BT.656 Video Capture Mode The BT.656 capture mode captures 8-bit or 10-bit 4:2:2 luma and chroma data multiplexed into a single data stream. Video data is conveyed in the order Cb,Y,Cr,Y,Cb,Y,Cr, etc. where the sequence Cb,Y,Cr refers to co-sited luma and chroma samples and the following Y value corresponds to the next luminance sample.
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BT.656 Video Capture Mode 3.2.2 BT.656 Timing Reference Codes For standard digital video, there are two reference signals, one at the beginning of each video data block (start of active video, SAV), and one at the end of each video block (end of active video, EAV). (Technically each line begins with the SAV code and ends just before the subsequent EAV code.) Each timing reference signal consists of a four sample sequence in the following format: FF.Ch 00.0h 00.0h XY.0h.
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BT.656 Video Capture Mode Bits P0, P1, P2, and P3 have different states depending on the state of bits F, V, and H as shown in Table 3–3. Table 3–3. BT.
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BT.656 Video Capture Mode Table 3–4.
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BT.656 Video Capture Mode Figure 3–1. Video Capture Parameters Hcount=0 Ycount=1 Ystart Xstart Capture Image Ystop Xstop Field 1 Ycount=1 Ystart Xstart Capture Image Ystop Xstop Field 2 Table 3–5 shows common digital camera standards and the number of fields per second, number of active lines per field, and the number of active pixels per line. Table 3–5.
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BT.656 Video Capture Mode For the BT.656 video capture mode, the FIFO buffer is divided into three sections (three buffers). One section is 1280 bytes deep and is dedicated for storage of Y data samples. The other two sections are dedicated for storage of Cb and Cr data samples, respectively. The buffers for Cb and Cr samples are each 640 bytes deep. The incoming video data stream is separated into Y, Cb, and Cr data streams, scaled (if selected), and the Y, Cb, and Cr buffers are filled.
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BT.656 Video Capture Mode 3.2.5 BT.656 FIFO Packing Captured data is always packed into 64-bits before being written into the capture FIFO(s). The packing and byte ordering is dependant upon the capture data size and the device endian mode. For little-endian operation (default), data is packed into the FIFO from right to left; for big-endian operation, data is packed from left to right. The 8-bit BT.656 mode uses three FIFOs for color separation.
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BT.656 Video Capture Mode The 10-bit BT.656 mode uses three FIFOs for color separation. Two samples are packed into each word with zero or sign extension as shown in Figure 3–3. Figure 3–3. 10-Bit BT.
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BT.656 Video Capture Mode The 10-bit BT.656 dense mode uses three FIFOs for color separation. Three samples are packed into each word with zero extension to provide increased DMA bandwidth as shown in Figure 3–4. Figure 3–4. 10-Bit BT.
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Y/C Video Capture Mode 3.3 Y/C Video Capture Mode The Y/C capture mode is similar to the BT.656 capture mode but captures 8 or 10-bit 4:2:2 data on separate luma and chroma data streams. One data stream contains Y samples and the other stream contains multiplexed Cb and Cr samples co-sited with every other Y sample. The Y samples are written into a Y FIFO and the chroma samples are demultiplexed and written into separate Cb and Cr FIFOs for transfer into Y, Cb, and Cr buffers in DSP memory.
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Y/C Video Capture Mode 3.3.3 Y/C Image Window and Capture The SDTV Y/C format (CCIR601) is an interlaced format consisting of two fields just like BT.656. HDTV Y/C formats may be interlaced or progressive scan. For interlaced capture, the capture windows are programmed identically to BT.656 mode. For progressive scan formats, only field1 is used. In Y/C mode, HCOUNT increments on every luma sample period (every VCLKINA rising edge) for which capture is enabled.
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Y/C Video Capture Mode 3.3.4 Y/C FIFO Packing Captured data is always packed into 64 bits before being written into the capture FIFO(s). The packing and byte ordering is dependant upon the capture data size and the device endian mode. For little-endian operation (default), data is packed into the FIFO from right to left; for big-endian operation, data is packed from left to right. The 8-bit Y/C mode uses three FIFOs for color separation. Four samples are packed into each word as shown in Figure 3–5.
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Y/C Video Capture Mode The 10-bit Y/C mode uses three FIFOs for color separation. Two samples are packed into each word with zero or sign extension as shown in Figure 3–6. Figure 3–6.
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Y/C Video Capture Mode The 10-bit Y/C dense mode uses three FIFOs for color separation. Three samples are packed into each word with zero extension to provide increased DMA bandwidth as shown in Figure 3–7. Figure 3–7.
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BT.656 and Y/C Mode Field and Frame Operation 3.4 BT.656 and Y/C Mode Field and Frame Operation Because DMAs are used to transfer data from the capture FIFOs to memory, there is a large amount of flexibility in the way that capture fields and frames are transferred and stored in memory. In some cases, for example a DMA structure can be created to provide a set of ping-pong or round-robin memory buffers to which a continuous stream of fields are stored without DSP intervention.
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BT.656 and Y/C Mode Field and Frame Operation Table 3–6. BT.656 and Y/C Mode Capture Operation VCxCTL Bit CON FRAME CF2 CF1 Operation 0 0 0 0 Reserved 0 0 0 1 Noncontinuous field 1 capture. Capture only field 1. F1C is set after field 1 capture and causes CCMPx to be set. The F1C bit must be cleared by the DSP before capture can continue. (The DSP has the entire field 2 time to clear F1C before next field 1 begins.) Can also be used for single progressive frame capture.
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BT.656 and Y/C Mode Field and Frame Operation Table 3–6. BT.656 and Y/C Mode Capture Operation (Continued) VCxCTL Bit CON FRAME CF2 CF1 1 0 1 0 Continuous field 2 capture. Capture only field 2. F2C is set after field 2 capture and causes CCMPx to be set (CCMPx interrupt can be disabled). The video port continues capturing field 2 fields, regardless of the state of F2C. 1 0 1 1 Reserved 1 1 0 0 Continuous frame capture. Capture both fields.
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BT.656 and Y/C Mode Field and Frame Operation Table 3–7. Vertical Synchronization Programming VCxCTL Bit VMode EXC VRST Vertical Counter Reset Point 0 0 0 First EAV with V=1 after EAV with V=0 – beginning of vertical blanking period. VCOUNT increments on each EAV. 1 0 1 First EAV with V=0 after EAV with V=1 – first active line. VCOUNT increments on each EAV. 2 1 0 On HCOUNT reset after VCTL2 input active edge – beginning of vertical blanking or vertical sync period.
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BT.656 and Y/C Mode Field and Frame Operation Figure 3–8.
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BT.656 and Y/C Mode Field and Frame Operation 3.4.3 Horizontal Synchronization Horizontal synchronization determines when the horizontal pixel/sample counter is reset. The EXC and HRST bits in VCxCTL allow you to program the event that triggers the start of a line. The encoding of these bits is shown in Table 3–8. Table 3–8. Horizontal Synchronization Programming VCxCTL Bit HMode EXC HRST Horizontal Counter Reset Point 0 0 0 EAV code (H=1) – beginning of horizontal blanking.
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BT.656 and Y/C Mode Field and Frame Operation Figure 3–9. HCOUNT Operation Example (EXC = 0) VCLKIN 4 268 1440 VDIN[9–0] EAV Blanking Data SAV EAV Next Line One Line EXC=0 HRST=0 HCOUNT EXC=0 HRST=1 Active Video 80.0 10.0 FF.C 00.0 00.0 XY.0 Cb 0 Y0 Cr 0 Y1 Cb 1 Y2 FF.C 00.0 00.0 XY.0 80.0 10.0 80.0 10.
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BT.656 and Y/C Mode Field and Frame Operation 3.4.4 Field Identification In order to properly synchronize to the source data stream and capture the correct fields, field identification needs to be performed. Field identification is made using one of three methods: EAV, field indicator input, or field detect logic. The field identification method is determined by the EXC, FLDD, and FINV bits in VCxCTL. Table 3–9.
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BT.656 and Y/C Mode Field and Frame Operation The field detect method uses HYSNC and VSYNC based field detect logic. This is used for BT.656 or Y/C systems that provide only HSYNC and VSYNC. The field detect logic samples the state of the HSYNC input on the VSYNC active edge. If HSYNC is active on the active VSYNC edge, then field 1 is detected; if HSYNC is inactive on the active VSYNC edge, then field 2 is detected.
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Video Input Filtering VCTL2 is a VSYNC (vertical sync) input, then a long field is always detected. (Even if VCYSTOPn is set to the last active line, VCOUNT usually increments past VCYSTOPn + 1 while it counts the vertical front porch lines that occur prior to VSYNC active.) 3.5 Video Input Filtering The video input filter performs simple hardware scaling and resampling on incoming 8-bit BT.656 or 8-bit Y/C data. Filtering hardware is always disabled during 10-bit or raw data capture modes.
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Video Input Filtering 3.5.2 Chrominance Resampling Operation Chrominance resampling computes chrominance values at sample points midway between the input luminance samples based on the input co-sited chrominance samples. This filter performs the horizontal portion of a conversion between YCbCr 4:2:2 format and YCbCr 4:2:0 format. The vertical portion of the conversion must be performed in software.
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Video Input Filtering Figure 3–13. 1/2 Scaled Co-Sited Filtering a b c d e f g h i j k l YCbCr 4:2:2 co-sited input samples 1/2 scaled co-sited capture results (Y) – Luma sample Y’h = (–3Ye+ 32Yg+ 70Yh+ 32Yi – 3Yk) / 128 (Cb/Cr) –Chroma samples Y’f = (–3Yc+ 32Ye+ 70Yf+ 32Yg – 3Yi) / 128 Cb’f = (–1Cbc+ 17Cbe+ 17Cbg – 1Cbi ) / 32 Cr’f = (–1Crc+ 17Cre+ 17Crg – 1Cri ) / 32 Figure 3–14.
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Video Input Filtering 3.5.4 Edge Pixel Replication Because the filters make use of preceding and trailing samples, filtering artifacts can occur at the beginning of the BT.656 or Y/C active line because no samples exist before the SAV code, and at the end of the BT.656 active line because no samples exist after the EAV code.
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Video Input Filtering Figure 3–16 shows an example of a capture window that is smaller than the BT.656 active line. Sample a is the first sample in the horizontal capture window and sample n is the last sample. In this case, any filtering done on the first sample location uses the m leading edge captured pixels (m is 3 in this example), and any filtering done on the last sample location uses the m trailing captured pixels.
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Ancillary Data Capture 3.6 Ancillary Data Capture The BT.656 and some Y/C specifications includes provision for carrying ancillary (nonvideo) data within the horizontal and vertical blanking regions. Horizontal ancillary (HANC) data appears between the EAV code and SAV codes. Vertical ancillary (VANC) data, also called vertical blanking interval (VBI) data, appears during the active horizontal line portion of vertically blanking (for example, after an SAV with V = 1). 3.6.
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Raw Data Capture Mode 3.7 Raw Data Capture Mode In the raw data capture mode, the data is sampled by the interface only when the CAPEN signal is active. Data is captured at the rate of the sender’s clock, without any interpretation or start/stop of capture based on the data values. To ensure initial capture synchronization to the beginning of a frame, an optional setup synchronization enable (SSE) bit is provided in VCxSTRT1.
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Raw Data Capture Mode Table 3–11. Raw Data Mode Capture Operation VCxCTL Bit CON FRAME CF2 CF1 Operation 0 0 x x Noncontinuous frame capture. FRMC is set after data block capture and causes CCMPx to be set. Capture will halt upon completion of the next frame unless the FRMC bit is cleared. (DSP has the entire next frame time to clear FRMC.) 0 1 x x Single frame capture. FRMC is set after data block capture and causes CCMPx to be set. Capture is halted until the FRMC bit is cleared.
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Raw Data Capture Mode The 8-bit raw-data mode stores all data in a single FIFO. Four samples are packed into each word as shown in Figure 3–17. Figure 3–17.
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Raw Data Capture Mode The 10-bit dense raw data mode stores all data into a single FIFO. Three samples are packed into each word with zero extension as shown in Figure 3–19. Figure 3–19.
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Raw Data Capture Mode The 20-bit raw data mode stores all data into a single FIFO. One sample is placed right justified in each word and zero or sign extended as shown in Figure 3–21. Figure 3–21.
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TSI Capture Mode 3.8 TSI Capture Mode The transport stream interface (TSI) capture mode captures MPEG-2 transport data. 3.8.1 TSI Capture Features The video port TSI capture mode supports the following features: - Supports SYNC detect using the PACSTRT input from a front-end device. Data capture at the rising edge of incoming VCLK1. Parallel data reception. Maximum data rate of 30 Mbytes/second. Programmable packet size. Hardware counter mechanism to timestamp incoming packet data.
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TSI Capture Mode Figure 3–22. Parallel TSI Capture VCLKIN CAPEN PACSTRT VDIN[9:2] ÉÉÉ ÉÉÉ Sync Byte Byte 1 Start Capture 3.8.3 Byte 2 Byte 3 ÉÉÉÉ ÉÉÉÉ Byte 4 TSI Capture Error Detection The video port checks for two types of errors during TSI capture. The first is a packet error on the incoming packet as indicated by an active PACERR signal.
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TSI Capture Mode Figure 3–23. Program Clock Reference (PCR) Header Format 47 15 14 9 8 Reserved PCR 0 PCR extension The video port, in conjunction with the VCXO interpolated control (VIC), allows a combined hardware and software solution to synchronize the local system time clock (STC) with the encoder time clock reference transmitted in the bit stream. The video port maintains a hardware counter that counts the system time.
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TSI Capture Mode The system time clock counter is initialized by software with the PCR of the first packet with a PCR header. After initialization, the counter can be reinitialized by software upon detecting a discontinuity in subsequent packet PCR header values. The system time is made available to the DSP at any time through the system time clock registers (TSISTCLKL and TSISTCLKM).
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TSI Capture Mode 3.8.6 Writing to the FIFO The captured TSI packet data and the associated timestamps are written into the receive FIFO. The packet data is written first, followed by the timestamp. The FIFO controller controls both data writes and timestamp writes into the FIFO. The FIFO data packing is shown in Figure 3–25. Figure 3–25.
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Capture Line Mode Boundary Conditions TSI Capture / Capture Line Boundary Conditions Figure 3–27. TSI Timestamp Format (Big Endian) 63 56 55 48 47 PCR(15–8) PCR(7–0) 31 25 PCR extension (6–0) 15 PCR(23–16) 24 32 PCR(31–24) 23 18 17 PCR32 Reserved 8 Reserved 3.8.7 40 39 7 6 PERR PSTERR 16 PCR ext (8–7) 5 0 Reserved Reading from the FIFO The YSRCA location is associated with the TSI capture buffer.
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Capture Line Boundary Conditions In Figure 3–28 (8-bit Y/C mode), the line length is not a doubleword. When the condition HCOUNT = VCXSTOP occurs, the FIFO location is written even though 8 bytes have not been received. The next capture line then begins in the next FIFO location at byte 0. This operation extends to all capture modes. In the case of TSI and raw data modes, there are no lines.
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Capturing Video in BT.656 or Y/C Mode 3.10 Capturing Video in BT.656 or Y/C Mode In order to capture video in the BT.656 or Y/C format, the following steps are needed: 1) Set the last pixel to be captured in VCxSTOP1 and VCxSTOP2 (set the VCXSTOP and VCYSTOP bits). 2) Set the first pixel to be captured in VCxSTRT1 and VCxSTRT2 (set the VCXSTART and VCYSTART bits). 3) Write to VCxTHRLD to set the capture threshold.
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Capturing Video in BT.656 or Y/C Mode 8) Write to VCxCTL to: - Set capture mode (CMODE = 00x for BT.656 input, 10x for Y/C input). Set desired field/frame operation (CON, FRAME, CF2, CF1 bits). Set sync and field ID control (VRST, HRST, FDD, FINV, VCTL1 bits). Set 10-bit pack mode (10BPK bits), if 10-bit operation is selected. Enable scaling (SCALE and RESMPL bits), if desired and using 8-bit data. - Set VCEN bit to enable capture.
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Capturing Video in Raw Data Mode 3.11 Capturing Video in Raw Data Mode In order to capture video in the raw data mode, the following steps are needed: 1) Set VCxSTOP1 to specify size of an image to be captured (VCXSTOP sets the lower 12 bits and VCYSTOP sets the upper 12 bits of the captured image size in pixels). 2) Write to VCxTHRLD to set the capture threshold. Every time the number of received pixels reaches the number specified by the VCTHRLD1 bits, a YEVTx is generated by the video capture module.
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Capturing Video in Raw Data Mode / Capturing Data in TSI Capture Mode 3.11.1 Handling FIFO Overrun Condition in Raw Data Mode In case of a FIFO overrun, the COVRx bit is set in VPIS. This condition initiates an interrupt to the DSP, if the overrun interrupt is enabled (setting the COVRx bit in VPIE enables overrun interrupt). The overrun interrupt routine should set the BLKCAP bit in VCxCTL and it should reconfigure DMA channel settings.
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Capturing Data in TSI Capture Mode 6) Write to TSISTCMPL, TSISTCMPM, TSISTMSKL, and TSISTMSKM if needed to initiate an interrupt, based on STC absolute time. 7) Write to TSITICKS if an interrupt is desired every x cycles of STC. 8) Write to VPCTL to select TSI capture operation (TSI = 1). 9) Write to VPIE to enable overrun (COVRA) and capture complete (CCMPA) interrupts, if desired. 10) Write to VCACTL to set capture mode (CMODE = 010). 11) Set VCEN bit in VCACTL to enable capture.
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Video Capture Registers 3.13 Video Capture Registers The registers for controlling the video capture mode of operation are listed in Table 3–13. See the device-specific datasheet for the memory address of these registers. Table 3–13. Video Capture Control Registers Acronym Register Name Section VCASTAT Video Capture Channel A Status Register 3.13.1 VCACTL Video Capture Channel A Control Register 3.13.2 VCASTRT1 Video Capture Channel A Field 1 Start Register 3.13.
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Video Capture Registers Table 3–13. Video Capture Control Registers (Continued) Acronym Register Name Section TSISTCMPL TSI System Time Clock Compare LSB Register 3.13.16 TSISTCMPM TSI System Time Clock Compare MSB Register 3.13.17 TSISTMSKL TSI System Time Clock Compare Mask LSB Register 3.13.18 TSISTMSKM TSI System Time Clock Compare Mask MSB Register 3.13.19 TSITICKS TSI System Time Clock Ticks Interrupt Register 3.13.20 3.13.
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Video Capture Registers Table 3–14. Video Capture Channel x Status Register (VCxSTAT) Field Descriptions Description Bit field† 31 FSYNC 30 symval† Value TSI Mode CLEARD 0 VCOUNT = VINT1 or VINT2, as selected by the FSCL2 bit in VCxVINT. Not used. Not used. SET 1 VCOUNT = 1 in field 1. Not used. Not used. FRMC Frame (data) captured bit. Write 1 to clear the bit, a write of 0 has no effect. NONE 0 Complete frame has not been captured. Complete data block has not been captured.
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Video Capture Registers Table 3–14. Video Capture Channel x Status Register (VCxSTAT) Field Descriptions (Continued) Description field† symval† 27–16 VCYPOS OF(value) 15–13 Reserved – Bit 12 11–0 Value 0–FFFh 0 VCFLD VCXPOS BT.656 or Y/C Mode Raw Data Mode Current VCOUNT Upper 12 bits of value and the line the data counter. that is currently being received (within the current field). TSI Mode Upper 12 bits of the data counter. Reserved. The reserved bit location is always read as 0.
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Video Capture Registers 3.13.2 Video Capture Channel A Control Register (VCACTL) Video capture is controlled by the video capture channel A control register (VCACTL) shown in Figure 3–30 and described in Table 3–15. Figure 3–30.
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Video Capture Registers Table 3–15. Video Capture Channel A Control Register (VCACTL) Field Descriptions (Continued) Description Bit field† 30 BLKCAP symval† Value BT.656 or Y/C Mode Raw Data Mode TSI Mode Block capture events bit. BLKCAP functions as a capture FIFO reset without affecting the current programmable register values. The F1C, F2C, and FRMC status bits, in VCASTAT, are not updated. Field or frame complete interrupts and vertical interrupts are also not generated.
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Video Capture Registers Table 3–15. Video Capture Channel A Control Register (VCACTL) Field Descriptions (Continued) Description Bit field† 18 FLDD 17 16 15 14–13 symval† Value BT.656 or Y/C Mode Raw Data Mode TSI Mode Field detect method bit. (Channel A only) EAVFID 0 1st line EAV or FID input. Not used. Not used. FDL 1 Field detect logic. Not used. Not used. VRST VCOUNT reset method bit. V1EAV 0 Start of vertical blank (1st V = 1 EAV or VCTL2 active edge) Not used. Not used.
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Video Capture Registers Table 3–15. Video Capture Channel A Control Register (VCACTL) Field Descriptions (Continued) Description Bit field† 12 LFDE 11 10 Value 8 SCALE Raw Data Mode TSI Mode DISABLE 0 Long field detect is disabled. Not used. Not used. ENABLE 1 Long field detect is enabled. Not used. Not used. Short field detect enable bit. DISABLE 0 Short field detect is disabled. Not used. Not used. ENABLE 1 Short field detect is enabled. Not used. Not used.
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Video Capture Registers Table 3–15. Video Capture Channel A Control Register (VCACTL) Field Descriptions (Continued) Description Bit 6 5 4 field† symval† Value FRAME‡ 2–0 CMODE TSI Mode NONE 0 Do not capture frame. Do not capture Do not capture single data block. single packet. FRMCAP 1 Capture frame. Capture single data block. Capture single packet. Capture field 2 bit. NONE 0 Do not capture field 2. Do not capture field 2. Not used. FLDCAP 1 Capture field 2. Capture field 2.
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Video Capture Registers 3.13.3 Video Capture Channel x Field 1 Start Register (VCASTRT1, VCBSTRT1) The captured image is a subset of the incoming image. The video capture channel x field 1 start register (VCASTRT1, VCBSTRT1) defines the start of the field 1 captured image. Note that the size is defined relative to incoming data (before scaling). VCxSTRT1 is shown in Figure 3–31 and described in Table 3–16. In BT.
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Video Capture Registers Table 3–16. Video Capture Channel x Field 1 Start Register (VCxSTRT1) Field Descriptions Description field† symval† 31–28 Reserved – 27–16 VCYSTART OF(value) Bit 15 14–12 11–0 Value 0 0–FFFh SSE BT.656 or Y/C Mode Raw Data Mode TSI Mode Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Starting line number. Not used. Not used. Startup synchronization enable bit. DISABLE 0 Not used.
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Video Capture Registers 3.13.4 Video Capture Channel x Field 1 Stop Register (VCASTOP1, VCBSTOP1) The video capture channel x field 1 stop register (VCASTOP1, VCBSTOP1) defines the end of the field 1-captured image or the end of the raw data or TSI packet. VCxSTOP1 is shown in Figure 3–32 and described in Table 3–17. In raw capture mode, the horizontal and vertical counters are combined into a single counter that keeps track of the total number of samples received.
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Video Capture Registers 3.13.5 Video Capture Channel x Field 2 Start Register (VCASTRT2, VCBSTRT2) The captured image is a subset of the incoming image. The video capture channel x field 2 start register (VCASTRT2, VCBSTRT2) defines the start of the field 2 captured image. (This allows different window alignment or size for each field.) Note that the size is defined relative to incoming data (before scaling). VCxSTRT2 is shown in Figure 3–33 and described in Table 3–18. In BT.
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Video Capture Registers 3.13.6 Video Capture Channel x Field 2 Stop Register (VCASTOP2, VCBSTOP2) The video capture channel x field 2 stop register (VCASTOP2, VCBSTOP2) defines the end of the field 2-captured image. VCxSTOP2 is shown in Figure 3–34 and described in Table 3–19. These registers are not used in raw data mode or TSI mode because their capture sizes are completely defined by the field 1 start and stop registers. Figure 3–34.
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Video Capture Registers 3.13.7 Video Capture Channel x Vertical Interrupt Register (VCAVINT, VCBVINT) The video capture channel x vertical interrupt register (VCAVINT, VCBVINT) controls the generation of vertical interrupts in each field. VCxVINT is shown in Figure 3–35 and described in Table 3–20. In BT.656 or Y/C mode, an interrupt can be generated upon completion of the specified line in a field (end of line when VCOUNT = VINTn). This allows the software to synchronize to the frame or field.
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Video Capture Registers Table 3–20. Video Capture Channel x Vertical Interrupt Register (VCxVINT) Field Descriptions Description Bit field† 31 VIF2 30 symval† TSI Mode 0 Setting of VINT in field 2 is disabled. Not used. Not used. ENABLE 1 Setting of VINT in field 2 is enabled. Not used. Not used. FSCL2 FSYNC bit cleared in field 2 enable bit. NONE 0 FSYNC bit is not cleared. Not used. Not used. FIELD2 1 FSYNC bit is cleared in field 2 instead of field 1. Not used. Not used.
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Video Capture Registers 3.13.8 Video Capture Channel x Threshold Register (VCATHRLD, VCBTHRLD) The video capture channel x threshold register (VCATHRLD, VCBTHRLD) determines when DMA requests are sent. VCxTHRLD is shown in Figure 3–36 and described in Table 3–21. The VCTHRLD1 bits determine when capture DMA events are generated. Once the threshold is reached, generation of further DMA events is disabled until service of the previous event(s) begins (the first FIFO read by the DMA occurs). In BT.
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Video Capture Registers Figure 3–36. Video Capture Channel x Threshold Register (VCATHRLD, VCBTHRLD) 31 26 25 16 Reserved VCTHRLD2 R-0 R/W-0 15 10 9 0 Reserved VCTHRLD1 R-0 R/W-0 Legend: R = Read only; R/W = Read/Write; -n = value after reset Table 3–21. Video Capture Channel x Threshold Register (VCxTHRLD) Field Descriptions Description field† symval† 31–26 Reserved – 25–16 VCTHRLD2 OF(value) 15–10 Reserved – VCTHRLD1 OF(value) Bit 9–0 Value 0 0–3FFh 0 0–3FFh BT.
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Video Capture Registers 3.13.9 Video Capture Channel x Event Count Register (VCAEVTCT, VCBEVTCT) The video capture channel x event count register (VCAEVTCT, VCBEVTCT) is programmed with the number of DMA events to be generated for each capture field. VCxEVTCT is shown in Figure 3–37 and described in Table 3–22. An event counter tracks how many events have been generated and indicates which threshold value (VCTHRLD1 or VCTHRLD2 in VCxTHRLD) to use in event generation and in the outgoing data counter.
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Video Capture Registers 3.13.10 Video Capture Channel B Control Register (VCBCTL) Video capture is controlled by the video capture channel B control register (VCBCTL) shown in Figure 3–38 and described in Table 3–23. Figure 3–38.
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Video Capture Registers Table 3–23. Video Capture Channel B Control Register (VCBCTL) Field Descriptions (Continued) Description Bit field† 30 BLKCAP symval† Value BT.656 or Y/C Mode Raw Data Mode TSI Mode Block capture events bit. BLKCAP functions as a capture FIFO reset without affecting the current programmable register values. The F1C, F2C, and FRMC status bits, in VCBSTAT, are not updated. Field or frame complete interrupts and vertical interrupts are also not generated.
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Video Capture Registers Table 3–23. Video Capture Channel B Control Register (VCBCTL) Field Descriptions (Continued) Description Bit field† 16 HRST 15 14–13 12 11 symval† Value BT.656 or Y/C Mode Raw Data Mode TSI Mode HCOUNT reset method bit. EAV 0 EAV or VCTL1 active edge. Not used. Not used. SAV 1 SAV or VCTL1 inactive edge. Not used. Not used. VCEN Video capture enable bit. Other bits in VCBCTL (except RSTCH and BLKCAP bits) may only be changed when VCEN = 0.
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Video Capture Registers Table 3–23. Video Capture Channel B Control Register (VCBCTL) Field Descriptions (Continued) Description Bit field† 10 RESMPL 9 Reserved 8 SCALE 7 6 5 symval† Value BT.656 or Y/C Mode Raw Data Mode TSI Mode Chroma resampling enable bit. DISABLE 0 Chroma resampling is disabled. Not used. Not used. ENABLE 1 Chroma is horizontally resampled from 4:2:2 co-sited to 4:2:0 interspersed before saving to chroma buffers. Not used. Not used. – 0 Reserved.
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Video Capture Registers Table 3–23. Video Capture Channel B Control Register (VCBCTL) Field Descriptions (Continued) Description Bit field† 4 CF1‡ 3–2 Reserved 1–0 CMODE symval† Value BT.656 or Y/C Mode Raw Data Mode TSI Mode Capture field 1 bit. NONE 0 Do not capture field 1. Not used. Not used. FLDCAP 1 Capture field 1. Not used. Not used. – 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Capture mode select bit.
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Video Capture Registers Table 3–24. TSI Capture Control Register (TSICTL) Field Descriptions Description Bit 31–6 5 4 3 2 1 0 field† symval† Reserved – Value 0 ENSTC TSI Mode Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. System time clock enable bit. HALTED 0 Not used. System time clock input is disabled (to save power). The system time clock counters and tick counter do not increment. CLKED 1 Not used.
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Video Capture Registers 3.13.12 TSI Clock Initialization LSB Register (TSICLKINITL) The transport stream interface clock initialization LSB register (TSICLKINITL) is used to initialize the hardware counter to synchronize with the system time clock. TSICLKINITL is shown in Figure 3–40 and described in Table 3–25. On receiving the first packet containing a program clock reference (PCR) and the PCR extension value, the DSP writes the 32 least-significant bits (LSBs) of the PCR into TSICLKINITL.
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Video Capture Registers 3.13.13 TSI Clock Initialization MSB Register (TSICLKINITM) The transport stream interface clock initialization MSB register (TSICLKINITM) is used to initialize the hardware counter to synchronize with the system time clock. TSICLKINITM is shown in Figure 3–41 and described in Table 3–26. On receiving the first packet containing a program clock reference (PCR) header, the DSP writes the most-significant bit (MSB) of the PCR and the 9-bit PCR extension into TSICLKINITM.
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Video Capture Registers 3.13.14 TSI System Time Clock LSB Register (TSISTCLKL) The transport stream interface system time clock LSB register (TSISTCLKL) contains the 32 least-significant bits (LSBs) of the program clock reference (PCR). The system time clock value is obtained by reading TSISTCLKL and TSISTCLKM. TSISTCLKL is shown in Figure 3–42 and described in Table 3–27. TSISTCLKL represents the current value of the 32 LSBs of the base PCR that normally counts at a 90-kHz rate.
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Video Capture Registers 3.13.15 TSI System Time Clock MSB Register (TSISTCLKM) The transport stream interface system time clock MSB register (TSISTCLKM) contains the most-significant bit (MSB) of the program clock reference (PCR) and the 9 bits of the PCR extension. The system time clock value is obtained by reading TSISTCLKM and TSISTCLKL. TSISTCLKM is shown in Figure 3–43 and described in Table 3–28. The PCRE value changes at a 27-MHz rate and is probably not reliably read by the DSP.
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Video Capture Registers 3.13.16 TSI System Time Clock Compare LSB Register (TSISTCMPL) The transport stream interface system time clock compare LSB register (TSISTCMPL) is used to generate an interrupt at some absolute time based on the STC. TSISTCMPL holds the 32 least-significant bits (LSBs) of the absolute time compare (ATC). Whenever the value in TSISTCMPL and TSISTCMPM match the unmasked bits of the time kept by the STC hardware counter and the STEN bit in TSICTL is set, the STC bit in VPIS is set.
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Video Capture Registers 3.13.17 TSI System Time Clock Compare MSB Register (TSISTCMPM) The transport stream interface system time clock compare MSB register (TSISTCMPM) is used to generate an interrupt at some absolute time based on the STC. TSISTCMPM holds the most-significant bit (MSB) of the absolute time compare (ATC). Whenever the value in TSISTCMPM and TSISTCMPL match the unmasked bits of the time kept by the STC hardware counter and the STEN bit in TSICTL is set, the STC bit in VPIS is set.
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Video Capture Registers 3.13.18 TSI System Time Clock Compare Mask LSB Register (TSISTMSKL) The transport stream interface system time clock compare mask LSB register (TSISTMSKL) holds the 32 least-significant bits (LSBs) of the absolute time compare mask (ATCM). This value is used with TSISTMSKM to mask out bits during the comparison of the ATC to the system time clock for absolute time. The bits that are set to one mask the corresponding ATC bits during the compare.
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Video Capture Registers 3.13.19 TSI System Time Clock Compare Mask MSB Register (TSISTMSKM) The transport stream interface system time clock compare mask MSB register (TSISTMSKM) holds the most-significant bit (MSB) of the absolute time compare mask (ATCM). This value is used with TSISTMSKL to mask out bits during the comparison of the ATC to the system time clock for absolute time. The bits that are set to one mask the corresponding ATC bits during the compare.
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Video Capture Registers 3.13.20 TSI System Time Clock Ticks Interrupt Register (TSITICKS) The transport stream interface system time clock ticks interrupt register (TSITICKS) is used to generate an interrupt after a certain number of ticks of the 27-MHz system time clock. When the TICKCT value is set to X and the TCKEN bit in TSICTL is set, the TICK bit in VPIS is set every X + 1 STCLK cycles.
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Video Capture FIFO Registers 3.14 Video Capture FIFO Registers The capture FIFO mapping registers are listed in Table 3–34. These registers provide read access to the capture FIFOs. These pseudo-registers should be mapped into DSP memory space rather than configuration register space in order to provide high-speed access. See the device-specific datasheet for the memory address of these registers. The function of the video capture FIFO mapping registers is listed in Table 3–35. Table 3–34.
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Chapter 4 Video Display Port The video port peripheral can operate as a video capture port, video display port, or transport stream interface (TSI) capture port. This chapter discusses the video display port. Topic Page 4.1 Video Display Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 BT.656 Video Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.3 Y/C Video Display Mode . . . . . . . . . . . . . . . . . . . . . . .
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Video Display Mode Selection 4.1 Video Display Mode Selection The video display module operates in one of three modes as listed in Table 4–1. The DMODE bits are in the video display control register (VDCTL). The Y/C and 16/20-bit raw display modes may only be selected if the DCDIS bit in the video port control register (VPCTL) is cleared to 0. Table 4–1. Video Display Mode Selection DMODE Bits 4.1.1 Mode Description 000 8-Bit ITU-R BT.
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Video Display Mode Selection Figure 4–1. NTSC Compatible Interlaced Display Field 1 Field 2 Line 20 Line 282 Line 21 Line 283 Line 22 Line 284 Line 261 Line 523 Line 262 Line 524 Line 263 Line 525 Figure 4–2.
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Video Display Mode Selection Figure 4–3. Interlaced Blanking Intervals and Video Areas Field 1 Vertical Blanking Field 1 Field 1 Image Height Field 1 Active Video Field 1 Image Horiz. Offset Frame Horizontal Blanking Field 1 Image Vertical Offset Field 1 Image Width Field 2 Vertical Blanking 4-4 Video Display Port Field 2 Field 2 Image Height Field 2 Active Video Field 2 Image Horiz.
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Video Display Mode Selection Figure 4–4. Progressive Blanking Intervals and Video Area Field 1 Vertical Blanking Field 1 Frame Field 1 Image Height Field 1 Image Vertical Offset Field 1 Active Video Field 1 Image Width 4.1.
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Video Display Mode Selection The image line counter (ILCOUNT) and the image pixel counter (IPCOUNT) track the visible image within the field. ILCOUNT begins counting at the first display image line in each field. IPCOUNT begins counting at the first displayed image pixel on each line. They stop counting when they reach the image height and image width as specified in the video display field n image size register (VDIMGSZn).
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Video Display Mode Selection Note that the signals can transition at any place along the video line (specified by the XSTART and XSTOP bits of the appropriate registers). In this case, VBLNK starts at horizontal count VBLNKXSTART2 = 429 on scan line VBLNKYSTART2 = 263 (565/60 operation). Figure 4–6.
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Video Display Mode Selection 4.1.4 External Sync Operation The video display module may be synchronized with an external video source using external sync signals. VCTL1 may be configured as an external horizontal sync input. When the external HSYNC is asserted, FPCOUNT is loaded with the HRLD value and VCCOUNT is loaded with the CRLD value. VCTL2 may be configured as an external vertical sync input. When the external VSYNC is asserted during field 1, FLCOUNT is loaded with the VRLD value.
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BT.656 Video Display Mode 4.2 BT.656 Video Display Mode The BT.656 display mode outputs 8-bit or 10-bit 4:2:2 co-sited luma and chroma data multiplexed into a single data stream. Pixels are output in pairs with each pair consisting of two luma samples and two chroma samples. The chroma samples are associated with the first luma pixel of the pair. Output pixels are valid on the positive edge of VCLKOUT in the sequence CbYCrY as shown in Figure 4–8. Figure 4–8. BT.656 Output Sequence VCLKOUT VDOUT[9–0] 4.
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BT.656 Video Display Mode Figure 4–10. 625/50 BT.656 Horizontal Blanking Timing One Line FPCOUNT 720 721 722 723 861 862 863 Next Line 0 1 2 718 719 720 721 722 723 VCLKOUT 280 4 EAV 80.0 10.0 FF.C 00.0 00.0 XY.0 Cb 0 Y0 Cr 0 Y1 Cb 1 Y2 VDOUT[9–0] Active Video FF.C 00.0 00.0 XY.0 80.0 10.0 80.0 10.0 Blanking 1440 Blanking Data SAV Cb 359 Y 718 Cr 359 Y 719 FF.C 00.0 00.0 XY.0 80.0 10.0 80.0 10.0 4 EAV SAV and EAV codes are identified by a 3-byte preamble of FFh, 00h, and 00h.
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BT.656 Video Display Mode Figure 4–11.
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BT.656 Video Display Mode 4.2.2 Blanking Codes The time between the EAV and SAV code on each line represents the horizontal blanking interval. During this time, the video port outputs digital video blanking values. These values are 10.0h for luma (Y) samples and 80.0h for chroma (Cb/Cr) samples. These values are also output during the active line period of vertical blanking (between SAV and EAV when V = 1).
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BT.656 Video Display Mode 4.2.4 BT.656 FIFO Unpacking Display data is always packed into the FIFOs in 64-bit words and must be unpacked before being sent to the video display data pipeline. The unpacking and byte ordering is dependant upon the display data size and the device endian mode. For little-endian operation (default), data is unpacked from right to left; for big-endian operation, data is unpacked from left to right. The 8-bit BT.656 mode uses three FIFOs for color separation.
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BT.656 Video Display Mode For 10-bit BT.656 operation, two samples are unpacked from each word as shown in Figure 4–13. Figure 4–13. 10-Bit BT.
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BT.656 Video Display Mode In 10-bit BT.656 dense-pack mode, three samples are unpacked from each word in the FIFO as seen in Figure 4–14. Figure 4–14. BT.
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Y/C Video Display Mode 4.3 Y/C Video Display Mode The Y/C display mode is similar to the BT.656 display mode but outputs 8 or 10-bit data on separate luma and chroma data streams. One data stream contains Y samples and the other stream contains multiplexed Cb and Cr samples co-sited with every other luminance sample. The Y samples are read from the Y FIFO and the Cb and Cr samples are read from the Cb and Cr FIFOs and combined on the chroma output.
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Y/C Video Display Mode 4.3.2 Y/C Blanking Codes The time between the EAV and SAV code on each line represents the horizontal blanking interval. During this time, the video port outputs the digital video blanking values. These values are 10.0h for luma (Y) samples and 80.0h for chroma (Cb/Cr) samples. These values are also output during the active line period of vertical blanking (between SAV and EAV when V = 1), unless replaced by VBI data.
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Y/C Video Display Mode The 8-bit Y/C mode uses three FIFOs for color separation. Four samples are unpacked from each word as shown in Figure 4–16. Figure 4–16.
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Y/C Video Display Mode For 10-bit operation, two samples are unpacked from each FIFO word. This is shown in Figure 4–17. Figure 4–17.
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Y/C Video Display Mode In 10-bit Y/C dense-pack mode, three samples are unpacked from each word in the FIFO as seen in Figure 4–18. Figure 4–18.
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Video Output Filtering 4.4 Video Output Filtering The video output filter performs simple hardware scaling and resampling on outgoing 8-bit BT.656 or 8-bit Y/C data. Filtering hardware is disabled during 10-bit or raw data display modes. 4.4.1 Output Filter Modes The output filter has four modes of operation: no-filtering, 2× scaling, chrominance resampling, and 2× scaling with chrominance resampling. Filter operation is determined by the DMODE, SCALE, and RESMPL bits of the VDCTL.
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Video Output Filtering 4.4.2 Chrominance Resampling Operation Chrominance resampling computes chrominance values at sample points corresponding to output luminance samples based on the input interspersed chrominance samples. This filter performs the conversion between interspersed YCbCr 4:2:2 format and co-sited YCbCr 4:2:2 format. The vertical portion of the conversion from YCbCr 4:2:0 to interspersed YCbCr 4:2:2 must be performed in software.
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Video Output Filtering Figure 4–20. 2x Co-Sited Scaling a YCbCr 4:2:2 co–sited source pixels a b a’ c b b’ d c c’ e d d’ e f e’ g f g f’ 2× upscaled output Y’b = Yb Y’d’ = (–1Yc + 17Yd + 17Ye – 1Yf ) / 32 Cb’c = Cbc Cr’c = Crc – Chroma (Cb/Cr) – Luma (Y) Cb’d = (–1Cba + 17Cbc + 17Cbe – 1Cbg ) / 32 Cr’d = (–1Cra + 17Crc + 17Cre – 1Crg ) / 32 samples sample Figure 4–21.
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Video Output Filtering Examples of luma edge and chroma edge replication for 2× interspersed to co-sited output are shown in Figure 4–23 and Figure 4–24, respectively. Figure 4–23.
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Ancillary Data Display Ancillary Data Display / Raw Data Display Mode 4.5 Ancillary Data Display The following sections discuss ancillary data display. No special previsions are made for the display of horizontal ancillary (HANC) or vertical ancillary (VANC), also called vertical blanking interval (VBI), data. 4.5.1 Horizontal Ancillary (HANC) Data Display HANC data can be displayed using the normal video display mechanism by programming IMGHSIZEn to occur prior to the SAV code.
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Raw Data Display Mode 4.6.1 Raw Mode RGB Output Support The raw data display mode has a special pixel count feature that allows the FPCOUNT increment rate to be set. FPCOUNT increments only when INCPIX samples have been sent out. This option allows proper tracking of the display pixels when sending out sequential RGB samples. (INCPIX would be set to three in this case, to indicate that a single pixel is represented by three output samples.
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Raw Data Display Mode For 10-bit operation, two samples are unpacked from each FIFO word. This is shown in Figure 4–26. Figure 4–26.
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Raw Data Display Mode Figure 4–28 shows the 16-bit raw mode. Two samples are unpacked from each word of the FIFO. Figure 4–28.
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Raw Data Display Mode In 8-bit raw ¾ mode, three samples are unpacked from the FIFO and the remaining byte is ignored. This is shown in Figure 4–30. Figure 4–30.
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Video Display Field and Frame Operation 4.7 Video Display Field and Frame Operation As a video source, the video port always outputs entire frames of data and transmits continuous video control signals. Depending on the DMA structure, however, the video port may need to interrupt the DSP on a field or frame basis to allow it to update video port registers or DMA parameters. To achieve this, the video port provides programmable control over the display process. 4.7.
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Video Display Field and Frame Operation Table 4–4. Display Operation VDCTL Bit CON FRAME DF2 DF1 Operation 0 0 0 0 Reserved 0 0 0 1 Noncontinuous field 1 display. Display only field 1. F1D is set after field 1 display and causes DCMPx to be set. The F1D bit must be cleared by the DSP or a DCNA interrupt occurs. (The DSP has the entire field 2 time to clear F1D before next field 1 begins.) Can also be used for single progressive frame display (internal timing codes only).
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Video Display Field and Frame Operation Table 4–4. Display Operation (Continued) VDCTL Bit CON FRAME DF2 DF1 1 0 1 0 Continuous field 2 display. Display only field 2. F2D is set after field 2 display and causes DCMPx to be set (DCMPx interrupt can be disabled). No DCNA interrupt occurs, regardless of the state of F2D. 1 0 1 1 Reserved 1 1 0 0 Continuous frame display. Display both fields. FRMD is set after field 2 display and causes DCMPx to be set (DCMPx interrupt can be disabled.
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Display Line Boundary Conditions 4.8 Display Line Boundary Conditions In order to simplify DMA transfers, FIFO doublewords do not contain data from more than one display line. This means that a FIFO read must be performed whenever 8-bytes have been output or when the line complete condition (IPCOUNT = IMGHSIZE) occurs. Thus, every display line begins on a doubleword boundary and non-doubleword length lines are truncated at the end. An example is shown in Figure 4–32.
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Display Line Boundary Conditions Figure 4–32.
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Display Timing Examples 4.9 Display Timing Examples The following are examples of display output for several modes of operation. 4.9.1 Interlaced BT.656 Timing Example This section shows an example of BT.656 display output for a 704 × 408 interlaced output image as might be generated by MPEG decoding. The horizontal output timing is shown in Figure 4–33. This diagram assumes that there is a two VCLK pipeline delay between the internal counter changing and the output on external pins.
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VCLKIN Video Display Port 268 4 1440 4 One Line FPCOUNT 720 721 722 723 735 736 799 800 IPCOUNT 703 703 703 703 703 703 703 703 Next Line 855 856 857 0 1 7 703 703 703 703 703 703 8 0 9 10 710 711 712 718 719 720 721 1 2 702 703 703 703 703 703 703 ‡ VCTL1 (HBLNK)† § VCTL1 (HSYNC)† § VCLKOUT Display Image EAV Blanking Data FLCOUNT SAV n n–1 FRMWIDTH = 858 IMGHOFF1 = 8 HSYNCSTART = 736 HBLNKSTART = 720 IMGHSIZE1 = 704 HSYNCSTOP = 800 HBLNKSTOP = 856 IMGHOFF2 = 8 IMG
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Display Timing Examples The interlaced BT.656 vertical output timing is shown in Figure 4–34. The BT.656 active field 1 is 244-lines high and active field 2 is 243-lines high. This example shows the 480-line image window centered in the screen. This results in an IMGVOFFn of 3 lines and also results in a nondata line at the end of field 1 due to its extra active line. The VBLNK and VSYNC signals are shown as they would be output for activelow operation.
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Display Timing Examples 525 1 2 3 4 5 6 Field 1 Blanking ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÉÉÉÉÉÉÉ 19 20 21 22 23 Field 1 Active EAV VF VSYNC† § ILCOUNT VBLNK† § FLCOUNT FLD Figure 4–34. BT.
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Display Timing Examples 4.9.2 Interlaced Raw Display Example This section shows an example of raw display output for the same 704 × 408 interlaced image. The horizontal output timing is shown in Figure 4–35. This diagram assumes that there is a two VCLK pipeline delay between the internal counter changing and the output on external pins. The actual delay can be longer or shorter as long as it is consistent within any display mode. The active line is 720-pixels wide.
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VCLKIN Video Display Port 414 2112 One Line Next Line FPCOUNT 720 721 735 736 799 800 857 0 1 7 8 9 711 712 719 720 721 IPCOUNT 703 703 703 703 703 703 703 703 703 703 0 1 703 703 703 703 703 VCTL1 (HBLNK)† § VCTL1 (HSYNC)† § VCLKOUT FRMWIDTH = 858 IMGHOFF1 = 8 HSYNCSTART = 736 HBLNKSTART = 720 IMGHSIZE1 = 704 HSYNCSTOP = 800 HBLNKSTOP = 0 IMGHOFF2 = 8 IMGHSIZE2 = 704 INCPIX = 3 † Assumes VCT1P bit in VPCTL is set to 1 (active-low output).
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Display Timing Examples The vertical output timing for raw mode is shown in Figure 4–36. This example outputs the same 480-line window. Note that the raw display mode is typically noninterlaced for output to a monitor. This example shows the more complex interlaced case. The active field 1 is 242.5-lines high and active field 2 is 242.5-lines high. This example shows the 480-line image window centered in the screen.
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Display Timing Examples Figure 4–36.
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Display Timing Examples 4.9.3 Y/C Progressive Display Example This section shows an example of progressive display operation. The output format follows SMPTE 296M-2001 specifications for a 1280 × 720/60 system. The example is for a 1264 × 716 progressive output image. The horizontal output timing is shown in Figure 4–37. This diagram assumes that there is a two VCLK pipeline delay between the internal counter changing and the output on external pins.
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VCLKIN 4 362 1280 7 8 9 10 1263 0 1 2 1276 1277 1278 1279 1280 1281 1282 1283 1644 1645 1646 1647 1648 1649 0 1 2 3 1263 1263 1263 1263 1263 1263 1263 1263 1263 1263 1263 1263 1263 1263 1263 1263 1263 1263 1429 1430 1263 1263 1270 1271 1272 1273 1349 1350 IPCOUNT VCTL1 (HBLNK)† § 1262 1263 1263 1263 FPCOUNT 1263 1263 Next Line 1280 1281 1282 1283 1284 1285 1286 1287 One Line 1263 1263 1263 1263 1263 1263 1263 1263 Video Display Port 4 ‡ VCTL1 (HSYNC)† § VCLKOUT Display Image 80.0 80.
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Display Timing Examples The vertical output timing is shown in Figure 4–38. SMPTE 296M has a single active field 1 that is 720-lines high. This example shows the 716-line image window with an IMGVOFFn of 3 lines and also results in a nondata line at the end of the field. The VBLNK and VSYNC signals are shown as they would be output for activelow operation. Note that only one of the two signals is actually available externally.
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Display Timing Examples 750 1 2 3 4 5 6 Field 1 Blanking ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ ÇÇÇÇÇÇÇ 25 26 27 28 29 Field 1 Active EAV VF VSYNC† § ILCOUNT VBLNK† § FLCOUNT FLD Figure 4–38.
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Displaying Video in BT.656 or Y/C Mode 4.10 Displaying Video in BT.656 or Y/C Mode In order to display video in the BT.656 or Y/C format, the following steps are needed: 1) Set the frame size in VDFRMSZ. Set the number of lines per frame (FRMHIGHT) and the number of pixels per line (FRMWIDTH). 2) Set the horizontal blanking in VDHBLNK. Specify the frame pixel counter value where horizontal blanking starts (HBLNKSTART) and pixel location where horizontal blanking stops (HBLNKSTOP).
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Displaying Video in BT.656 or Y/C Mode 12) Configure a DMA to move data from the Y buffer in the DSP memory to YDSTA (memory-mapped Y display FIFO). The transfers should be triggered by the YEVT. 13) Configure a DMA to move data from the Cb buffer in the DSP memory to CBDST (memory-mapped Cb display FIFO). The transfers should be triggered by the CbEVT. The size of the transfers should be set to ½ the Y transfer size.
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Displaying Video in Raw Data Mode 22) If continuous display is enabled, the video port begins displaying again at the start of the next field or frame. If noncontinuous field 1 and field 2 or frame display is enabled, the next field or frame is displayed, during which the DSP must clear the appropriate completion status bit or a DCNA interrupt occurs and incorrect data may be output. 4.
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Displaying Video in Raw Data Mode 11) Set the horizontal synchronization in VDHSYNC. Specify the frame pixel counter value for a pixel where HSYNC gets asserted (HSYNCYSTART) and width of the HSYNC pulse (HSYNCSTOP) in frame pixel clocks. 12) Set the video display field 1 timing. Specify the first line and pixel of field 1 in VDFLDT1. 13) Set the video display field 2 timing. Specify the first line and pixel of field 2 in VDFLDT2.
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Displaying Video in Raw Data Mode 22) If continuous display is enabled, the video port begins displaying again at the start of the next field or frame. If noncontinuous field 1 and field 2 or frame display is enabled, the next field or frame is displayed, during which the DSP must clear the appropriate completion status bit or a DCNA interrupt occurs and incorrect data may be output. 4.11.
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Video Display Registers 4.12 Video Display Registers The registers for controlling the video display mode of operation are listed in Table 4–5. See the device-specific datasheet for the memory address of these registers. Table 4–5. Video Display Control Registers Acronym Register Name Section VDSTAT Video Display Status Register 4.12.1 VDCTL Video Display Control Register 4.12.2 VDFRMSZ Video Display Frame Size Register 4.12.3 VDHBLNK Video Display Horizontal Blanking Register 4.12.
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Video Display Registers Table 4–5. Video Display Control Registers (Continued) Acronym Register Name Section VDDEFVAL Video Display Default Display Value Register 4.12.24 VDVINT Video Display Vertical Interrupt Register 4.12.25 VDFBIT Video Display Field Bit Register 4.12.26 VDVBIT1 Video Display Field 1 Vertical Blanking Bit Register 4.12.27 VDVBIT2 Video Display Field 2 Vertical Blanking Bit Register 4.12.28 4.12.
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Video Display Registers Table 4–6. Video Display Status Register (VDSTAT) Field Descriptions Bit field† symval† 31 Reserved – 30 FRMD 29 28 0 Complete frame has not been displayed. DISPLAYED 1 Complete frame has been displayed. F2D Field 2 displayed bit. Write 1 to clear the bit, a write of 0 has no effect. NONE 0 Field 2 has not been displayed. DISPLAYED 1 Field 2 has been displayed. F1D Field 1 displayed bit. Write 1 to clear the bit, a write of 0 has no effect.
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Video Display Registers 4.12.2 Video Display Control Register (VDCTL) The video display is controlled by the video display control register (VDCTL). The VDCTL is shown in Figure 4–40 and described in Table 4–7. Figure 4–40.
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Video Display Registers Table 4–7. Video Display Control Register (VDCTL) Field Descriptions (Continued) Description Bit field† 30 BLKDIS symval† Value BT.656 and Y/C Mode Raw Data Mode Block display events bit. BLKDIS functions as a display FIFO reset without affecting the current programmable register values. The video display module continues to function normally, the counters count, control outputs are generated, EAV/SAV codes are generated for BT.
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Video Display Registers Table 4–7. Video Display Control Register (VDCTL) Field Descriptions (Continued) Description Bit field† 21 HXS 20 19–18 17–16 15 14 symval† Value BT.656 and Y/C Mode Raw Data Mode Horizontal external synchronization enable bit. OUTPUT 0 VCTL1 is an output. HSINPUT 1 VCTL1 is an external horizontal sync input. VCTL3S VCTL3 output select bit. CBLNK 0 Output CBLNK FLD 1 Output FLD VCTL2S VCTL2 output select bit.
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Video Display Registers Table 4–7. Video Display Control Register (VDCTL) Field Descriptions (Continued) Description Bit field† 13 RGBX 12 11 10 Value DISABLE 0 Not used. ENABLE 1 Not used. SCALE Perform ¾ FIFO unpacking. DISABLE 0 Not used. Second, synchronized raw data channel is disabled. ENABLE 1 Not used. Second, synchronized raw data channel is enabled. Default value enable bit. BLANKING 0 Blanking value is output during non-sourced active pixels. Not used.
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Video Display Registers Table 4–7. Video Display Control Register (VDCTL) Field Descriptions (Continued) Description Bit 6 5 4 field† symval† Value FRAME‡ NONE 0 Do not display frame. FRMDIS 1 Display frame. Display field 2 bit. NONE 0 Do not display field 2. FLDDIS 1 Display field 2. DF1‡ Reserved 2–0 DMODE Raw Data Mode Display frame bit. DF2‡ 3 BT.656 and Y/C Mode Display field 1 bit. NONE 0 Do not display field 1. FLDDIS 1 Display field 1. – 0 Reserved.
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Video Display Registers 4.12.3 Video Display Frame Size Register (VDFRMSZ) The video display frame size register (VDFRMSZ) sets the display channel frame size by setting the ending values for the frame line counter (FLCOUNT) and the frame pixel counter (FPCOUNT). The VDFRMSZ is shown in Figure 4–41 and described in Table 4–8. The FPCOUNT starts at 0 and counts to FRMWIDTH – 1 before restarting. The FLCOUNT starts at 1 and counts to FRMHEIGHT before restarting. Figure 4–41.
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Video Display Registers 4.12.4 Video Display Horizontal Blanking Register (VDHBLNK) The video display horizontal blanking register (VDHBLNK) controls the display horizontal blanking. The VDHBLNK is shown in Figure 4–42 and described in Table 4–9. Every time the frame pixel counter (FPCOUNT) is equal to HBLNKSTART, HBLNK is asserted. HBLNKSTART also determines where the EAV code is inserted in the BT.656 and Y/C output.
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Video Display Registers Table 4–9. Video Display Horizontal Blanking Register (VDHBLNK) Field Descriptions Description field† symval† 31–28 Reserved – 27–16 HBLNKSTOP OF(value) Bit 15 14–12 11–0 Value 0 0–FFFh HBDLA BT.656 and Y/C Mode Raw Data Mode Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Location of SAV code and HBLNK inactive edge within the line. HBLNK inactive edge may be optionally delayed by 4 VCLKs.
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Video Display Registers Figure 4–43. Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1) 31 28 27 16 Reserved VBLNKYSTART1 R-0 R/W-0 15 12 11 0 Reserved VBLNKXSTART1 R-0 R/W-0 Legend: R = Read only; R/W = Read/Write; -n = value after reset Table 4–10.
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Video Display Registers 4.12.6 Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) The video display field 1 vertical blanking end register (VDVBLKE1) controls the end of vertical blanking in field 1. The VDVBLKE1 is shown in Figure 4–44 and described in Table 4–11. In raw data mode, VBLNK is deasserted whenever the frame line counter (FLCOUNT) is equal to VBLNKYSTOP1 and the frame pixel counter (FPCOUNT) is equal to VBLNKXSTOP1 (this is shown in Figure 4–6, page 4-7). In BT.
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Video Display Registers Table 4–11. Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) Field Descriptions Description field† symval† 31–28 Reserved – 27–16 VBLNKYSTOP1 OF(value) 15–12 Reserved – VBLNKXSTOP1 OF(value) Bit 11–0 Value 0 0–FFFh 0 0–FFFh BT.656 and Y/C Mode Raw Data Mode Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Specifies the line (in FLCOUNT) where VBLNK inactive edge occurs for field 1.
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Video Display Registers Figure 4–45. Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) 31 28 27 16 Reserved VBLNKYSTART2 R-0 R/W-0 15 12 11 0 Reserved VBLNKXSTART2 R-0 R/W-0 Legend: R = Read only; R/W = Read/Write; -n = value after reset Table 4–12.
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Video Display Registers 4.12.8 Video Display Field 2 Vertical Blanking End Register (VDVBLKE2) The video display field 2 vertical blanking end register (VDVBLKE2) controls the end of vertical blanking in field 2. The VDVBLKE2 is shown in Figure 4–46 and described in Table 4–13. In raw data mode, VBLNK is deasserted whenever the frame line counter (FLCOUNT) is equal to VBLNKYSTOP2 and the frame pixel counter (FPCOUNT) is equal to VBLNKXSTOP2 (this is shown in Figure 4–6, page 4-7). In BT.
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Video Display Registers Table 4–13. Video Display Field 2 Vertical Blanking End Register (VDVBLKE2) Field Descriptions Description field† symval† 31–28 Reserved – 27–16 VBLNKYSTOP2 OF(value) 15–12 Reserved – VBLNKXSTOP2 OF(value) Bit 11–0 Value 0 0–FFFh 0 0–FFFh BT.656 and Y/C Mode Raw Data Mode Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Specifies the line (in FLCOUNT) where VBLNK inactive edge occurs for field 2.
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Video Display Registers Figure 4–47. Video Display Field 1 Image Offset Register (VDIMGOFF1) 31 30 28 27 16 NV Reserved IMGVOFF1 R/W-0 R-0 R/W-0 15 14 12 11 0 NH Reserved IMGHOFF1 R/W-0 R-0 R/W-0 Legend: R = Read only; R/W = Read/Write; -n = value after reset Table 4–14. Video Display Field 1 Image Offset Register (VDIMGOFF1) Field Descriptions Description Bit field† 31 NV symval† 0 NEGOFF 1 Display image window begins before the first active line of field 1.
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Video Display Registers 4.12.10 Video Display Field 1 Image Size Register (VDIMGSZ1) The video display field 1 image size register (VDIMGSZ1) defines the field 1 image area and specifies the size of the displayed image within the active display. The VDIMGSZ1 is shown in Figure 4–48 and described in Table 4–15. The image pixel counter (IPCOUNT) counts displayed image pixel output on each of the displayed image. Displayed image pixel output stops when IPCOUNT = IMGHSIZE1.
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Video Display Registers 4.12.11 Video Display Field 2 Image Offset Register (VDIMGOFF2) The video display field 2 image offset register (VDIMGOFF2) defines the field 2 image offset and specifies the starting location of the displayed image relative to the start of the active display. The VDIMGOFF2 is shown in Figure 4–49 and described in Table 4–16. The image line counter (ILCOUNT) is reset to 1 on the first image line (when FLCOUNT = VBLNKYSTOP2 + IMGVOFF2).
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Video Display Registers Table 4–16. Video Display Field 2 Image Offset Register (VDIMGOFF2) Field Descriptions Description Bit field† 31 NV symval† 0 NEGOFF 1 Display image window begins before the first active line of field 2. (Used for VBI data output.) 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. 0–FFFh Specifies the display image vertical offset in lines from the first active line of field 2.
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Video Display Registers 4.12.12 Video Display Field 2 Image Size Register (VDIMGSZ2) The video display field 2 image size register (VDIMGSZ2) defines the field 2 image area and specifies the size of the displayed image within the active display. The VDIMGSZ2 is shown in Figure 4–50 and described in Table 4–17. The image pixel counter (IPCOUNT) counts displayed image pixel output on each of the displayed image. Displayed image pixel output stops when IPCOUNT = IMGHSIZE2.
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Video Display Registers 4.12.13 Video Display Field 1 Timing Register (VDFLDT1) The video display field 1 timing register (VDFLDT1) sets the timing of the field identification signal. The VDFLDT1 is shown in Figure 4–51 and described in Table 4–18. In raw data mode, the FLD signal is deasserted to indicate field 1 display whenever the frame line counter (FLCOUNT) is equal to FLD1YSTART and the frame pixel counter (FPCOUNT) is equal to FLD1XSTART (this is shown in Figure 4–6, page 4-7). In BT.
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Video Display Registers 4.12.14 Video Display Field 2 Timing Register (VDFLDT2) The video display field 2 timing register (VDFLDT2) sets the timing of the field identification signal. The VDFLDT2 is shown in Figure 4–52 and described in Table 4–19. In raw data mode, the FLD signal is asserted whenever the frame line counter (FLCOUNT) is equal to FLD2YSTART and the frame pixel counter (FPCOUNT) is equal to FLD2XSTART (this is shown in Figure 4–6, page 4-7). In BT.
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Video Display Registers 4.12.15 Video Display Threshold Register (VDTHRLD) The video display threshold register (VDTHRLD) sets the display FIFO threshold to determine when to load more display data. The VDTHRLD is shown in Figure 4–53 and described in Table 4–20. The VDTHRLDn bits determines how much space must be available in the display FIFOs before the appropriate DMA event may be generated.
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Video Display Registers Table 4–20. Video Display Threshold Register (VDTHRLD) Field Descriptions Description field† symval† 31–26 Reserved – 25–16 VDTHRLD2 OF(value) 0–3FFh 15–12 INCPIX OF(value) 0–Fh 11–10 Reserved – VDTHRLD1 OF(value) Bit 9–0 Value 0 0 0–3FFh BT.656 and Y/C Mode Raw Data Mode Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Field 2 threshold.
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Video Display Registers 4.12.16 Video Display Horizontal Synchronization Register (VDHSYNC) The video display horizontal synchronization register (VDHSYNC) controls the timing of the horizontal synchronization signal. The VDHSYNC is shown in Figure 4–54 and described in Table 4–21. Generation of the horizontal synchronization is shown in Figure 4–5, page 4-6. The HSYNC signal is asserted to indicate the start of the horizontal sync pulse whenever the frame pixel counter (FPCOUNT) is equal to HSYNCSTART.
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Video Display Registers 4.12.17 Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1) The video display field 1 vertical synchronization start register (VDVSYNS1) controls the start of vertical synchronization in field 1. The VDVSYNS1 is shown in Figure 4–55 and described in Table 4–22. Generation of the vertical synchronization is shown in Figure 4–6, page 4-7.
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Video Display Registers 4.12.18 Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1) The video display field 1 vertical synchronization end register (VDVSYNE1) controls the end of vertical synchronization in field 1. The VDVSYNE1 is shown in Figure 4–56 and described in Table 4–23. Generation of the vertical synchronization is shown in Figure 4–6, page 4-7.
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Video Display Registers 4.12.19 Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2) The video display field 2 vertical synchronization start register (VDVSYNS2) controls the start of vertical synchronization in field 2. The VDVSYNS2 is shown in Figure 4–57 and described in Table 4–24. Generation of the vertical synchronization is shown in Figure 4–6, page 4-7.
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Video Display Registers 4.12.20 Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2) The video display field 2 vertical synchronization end register (VDVSYNE2) controls the end of vertical synchronization in field 2. The VDVSYNE2 is shown in Figure 4–58 and described in Table 4–25. Generation of the vertical synchronization is shown in Figure 4–6, page 4-7.
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Video Display Registers 4.12.21 Video Display Counter Reload Register (VDRELOAD) When external horizontal or vertical synchronization are used, the video display counter reload register (VDRELOAD) determines what values are loaded into the counters when an external sync is activated. The VDRELOAD is shown in Figure 4–59 and described in Table 4–26. Figure 4–59.
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Video Display Registers 4.12.22 Video Display Display Event Register (VDDISPEVT) The video display display event register (VDDISPEVT) is programmed with the number of DMA events to be generated for display field 1 and field 2. The VDDISPEVET is shown in Figure 4–60 and described in Table 4–27. Figure 4–60.
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Video Display Registers 4.12.23 Video Display Clipping Register (VDCLIP) The video display clipping register (VDCLIP) is shown in Figure 4–61 and described in Table 4–28. The video display module in the BT.656 and Y/C modes performs programmable clipping. The clipping is performed as the last step of the video pipeline. It is applied only on the image areas defined by VDIMGSZn and VDIMGOFFn inside the active video area (blanking values are not clipped).
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Video Display Registers 4.12.24 Video Display Default Display Value Register (VDDEFVAL) The video display default display value register (VDDEFVAL) defines the default value to be output during the portion of the active video window that is not part of the displayed image. The VDDEFVAL is shown in Figure 4–62 for the BT.656 and Y/C modes and in Figure 4–63 for the raw data mode, and described in Table 4–29. The default value is output during the nonimage display window portions of the active video.
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Video Display Registers Figure 4–63. Video Display Default Display Value Register (VDDEFVAL)—Raw Data Mode 31 20 19 16 Reserved DEFVAL R/W-0 R/W-0 15 0 DEFVAL R/W-0 Legend: R/W = Read/Write; -n = value after reset Table 4–29. Video Display Default Display Value Register (VDDEFVAL) Field Descriptions Description Bit 31–24 field† symval† Value BT.656 and Y/C Mode Raw Data Mode CRDEFVAL OF(value) 0–FFh Specifies the 8 MSBs of the default Cr display value. Not used. 0 Not used. Reserved.
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Video Display Registers 4.12.25 Video Display Vertical Interrupt Register (VDVINT) The video display vertical interrupt register (VDVINT) controls the generation of vertical interrupts in field 1 and field 2. The VDVINT is shown in Figure 4–64 and described in Table 4–30. An interrupt can be generated upon completion of the specified line in a field (when FLCOUNT = VINTn). This allows the software to synchronize itself to the frame or field.
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Video Display Registers 4.12.26 Video Display Field Bit Register (VDFBIT) The video display field bit register (VDFBIT) controls the F bit value in the EAV and SAV timing control codes. The VDFBIT is shown in Figure 4–65 and described in Table 4–31. The FBITCLR and FBITSET bits control the F bit value in the EAV and SAV timing control codes. The F bit is cleared to 0 (indicating field 1 display) in the EAV code at the beginning of the line whenever the frame line counter (FLCOUNT) is equal to FBITCLR.
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Video Display Registers 4.12.27 Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1) The video display field 1 vertical blanking bit register (VDVBIT1) controls the V bit value in the EAV and SAV timing control codes for field 1. The VDVBIT1 is shown in Figure 4–66 and described in Table 4–32. The VBITSET1 and VBITCLR1 bits control the V bit value in the EAV and SAV timing control codes.
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Video Display Registers Table 4–32. Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1) Field Descriptions Description field† symval† 31–28 Reserved – 27–16 VBITCLR1 OF(value) 15–12 Reserved – 11–0 VBITSET1 OF(value) Bit Value 0 0–FFFh 0 0–FFFh BT.656 and Y/C Mode Raw Data Mode Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Specifies the first line with an EAV of V = 0 indicating the start of field 1 active display.
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Video Display Registers 4.12.28 Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2) The video display field 2 vertical blanking bit register (VDVBIT2) controls the V bit in the EAV and SAV timing control words for field 2. The VDVBIT2 is shown in Figure 4–67 and described in Table 4–33. The VBITSET2 and VBITCLR2 bits control the V bit value in the EAV and SAV timing control codes.
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Video Display Registers Table 4–33. Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2) Field Descriptions Description field† symval† 31–28 Reserved – 27–16 VBITCLR2 OF(value) 15–12 Reserved – 11–0 VBITSET2 OF(value) Bit Value 0 0–FFFh 0 0–FFFh BT.656 and Y/C Mode Raw Data Mode Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Specifies the first line with an EAV of V = 0 indicating the start of field 2 active display.
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Video Display Registers Recommended Values 4.13 Video Display Registers Recommended Values Sample recommended values (decimal) for video display registers for BT.656 output are given in Table 4–34. Table 4–34.
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Video Display Registers Recommended Values Table 4–34. Video Display Register Recommended Values (Continued) Register Field VDVSYNS2 VDVSYNE2 VDFBIT VDVBIT1 VDVBIT2 525/60 Value 625/50 Value VSYNCXSTART2 360† 360† VSYNCYSTART2 266† 313† VSYNCXSTOP2 360† 720† VSYNCYSTOP2 269† 316† FBITCLR 4 1 FBITSET 266 313 VBITSET1 1 624 VBITCLR1 20 23 VBITSET2 264 311 VBITCLR2 283 336 † Programming only required if external control signal is used.
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Video Display FIFO Registers 4.14 Video Display FIFO Registers The display FIFO mapping registers are listed in Table 4–35. These registers provide DMA write access to the display FIFOs. These pseudo-registers should be mapped into DSP memory space rather than configuration register space in order to provide high-speed access. See the device-specific datasheet for the memory address of these registers. The function of the video display FIFO mapping registers is listed in Table 4–36. Table 4–35.
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Chapter 5 General Purpose I/O Operation Signals not used for video display or video capture can be used as generalpurpose input/output (GPIO) signals. Topic 5.1 Page GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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GPIO Registers 5.1 GPIO Registers The GPIO register set includes required registers such as peripheral identification and emulation control. The GPIO registers are listed in Table 5–1. See the device-specific datasheet for the memory address of these registers. Table 5–1. Video Port Registers Acronym Register Name VPPID Video Port Peripheral Identification Register 5.1.1 PCR Video Port Power Management Register 5.1.2 PFUNC Video Port Pin Function Register 5.1.
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GPIO Registers 5.1.1 Video Port Peripheral Identification Register (VPPID) The video port peripheral identification register (VPPID) is a read-only register used to store information about the peripheral. The VPPID is shown in Figure 5–1 and described in Table 5–2. Figure 5–1.
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GPIO Registers 5.1.2 Video Port Peripheral Control Register (PCR) The video port peripheral control register (PCR) determines operation during emulation. The video port peripheral control register is shown in Figure 5–2 and described in Table 5–3. Normal operation is to not halt the port during emulation suspend. This allows a displayed image to remain visible during suspend.
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GPIO Registers Table 5–3. Video Port Peripheral Control Register (PCR) Field Descriptions Bit 31–3 2 1 0 field† symval† Value Description Reserved Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. PEREN Peripheral enable bit. DISABLE 0 Video port is disabled. Port clock (VCLK1, VCLK2, STCLK) inputs are gated off to save power.
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GPIO Registers 5.1.3 Video Port Pin Function Register (PFUNC) The video port pin function register (PFUNC) selects the video port pins as GPIO. The PFUNC is shown in Figure 5–3 and described in Table 5–4. Each bit controls either one pin or a set of pins. When a bit is set to 1, it enables the pin(s) that map to it as GPIO. The GPIO feature should not be used for pins that are used as part of the capture or display operation.
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GPIO Registers Table 5–4. Video Port Pin Function Register (PFUNC) Field Descriptions (Continued) Bit field† 20 PFUNC20 19–11 Reserved 10 PFUNC10 9–1 Reserved 0 PFUNC0 symval† Value Description PFUNC20 bit determines if VCTL1 pin functions as GPIO. NORMAL 0 Pin functions normally. VCTL1 1 Pin functions as GPIO pin. – 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. PFUNC10 bit determines if VDATA[19–10] pins function as GPIO.
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GPIO Registers 5.1.4 Video Port Pin Direction Register (PDIR) The video port pin direction register (PDIR) is shown in Figure 5–4 and described in Table 5–5. The PDIR controls the direction of IO pins in the video port for those pins set by PFUNC. If a bit is set to 1, the relevant pin or pin group acts as an output. If a bit is cleared to 0, the pin or pin group functions as an input. The PDIR settings do not affect pins where the corresponding PFUNC bit is not set. Figure 5–4.
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GPIO Registers Table 5–5. Video Port Pin Direction Register (PDIR) Field Descriptions (Continued) Bit field† 21 PDIR21 20 19–17 16 15–13 12 Value Reserved VCTL2IN 0 Pin functions as input. VCTL2OUT 1 Pin functions as output. PDIR20 bit controls the direction of the VCTL1 pin. VCTL1IN 0 Pin functions as input. VCTL1OUT 1 Pin functions as output. – 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
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GPIO Registers Table 5–5. Video Port Pin Direction Register (PDIR) Field Descriptions (Continued) Bit field† 8 PDIR8 7–5 4 3–1 0 Reserved symval† Value PDIR8 bit controls the direction of the VDATA[9–8] pins. VDATA8TO9IN 0 Pins function as input. VDATA8TO9OUT 1 Pins function as output. – 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. PDIR4 Reserved Description PDIR4 bit controls the direction of the VDATA[7–4] pins.
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GPIO Registers 5.1.5 Video Port Pin Data Input Register (PDIN) The read-only video port pin data input register (PDIN) is shown in Figure 5–5 and described in Table 5–6. PDIN reflects the state of the video port pins. When read, PDIN returns the value from the pin’s input buffer (with appropriate synchronization) regardless of the state of the corresponding PFUNC or PDIR bit. Figure 5–5.
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GPIO Registers Table 5–6. Video Port Pin Data Input Register (PDIN) Field Descriptions Bit 31–23 22 21 20 19–0 field† symval† Reserved – Value 0 PDIN22 Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. PDIN22 bit returns the logic level of the VCTL3 pin. VCTL3LO 0 Pin is logic low. VCTL3HI 1 Pin is logic high. PDIN21 PDIN21 bit returns the logic level of the VCTL2 pin. VCTL2LO 0 Pin is logic low.
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GPIO Registers 5.1.6 Video Port Pin Data Output Register (PDOUT) The video port pin data output register (PDOUT) is shown in Figure 5–6 and described in Table 5–7. The bits of PDOUT determine the value driven on the corresponding GPIO pin, if the pin is configured as an output. Writes do not affect pins not configured as GPIO outputs. The bits in PDOUT are set or cleared by writing to this register directly.
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GPIO Registers Table 5–7. Video Port Pin Data Out Register (PDOUT) Field Descriptions field† symval† 31–23 Reserved – 22 PDOUT22 Bit Value 0 Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. PDOUT22 bit drives the VCTL3 pin only when the GPIO is configured as output. When reading data, returns the bit value in PDOUT22, does not return input from pin. When writing data, writes to PDOUT22 bit. 21 VCTL3LO 0 Pin drives low.
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GPIO Registers 5.1.7 Video Port Pin Data Set Register (PDSET) The video port pin data set register (PDSET) is shown in Figure 5–7 and described in Table 5–8. PDSET is an alias of the video port pin data output register (PDOUT) for writes only and provides an alternate means of driving GPIO outputs high. Writing a 1 to a bit of PDSET sets the corresponding bit in PDOUT. Writing a 0 has no effect. Register reads return all 0s. Figure 5–7.
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GPIO Registers Table 5–8. Video Port Pin Data Set Register (PDSET) Field Descriptions field† symval† 31–23 Reserved – 22 PDSET22 Bit 21 20 19–0 Value 0 Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Allows PDOUT22 bit to be set to a logic high without affecting other I/O pins controlled by the same port. NONE 0 No effect. VCTL3HI 1 Sets PDOUT22 (VCTL3) bit to 1.
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GPIO Registers 5.1.8 Video Port Pin Data Clear Register (PDCLR) The video port pin data clear register (PDCLR) is shown in Figure 5–8 and described in Table 5–9. PDCLR is an alias of the video port pin data output register (PDOUT) for writes only and provides an alternate means of driving GPIO outputs low. Writing a 1 to a bit of PDCLR clears the corresponding bit in PDOUT. Writing a 0 has no effect. Register reads return all 0s. Figure 5–8.
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GPIO Registers Table 5–9. Video Port Pin Data Clear Register (PDCLR) Field Descriptions field† symval† 31–23 Reserved – 22 PDCLR22 Bit 21 20 19–0 Value 0 Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Allows PDOUT22 bit to be cleared to a logic low without affecting other I/O pins controlled by the same port. NONE 0 No effect. VCTL3CLR 1 Clears PDOUT22 (VCTL3) bit to 0.
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GPIO Registers 5.1.9 Video Port Pin Interrupt Enable Register (PIEN) The video port pin interrupt enable register (PIEN) is shown in Figure 5–9 and described in Table 5–10. The GPIOs can be used to generate DSP interrupts or DMA events. The PIEN selects which pins may be used to generate an interrupt. Only pins whose corresponding bits in PIEN are set may cause their corresponding PISTAT bit to be set.
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GPIO Registers Table 5–10. Video Port Pin Interrupt Enable Register (PIEN) Field Descriptions Bit 31–23 22 21 20 19–0 field† symval† Reserved – Value 0 PIEN22 Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. PIEN22 bit enables the interrupt on the VCTL3 pin. VCTL3LO 0 Interrupt is disabled. VCTL3HI 1 Pin enables the interrupt. PIEN21 PIEN21 bit enables the interrupt on the VCTL2 pin. VCTL2LO 0 Interrupt is disabled.
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GPIO Registers 5.1.10 Video Port Pin Interrupt Polarity Register (PIPOL) The video port pin interrupt polarity register (PIPOL) is shown in Figure 5–10 and described in Table 5–11. The PIPOL determines the GPIO pin signal polarity that generates an interrupt. Figure 5–10.
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GPIO Registers Table 5–11. Video Port Pin Interrupt Polarity Register (PIPOL) Field Descriptions field† symval† 31–23 Reserved – 22 PIPOL22 Bit 21 20 19–0 Value 0 Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. PIPOL22 bit determines the VCTL3 pin signal polarity that generates an interrupt. VCTL3ACTHI 0 Interrupt is caused by a low-to-high transition on the VCTL3 pin.
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GPIO Registers 5.1.11 Video Port Pin Interrupt Status Register (PISTAT) The video port pin interrupt status register (PISTAT) is shown in Figure 5–11 and described in Table 5–12. PISTAT is a read-only register that indicates the GPIO pin that has a pending interrupt.
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GPIO Registers Table 5–12. Video Port Pin Interrupt Status Register (PISTAT) Field Descriptions field† symval† 31–23 Reserved – 22 PISTAT22 Bit 21 20 19–0 Value 0 Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. PISTAT22 bit indicates if there is a pending interrupt on the VCTL3 pin. NONE 0 No pending interrupt on the VCTL3 pin. VCTL3INT 1 Pending interrupt on the VCTL3 pin.
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GPIO Registers 5.1.12 Video Port Pin Interrupt Clear Register (PICLR) The video port pin interrupt clear register (PICLR) is shown in Figure 5–12 and described in Table 5–13. PICLR is an alias of the video port pin interrupt status register (PISTAT) for writes only. Writing a 1 to a bit of PICLR clears the corresponding bit in PISTAT. Writing a 0 has no effect. Register reads return all 0s. Figure 5–12.
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GPIO Registers Table 5–13. Video Port Pin Interrupt Clear Register (PICLR) Field Descriptions field† symval† 31–23 Reserved – 22 PICLR22 Bit 21 20 19–0 Value 0 Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Allows PISTAT22 bit to be cleared to a logic low. NONE 0 No effect. VCTL3CLR 1 Clears PISTAT22 (VCTL3) bit to 0. PICLR21 Allows PISTAT21 bit to be cleared to a logic low. NONE 0 No effect.
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Chapter 6 VCXO Interpolated Control Port This chapter provides an overview of the VCXO interpolated control (VIC) port. Topic SPRU629 Page 6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.3 Operational Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Overview 6.1 Overview The VCXO interpolated control (VIC) port provides single-bit interpolated VCXO control with resolution from 9 bits to up to 16 bits. The frequency of interpolation is dependent on the resolution needed. When the video port is used in transport stream interface (TSI) mode, the VIC port is used to control the system clock, VCXO, for MPEG transport stream (Figure 6–1).
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Interface Interface / Operational Details 6.2 Interface The pin list for VIC port is shown in Table 6–1 (pins are 3.3V I/Os). Table 6–1. VIC Port Interface Signals VIC Port Signal Direction Description VCTL Output VCXO control STCLK Input System time clock 6.3 Operational Details Synchronization is an important aspect of decoding and presenting data in real-time digital data delivery systems.
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Operational Details Any time a packet with a PCR is received, the timestamp for that packet is compared with the PCR value in software. A PLL is implemented in software to synchronize the STCLK with the system time clock. The DSP updates the VIC input register (VICIN) using the output from this algorithm, which in turn drives the VCTL output that controls the system time clock VCXO.
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Enabling VIC Port Enabling VIC Port / VIC Port Registers 6.4 Enabling VIC Port Perform the following steps to enable the VIC port. 1) Clear the GO bit in the VIC control register (VICCTL) to 0. 2) Set the PRECISION bits in VICCTL to the desired precision. 3) Set the VIC clock divider register (VICDIV) bits to appropriate value based on the precision and interpolation frequency. 4) Set the GO bit in VICCTL to 1.
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VIC Port Registers 6.5.1 VIC Control Register (VICCTL) The VIC control register (VICCTL) is shown in Figure 6–3 and described in Table 6–4. Figure 6–3. VIC Control Register (VICCTL) 31 16 Reserved R-0 15 4 3 1 0 Reserved PRECISION GO R-0 R/W-0 R/W-0 Legend: R = Read only; R/W = Read/Write; -n = value after reset Table 6–4. VIC Control Register (VICCTL) Field Descriptions field† symval† 31–4 Reserved – 3–1 PRECISION Bit Value 0 0–7h Description Reserved.
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VIC Port Registers Table 6–4. VIC Control Register (VICCTL) Field Descriptions (Continued) Bit 0 field† symval† Value GO Description The GO bit can be written to at any time. 0 0 The VICDIV and VICCTL registers can be written to without affecting the operation of the VIC port. All the logic in the VIC port is held in reset state and a 0 is output on the VCTL output line. A write to VICCTL bits as well as setting GO to 1 is allowed in a single write operation.
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VIC Port Registers 6.5.2 VIC Input Register (VICIN) The DSP writes the input bits for VCXO interpolated control in the VIC input register (VICIN). The DSP decides how often to update VICIN. The DSP can write to VICIN only when the GO bit in the VIC control register (VICCTL) is set to 1. The VIC module uses the MSBs of VICIN for precision values less than 16. The VICIN is shown in Figure 6–4 and described in Table 6–5. Figure 6–4.
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VIC Port Registers 6.5.3 VIC Clock Divider Register (VICDIV) The VIC clock divider register (VICDIV) defines the clock divider for the VIC interpolation frequency. The VIC interpolation frequency is obtained by dividing the module clock. The divider value written to VICDIV is: Divider + RoundƪDCLKńR ] where DCLK is the CPU clock divided by 2, and R is the desired interpolation frequency. The interpolation frequency depends on precision β. The default value of VICDIV is 0001h; 0000h is an illegal value.
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Appendix AppendixAA Video Port Configuration Examples This appendix describes how to configure the video port in different modes with the help of examples. All examples in this appendix use the video port Chip Support Library (CSL). Topic Page A.1 Example 1: Noncontinuous Frame Capture for 525/60 Format . . . . . A-2 A.2 Example 2: Noncontinuous Frame Display for 525/60 Format . . . .
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Example 1: Noncontinuous Frame Capture for 525/60 Format A.1 Example 1: Noncontinuous Frame Capture for 525/60 Format This is an example that explains how to configure the video port for 8-bit BT.656 noncontinuous frame capture on channel A for 525/60 format. See ITU–R BT.656-4 and video port specification (Figures 4–11, 4–33, 4–34, and Table 4–37) for more details on 525/60 format.
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Example 1: Noncontinuous Frame Capture for 525/60 Format /* –––––––––––––––––––––––––––––––––––––––––––– */ /* EDMA parameters for capture Y event that are */ /* specific to this example.
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Example 1: Noncontinuous Frame Capture for 525/60 Format /* Error volatile volatile volatile volatile flags Uint32 Uint32 Uint32 Uint32 */ capChaAOverrun = 0; capChaASyncError = 0; capChaAShortFieldDetect = 0; capChaALongFieldDetect = 0; /* ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– /* Function : bt656_8bit_ncfc /* Input(s) : portNumber, video port number i.e. 0, 1 or 2. /* Description : Configures given video port for 8–bit BT.656 non– /* continuos frame capture on channel A.
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Example 1: Noncontinuous Frame Capture for 525/60 Format /* Set last pixel to be captured in Field2 (VCA_STOP2 reg) VP_RSETH(vpCaptureHandle, VCASTOP2, VP_VCASTOP2_RMK(VCA_YSTOP2, VCA_XSTOP2)); */ /* Set first pixel to be captured in Field1 (VCA_STRT1 reg) VP_RSETH(vpCaptureHandle, VCASTRT1, VP_VCASTRT1_RMK(VCA_YSTART1, VP_VCASTRT1_SSE_ENABLE, VCA_XSTART1)); */ /* Set first pixel to be captured in Field2 (VCA_STRT2 reg) VP_RSETH(vpCaptureHandle, VCASTRT2, VP_VCASTRT2_RMK(VCA_YSTART2, VCA_XSTART2)); */
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Example 1: Noncontinuous Frame Capture for 525/60 Format /* –––––––––––––– */ /* enable capture */ /* –––––––––––––– */ /* set VCEN bit to enable capture VP_FSETH(vpCaptureHandle, VCACTL, VCEN, VP_VCACTL_VCEN_ENABLE); */ /* clear BLKCAP in VCA_CTL to enable capture DMA events VP_FSETH(vpCaptureHandle, VCACTL, BLKCAP, VP_VCACTL_BLKCAP_CLEAR); */ } /*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– /* Function : VPCapChaAIsr /* Description : This capture ISR clears FRMC to continue captur
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Example 1: Noncontinuous Frame Capture for 525/60 Format if(vpis & _VP_VPIS_SFDA_MASK) /* short field detect { capChaAShortFieldDetect++; VP_FSETH(vpCaptureHandle, VPIS, SFDA, VP_VPIS_SFDA_CLEAR); } */ if(vpis & _VP_VPIS_LFDA_MASK) /* long field detect { capChaALongFieldDetect++; VP_FSETH(vpCaptureHandle, VPIS, LFDA, VP_VPIS_LFDA_CLEAR); } */ } /*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– /* Function : setupVPCapChaAEDMA /* Input(s) : portNumber, video port number i.e. 0, 1 or 2.
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Example 1: Noncontinuous Frame Capture for 525/60 Format /* Configure Cb EDMA channel to move data from CbSRCA /* (FIFO) to Cb–data buffer, capChaACbSpace configVPCapEDMAChannel(&hEdmaVPCapChaACb, UEvent, &edmaCapChaACbTccNum, vpCaptureHandle–>cbsrcaAddr, (Uint32)capChaACbSpace, VCA_Y_EDMA_FRMCNT, VCA_Y_EDMA_ELECNT/2); /* (1/2) of Y–samples */ */ /* Configure Cr EDMA channel to move data from CrSRCA /* (FIFO) to Cr–data buffer, capChaACrSpace configVPCapEDMAChannel(&hEdmaVPCapChaACr, VEvent, &edmaCapChaA
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Example 1: Noncontinuous Frame Capture for 525/60 Format void configVPCapEDMAChannel(EDMA_Handle *edmaHandle, Int32 eventId, Int32 *tccNum, Uint32 srcAddr, Uint32 dstAddr, Uint32 frameCount, Uint32 elementCount) { Int32 tcc = 0; /* Open Y EVT EDMA channel *edmaHandle = EDMA_open(eventId, EDMA_OPEN_RESET); */ if(*edmaHandle == EDMA_HINV) test_exit(FAIL); /* allocate TCC for Y event if((tcc = EDMA_intAlloc(–1)) == –1) test_exit(FAIL); */ /* Configure EDMA parameters EDMA_configArgs( *edmaHandle, EDMA_OPT
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Example 2: Noncontinuous Frame Display for 525/60 Format A.2 Example 2: Noncontinuous Frame Display for 525/60 Format This is an example that explains how to configure the video port for 8-bit BT.656 noncontinuous frame display for 525/60 format. See ITU–R BT.656–4 and video port specification (Figures 4–11, 4–33, 4–34, and Table 4–37) for more details on 525/60 format. For simplicity, this example does not contain any margins; that is, both vertical and horizontal offsets are zero.
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Example 2: Noncontinuous Frame Display for 525/60 Format /* ––––––––––––––––––––––––––––––––––––––––––––––––– */ /* Define vertical blanking bit(VD_VBITn) reg values */ /* ––––––––––––––––––––––––––––––––––––––––––––––––– */ #define VD_VBIT_SET1 1 /* first line with an EAV with V=1 /* indicating the start of Field1 /* vertical blanking #define VD_VBIT_CLR1 20 /* first line with an EAV with V=0 /* indicating the start of Field1 /* active display #define VD_VBLNK1_SIZE (VD_VBIT_CLR1 – VD_VBIT_SET1) /* 19 lin
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Example 2: Noncontinuous Frame Display for 525/60 Format /* –––––––––––––––––––––––––––––––––––––––––– */ /* Define vertical synchronization for field2 */ /* –––––––––––––––––––––––––––––––––––––––––– */ #define VD_VSYNC_XSTART2 360 #define VD_VSYNC_YSTART2 266 #define VD_VSYNC_XSTOP2 360 #define VD_VSYNC_YSTOP2 269 /* –––––––––––––––––––––––––––––––––––––––– /* Define image offsets for both the fields /* which are zero in this example /* –––––––––––––––––––––––––––––––––––––––– #define VD_IMG_HOFF1 0 #def
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Example 2: Noncontinuous Frame Display for 525/60 Format /******************************************************************/ /* Description : 8–bit BT.656 non–continuous frame display */ /* */ /* Some important field descriptions: */ /* */ /* DMODE = 000, 8–bit BT.
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Example 2: Noncontinuous Frame Display for 525/60 Format /*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– /* Function : bt656_8bit_ncfd /* Input(s) : portNumber, video port number i.e. 0, 1 or 2. /* Description : Configures given video port for 8–bit BT.656 non– /* continuous frame display.
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Example 2: Noncontinuous Frame Display for 525/60 Format /* set vertical blanking start for field2 VP_RSETH(vpDisplayHandle , VDVBLKS2, VP_VDVBLKS2_RMK(VD_VBLNK_YSTART2, VD_VBLNK_XSTART2)); */ /* set vertical blanking end for field2 VP_RSETH(vpDisplayHandle , VDVBLKE2, VP_VDVBLKE2_RMK(VD_VBLNK_YSTOP2, VD_VBLNK_XSTOP2)); */ /* set vertical blanking bit register for field 1(VD_VBIT1) VP_RSETH(vpDisplayHandle , VDVBIT1, VP_VDVBIT1_RMK(VD_VBIT_CLR1, VD_VBIT_SET1)); */ /* set vertical blanking bit registe
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Example 2: Noncontinuous Frame Display for 525/60 Format /* set vertical sync end for field2 (VCTL2S) VP_RSETH(vpDisplayHandle , VDVSYNE2, VP_VDVSYNE2_RMK(VD_VSYNC_YSTOP2, VD_VSYNC_XSTOP2)); */ /* Let clipping values to be their defaults (VD_CLIP) */ /* No need to set DEF_VAL and VD_RELOAD in this example */ /* set event register VP_RSETH(vpDisplayHandle , VDDISPEVT, VP_VDDISPEVT_RMK(VD_DISPEVT2, VD_DISPEVT1)); */ /* Vertical interrupts are not used in this example (VD_VINT) */ /* set threshold v
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Example 2: Noncontinuous Frame Display for 525/60 Format /* –––––––––––––– */ /* enable display */ /* –––––––––––––– */ /* set VDEN to enable display for loop–back VP_FSETH(vpBDisplayHandle, VDCTL, VDEN, VP_VDCTL_VDEN_ENABLE); */ /* clear BLKDIS in VD_CTL to enable display DMA events VP_FSETH(vpBDisplayHandle, VDCTL, BLKDIS, VP_VDCTL_BLKDIS_CLEAR); */ } /*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– /* Function : VPDispIsr /* Description : This display ISR clears FRMD to continue di
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Example 2: Noncontinuous Frame Display for 525/60 Format /*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– /* Function : setupVPDispEDMA /* Input(s) : portNumber, video port number i.e. 0,1 or 2. /* Description : Sets up DMA channels for Y, U, V events for VP /* display.
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Example 2: Noncontinuous Frame Display for 525/60 Format /* enable three EDMA channels EDMA_enableChannel(hEdmaVPDispY); EDMA_enableChannel(hEdmaVPDispCb); EDMA_enableChannel(hEdmaVPDispCr); */ } /*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– /* Function : configVPDispEDMAChannel /* /* Input(s) : edmaHandle – pointer to EDMA handle. /* eventId – EDMA eventId. /* tccNum – pointer to transfer complete number. /* srcAddr – source address for EDMA transfer.
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Example 2: Noncontinuous Frame Display for 525/60 Format /* Configure EDMA parameters EDMA_configArgs( *edmaHandle, EDMA_OPT_RMK( EDMA_OPT_PRI_MEDIUM, /* medium priority EDMA_OPT_ESIZE_32BIT, /* Element size 32 bits EDMA_OPT_2DS_YES, /* 2–dimensional source EDMA_OPT_SUM_INC, /* source address auto increment EDMA_OPT_2DD_NO, /* 1–dimensional destination(FIFO) EDMA_OPT_DUM_NONE, /* fixed dest address mode(FIFO) EDMA_OPT_TCINT_YES, /* Enable transfer complete /* indication EDMA_OPT_TCC_OF(tcc & 0xF), EDMA_OPT
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Index Index A ancillary data capture 3-31 ancillary data display 4-25 architecture 1-3 ATC bit in TSISTCMPL 3-78 in TSISTCMPM 3-79 ATCM bit in TSISTMSKL 3-80 in TSISTMSKM 3-81 B BLKCAP bit in VCACTL 3-53 in VCBCTL 3-68 BLKDIS bit 4-55 block diagrams 16/20-bit raw video capture FIFO configuration 1-9 16/20-bit raw video display FIFO configuration 1-11 8/10-bit locked raw video display FIFO configuration 1-11 8/10-bit raw video capture FIFO configuration 1-7 8/10-bit raw video display FIFO configuration 1-1
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Index CbDEFVAL bits 4-86 CBDST 4-96 CBSRCx 3-83 CCMPA bit in VPIE 2-21 in VPIS 2-24 CCMPB bit in VPIE 2-21 in VPIS 2-24 CF1 bit in VCACTL 3-53 in VCBCTL 3-68 CF2 bit in VCACTL 3-53 in VCBCTL 3-68 CLASS bits 5-3 CLIPCHIGH bits 4-85 CLIPCLOW bits 4-85 CLIPYHIGH bits 4-85 CLIPYLOW bits 4-85 clocks 2-12 CMODE bits in VCACTL 3-53 in VCBCTL 3-68 CON bit 4-55 in VCACTL 3-53 in VCBCTL 3-68 COVRA bit in VPIE 2-21 in VPIS 2-24 COVRB bit in VPIE 2-21 in VPIS 2-24 Cr FIFO destination register (CRDST) 4-96 Cr FIFO sour
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Index F G F1C bit 3-50 F1D bit 4-53 F2C bit 3-50 F2D bit 4-53 GO bit 6-6 GPIO bit in VPIE 2-21 in VPIS 2-24 GPIO registers 5-2 FBITCLR bits 4-89 FBITSET bits 4-89 H FIFO overrun BT.656 mode 3-45 raw data mode 3-47 TSI capture mode 3-48 video display 4-51 Y/C mode 3-45 FIFO packing BT.656 mode 3-9 raw data mode 3-33 TSI capture mode 3-41 Y/C mode 3-14 FIFO unpacking BT.
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Index LFDE bit in VCACTL in VCBCTL 3-53 3-68 M mode selection TSI capture 3-2 video capture 3-2 video display 4-2 N NH bit in VDIMGOFF1 4-69 in VDIMGOFF2 4-71 noncontinuous frame capture for 525/60 format example A-2 noncontinuous frame display for 525/60 format example A-10 notational conventions iii NV bit in VDIMGOFF1 4-69 in VDIMGOFF2 4-71 O overview 1-2 VIC port 6-2 video capture 3-1 P PCR 5-4 PCR bits 3-76 PCR header 3-39 PCRE bits 3-77 PCRM bit 3-77 PDCLR 5-17 PDCLRn bits 5-17 PDIN 5-11 PDINn b
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Index registers (continued) VIC port 6-5 VIC clock divider register (VICDIV) 6-9 VIC control register (VICCTL) 6-6 VIC input register (VICIN) 6-8 video capture 3-49 Cb FIFO source register (CBSRCx) 3-83 channel A control register (VCACTL) 3-53 channel A event count register (VCAEVTCT) 3-67 channel A field 1 start register (VCASTRT1) 3-58 channel A field 1 stop register (VCASTOP1) 3-60 channel A field 2 start register (VCASTRT2) 3-61 channel A field 2 stop register (VCASTOP2) 3-62 channel A status register
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Index registers (continued) video display frame size register (VDFRMSZ) 4-60 horizontal blanking register (VDHBLNK) 4-61 horizontal synchronization register (VDHSYNC) 4-78 recommended values 4-94 status register (VDSTAT) 4-53 threshold register (VDTHRLD) 4-76 vertical interrupt register (VDVINT) 4-88 Y FIFO destination register A (YDSTA) 4-96 Y FIFO destination register B (YDSTB) 4-96 video port 2-16 control register (VPCTL) 2-17 interrupt enable register (VPIE) 2-21 interrupt status register (VPIS) 2-24 p
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Index TSI clock initialization LSB register (TSICLKINITL) 3-74 TSI clock initialization MSB register (TSICLKINITM) 3-75 TSI system time clock compare LSB register (TSISTCMPL) 3-78 TSI system time clock compare mask LSB register (TSISTMSKL) 3-80 TSI system time clock compare mask MSB register (TSISTMSKM) 3-81 TSI system time clock compare MSB register (TSISTCMPM) 3-79 TSI system time clock LSB register (TSISTCLKL) 3-76 TSI system time clock MSB register (TSISTCLKM) 3-77 TSI system time clock ticks interrupt
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Index VDCLIP 4-85 VDCTL 4-55 VDDEFVAL 4-86 VDDISPEVT 4-84 VDEN 4-55 VDFBIT 4-89 VDFLD bit 4-53 VDFLDT1 4-74 VDFLDT2 4-75 VDFRMSZ 4-60 VDHBLNK 4-61 VDHSYNC 4-78 VDIMGOFF1 4-68 VDIMGOFF2 4-71 VDIMGSZ1 4-70 VDIMGSZ2 4-73 VDRELOAD 4-83 VDSTAT 4-53 VDTHRLD 4-76 VDTHRLD1 bits 4-76 VDTHRLD2 bits 4-76 VDVBIT1 4-90 VDVBIT2 4-92 VDVBLKE1 4-64 VDVBLKE2 4-67 VDVBLKS1 4-62 VDVBLKS2 4-65 VDVINT 4-88 VDVSYNE1 4-80 VDVSYNE2 4-82 VDVSYNS1 4-79 VDVSYNS2 4-81 VDXPOS bits 4-53 VDYPOS bits 4-53 VIC clock divider register (VICD
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Index video capture channel B vertical interrupt register (VCBVINT) 3-63 video capture FIFO configurations 1-6 video capture mode BT.
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Index video port FIFO VPCTL 1-5 2-17 video port interrupt enable register (VPIE) 2-21 video port interrupt status register (VPIS) 2-24 video port peripheral control register (PCR) 5-4 VPHLT bit video port peripheral identification register (VPPID) 5-3 video port pin data clear register (PDCLR) VPPID 2-21 VPIS 2-24 5-3 VPRST bit 5-17 video port pin data input register (PDIN) 5-11 video port pin data output register (PDOUT) 5-13 video port pin data set register (PDSET) 5-15 video port pin directi