TMS320DM357 DMSoC Universal Serial Bus (USB) Controller User's Guide Literature Number: SPRUGH3 November 2008
SPRUGH3 – November 2008 Submit Documentation Feedback
Contents Preface....................................................................................................................................... 11 1 Introduction ....................................................................................................................... 14 1.1 2 3 4 Purpose of the Peripheral .............................................................................................. 14 ................................................................................
www.ti.com 4.17 Transmit CPPI Masked Status Register (TCPPIMSKSR) .......................................................... 95 4.18 Transmit CPPI Raw Status Register (TCPPIRAWSR) 4.19 4.20 4.21 4.22 4.23 4.24 4.25 4.26 4.27 4.28 4.29 4.30 4.31 4.32 4.33 4.34 4.35 4.36 4.37 4.38 4.39 4.40 4.41 4.42 4.43 4.44 4.45 4.46 4.47 4.48 4.49 4.50 4.51 4.52 4.53 4.54 4.55 4.56 4.57 4.58 4.59 4.60 4.61 4.62 4.63 4.64 4.65 4 Contents .............................................................
www.ti.com ................................................................ 129 ................................................... 129 4.68 NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) .................................................... 130 4.69 Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) .......................................... 130 4.70 Receive Type Register (Host mode only) (HOST_RXTYPE) ................................................... 131 4.
www.ti.com List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 6 Functional Block Diagram ................................................................................................. 15 Interrupt Service Routine Flow Chart .................................................................................... 25 CPU Actions at Transfer Phases ....................................................
www.ti.com 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1) ........................................................ Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2) ........................................................ Receive CPPI DMA State Word 3 (RCPPIDMASTATEW3) ........................................................
www.ti.com List of Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 8 USB Pins .................................................................................................................... 23 PERI_TXCSR Register Bit Configuration for Bulk IN Transactions ................................................. 37 PERI_RXCSR Register Bit Configuration for Bulk OUT Transactions ..................................
www.ti.com 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Transmit CPPI DMA State Word 4 (TCPPIDMASTATEW4) Field Descriptions .................................. Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5) Field Descriptions .................................. Transmit CPPI Completion Pointer (TCPPICOMPPTR) Field Descriptions.......................................
www.ti.com 101 102 103 104 A-1 10 Transmit Hub Port (TXHUBPORT) Field Descriptions ............................................................... Receive Function Address (RXFUNCADDR) Field Descriptions ................................................... Receive Hub Address (RXHUBADDR) Field Descriptions .......................................................... Receive Hub Port (RXHUBPORT) Field Descriptions ............................................................... Document Revision History .....
Preface SPRUGH3 – November 2008 Read This First About This Manual This document describes the universal serial bus (USB) controller in the TMS320DM357 Digital Media System-on-Chip (DMSoC). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. • Registers in this document are shown in figures and described in tables.
Notational Conventions www.ti.com SPRUG28 — TMS320DM357 DMSoC 64-Bit Timer User's Guide. Describes the operation of the software-programmable 64-bit timer in the TMS320DM357 Digital Media System-on-Chip (DMSoC). Timer 0 and Timer 1 are used as general-purpose (GP) timers and can be programmed in 64-bit mode, dual 32-bit unchained mode, or dual 32-bit chained mode; Timer 2 is used only as a watchdog timer.
www.ti.com Notational Conventions SPRUG37 — TMS320DM357 DMSoC Pulse-Width Modulator (PWM) Peripheral User's Guide. Describes the pulse-width modulator (PWM) peripheral in the TMS320DM357 Digital Media System-on-Chip (DMSoC). SPRUG38 — TMS320DM357 DMSoC DDR2 Memory Controller User's Guide. Describes the DDR2 memory controller in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The DDR2 memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM devices.
User's Guide SPRUGH3 – November 2008 Universal Serial Bus (USB) Controller 1 Introduction This document describes the universal serial bus (USB) controller in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The controller supports high-speed USB peripheral mode and high-speed limited host-mode operations. The USB controller can be operated by ARM through the memory-mapped registers. Note: The High-Speed USB OTG Controller is an instantiation of the MUSBMHDRC from Mentor Graphics Corporation.
Introduction www.ti.com 1.4 Functional Block Diagram The USB functional block diagram is shown in Figure 1. Figure 1. Functional Block Diagram Internal bus CPPI DMA engine FIFO Packet encode/ decode Registers, interrupts, endpoint control, and packet scheduling SPRUGH3 – November 2008 Submit Documentation Feedback USB 2.
Introduction 1.5 www.ti.com Supported Use Case Examples The USB supports the following user cases: Detailed information about the architecture and operation of the USB controller follows in Section 2. Programming examples are also provided for each of the operational modes of the controller. User Case 1: An example of how to initialize the USB controller Example 1.
Introduction www.ti.com User Case 2: An example of how to program the USB Endpoints in peripheral mode Example 2. Programming the USB Endpoints in Peripheral Mode // DMA channel number. int CHAN_NUM = 0; // // // // // // // // // // // Valid values are 0, 1, 2, or 3. Fifo sizes: uncomment the desired size. This example uses 64-byte fifo.
Introduction www.ti.com User Case 3: An example of how to program the USB endpoints in host mode Example 3. Programming the USB Endpoints in Host Mode // DMA channel number. int CHAN_NUM = 0; // // // // // // // // // // // Valid values are 0, 1, 2, or 3. Fifo sizes: uncomment the desired size. This example uses 64-byte fifo.
Introduction www.ti.com Example 3.
Introduction www.ti.com User Case 4: An example of how to do host negotiation to support USB If the HOSTREQ bit in the DEVCTL register is set, host negotiation is performed by the hardware when the device enters suspend mode. The bit is cleared when host negotiation is complete. User Case 5: An example of how to program the USB DMA controller Example 4.
Introduction www.ti.com Example 4. Programming the USB DMA Controller (continued) usbRegs->CHANNEL[i].RCPPIDMASTATEW6 = 0; tx_desc[i] = 0; rx_desc[i] = 0; } // Routine to flush TX fifo.
Introduction www.ti.com Example 4. Programming the USB DMA Controller (continued) // Increment descriptor counter tx_desc[ch]++; } // Routine to start the RX DMA for a given channel void start_rx_dma(int ch) { int index_save; index_save = usbRegs->INDEX; // Save the index to restore later // Must have at least 3 descriptors to receive anything if (rx_desc[ch] < 2) {error++;} else { usbRegs->INDEX = ch+1; usbRegs->RCPPICR = 1; //Enable Rx CPPI DMA usbRegs->CHANNEL[ch].
Peripheral Architecture www.ti.com 2 Peripheral Architecture 2.1 Clock Control Information related to clock generation and control for the USB peripheral will be added in a future revision of this document. Clocks for USB are generated based on a crystal oscillator on the M24XI and M24XO pins. The oscillator is enabled by bit OSCPDWN of the USBPHY_CTL register in the system module. 2.2 Signal Descriptions The USB controller provides the following I/O signals.
USB Controller Host and Peripheral Modes Operation 2.4 www.ti.com USB PHY Initialization The following bits in USBPHY_CTL must be cleared to enable the USB controller: OSCPDWN and PHYPDWN. The following bits in USBPHY_CTL must be set to enable the level comparators: VBDTCTEN and VBUSENS. After this configuration is in place, wait until the PLL clock is good prior to continuing, i.e., wait until USBPHY_CTL.PHYCLKGD bit is set. 2.
USB Controller Host and Peripheral Modes Operation www.ti.com Figure 2.
USB Controller Host and Peripheral Modes Operation 3.1 USB Controller Peripheral Mode Operation • • • • Soft connect - After a reset, the SOFTCONN bit of POWER register (bit 6) is cleared to 0. The controller will therefore appear disconnected until the software has set the SOFTCONN bit to 1. The application software can then choose when to set the PHY into its normal mode.
USB Controller Host and Peripheral Modes Operation www.ti.com Note: 3.1.1.1 The Setup packet associated with any standard device request should include an 8-byte command. Any setup packet containing a command field of anything other than 8 bytes will be automatically rejected by the controller. Zero Data Requests Zero data requests have all their information included in the 8-byte command and require no additional data to be transferred.
USB Controller Host and Peripheral Modes Operation www.ti.com If the length of the data associated with the request (indicated by the wLength field in the command) is greater than the maximum packet size for endpoint 0, further data packets will be sent. In this case, PERI_CSR0 should be written to set the SERV_RXPKTRDY bit, but the DATAEND bit should not be set.
USB Controller Host and Peripheral Modes Operation www.ti.com 3.1.1.4 Endpoint 0 States When the USB controller is operating as a peripheral device, the endpoint 0 control needs three modes – IDLE, TX and RX – corresponding to the different phases of the control transfer and the states endpoint 0 enters for the different phases of the transfer (described in later sections). The default mode on power-up or reset should be IDLE.
USB Controller Host and Peripheral Modes Operation www.ti.com Figure 4. Sequence of Transfer Idle Sequence #1 CPU actions Setup TX state Int Unload device req. and clear RxPktRdy IN data phase Int IN data phase Load FIFO and set TxPktRdy Setup Int Load FIFO and set TxPktRdy Idle Sequence #2 Idle IN data phase Int OUT data phase Int Unload device req.
USB Controller Host and Peripheral Modes Operation www.ti.com 3.1.1.5 Endpoint 0 Service Routine An Endpoint 0 interrupt is generated when: • The controller sets the RXPKTRDY bit of PERI_CSR0 (bit 0) after a valid token has been received and data has been written to the FIFO. • The controller clears the TXPKTRDY bit of PERI_CSR0 (bit 1) after the packet of data in the FIFO has been successfully transmitted to the host.
USB Controller Host and Peripheral Modes Operation www.ti.com Figure 5.
USB Controller Host and Peripheral Modes Operation www.ti.com 3.1.1.5.1 IDLE Mode IDLE mode is the mode the endpoint 0 control must select at power-on or reset and is the mode to which the endpoint 0 control should return when the RX and TX modes are terminated. It is also the mode in which the SETUP phase of control transfer is handled (as outlined in Figure 6). Figure 6.
USB Controller Host and Peripheral Modes Operation 3.1.1.5.2 www.ti.com TX Mode When the endpoint is in TX state all arriving IN tokens need to be treated as part of a data phase until the required amount of data has been sent to the host. If either a SETUP or an OUT token is received while the endpoint is in the TX state, this will cause a SetupEnd condition to occur as the core expects only IN tokens. See Figure 7.
USB Controller Host and Peripheral Modes Operation www.ti.com 3.1.1.5.3 RX Mode In RX mode, all arriving data should be treated as part of a data phase until the expected amount of data has been received. If either a SETUP or an IN token is received while the endpoint is in RX state, a SetupEnd condition will occur as the controller expects only OUT tokens. Three events can cause RX mode to be terminated before the expected amount of data has been received as shown in Figure 8: 1.
USB Controller Host and Peripheral Modes Operation 3.1.1.5.4 www.ti.com Error Handling A control transfer may be aborted due to a protocol error on the USB, the host prematurely ending the transfer, or if the software wishes to abort the transfer (e.g., because it cannot process the command).
USB Controller Host and Peripheral Modes Operation www.ti.com 3.1.2 Bulk Transactions 3.1.2.1 Peripheral Mode: Bulk In Transactions A Bulk IN transaction is used to transfer non-periodic data from the USB peripheral device to the host. The following optional features are available for use with a Tx endpoint used in peripheral mode for Bulk IN transactions: • Double packet buffering: When enabled, up to two packets can be stored in the FIFO awaiting transmission to the host.
USB Controller Host and Peripheral Modes Operation 3.1.2.1.2 www.ti.com Operation When data is to be transferred over a Bulk IN pipe, a data packet needs to be loaded into the FIFO and the PERI_TXCSR register written to set the TXPKTRDY bit (bit 0). When the packet has been sent, the TXPKTRDY bit will be cleared by the USB controller and an interrupt generated so that the next packet can be loaded into the FIFO.
USB Controller Host and Peripheral Modes Operation www.ti.com 3.1.2.2.1 Setup In configuring an Rx endpoint for Bulk OUT transactions, the RXMAXP register must be written with the maximum packet size (in bytes) for the endpoint. This value should be the same as the wMaxPacketSize field of the Standard Endpoint Descriptor for the endpoint.
USB Controller Host and Peripheral Modes Operation 3.1.2.2.3 www.ti.com Error Handling If the software wants to shut down the Bulk OUT pipe, it should set the SENDSTALL bit (bit 5 of PERI_RXCSR). When the controller receives the next packet it will send a STALL to the host, set the SENTSTALL bit (bit 6 of PERI_RXCSR) and generate an interrupt. When the software receives an interrupt with the SENTSTALL bit (bit 6 of PERI_RXCSR) set, it should clear this bit.
USB Controller Host and Peripheral Modes Operation www.ti.com 3.1.4 Isochronous Transactions 3.1.4.1 Isochronous IN Transactions An Isochronous IN transaction is used to transfer periodic data from the function controller to the host. The following optional features are available for use with a Tx endpoint used in Peripheral mode for Isochronous IN transactions: • Double packet buffering: When enabled, up to two packets can be stored in the FIFO awaiting transmission to the host.
USB Controller Host and Peripheral Modes Operation www.ti.com An interrupt is generated whenever a packet is sent to the host and the software may use this interrupt to load the next packet into the FIFO and set the TXPKTRDY bit in the PERI_TXCSR register (bit 0) in the same way as for a Bulk Tx endpoint. As the interrupt could occur almost any time within a frame(/microframe), depending on when the host has scheduled the transaction, this may result in irregular timing of FIFO load requests.
USB Controller Host and Peripheral Modes Operation www.ti.com 3.1.4.2.1 Setup In configuring an Rx endpoint for Isochronous OUT transactions, the RXMAXP register must be written with the maximum packet size (in bytes) for the endpoint. This value should be the same as the wMaxPacketSize field of the Standard Endpoint Descriptor for the endpoint.
USB Controller Host and Peripheral Modes Operation 3.2 USB Controller Host Mode Operation • • • • 3.2.1 www.ti.com Entry into Suspend mode. When operating as a host, the controller can be prompted to enter Suspend mode by setting the SUSPENDM bit in the POWER register. When this bit is set, the controller will complete the current transaction then stop the transaction scheduler and frame counter. No further transactions will be started and no SOF packets will be generated.
USB Controller Host and Peripheral Modes Operation www.ti.com 3.2.1.1 Setup Phase For the SETUP Phase of a control transaction (Figure 9), the software driving the US host device needs to: 1. Load the 8 bytes of the required Device request command into the Endpoint 0 FIFO. 2. Set SETUPPKT and TXPKTRDY (bits 3 and 1 of HOST_CSR0, respectively). Note: These bits must be set together.
USB Controller Host and Peripheral Modes Operation www.ti.com 3. At the end of the attempt to send the data, the controller will generate an Endpoint 0 interrupt. The software should then read HOST_CSR0 to establish whether the RXSTALL bit (bit 2), the ERROR bit (bit 4) or the NAK_TIMEOUT bit (bit 7) has been set. If RXSTALL is set, it indicates that the target did not accept the command (e.g., because it is not supported by the target device) and so has issued a STALL response.
USB Controller Host and Peripheral Modes Operation www.ti.com Figure 10.
USB Controller Host and Peripheral Modes Operation www.ti.com If NAK_TIMEOUT is set, it means that the controller has received a NAK response to each attempt to send the OUT token, for longer than the time set in the HOST_NAKLIMIT0 register. The controller can then be directed either to continue trying this transaction (until it times out again) by clearing the NAK_TIMEOUT bit or to abort the transaction by flushing the FIFO before clearing the NAK_TIMEOUT bit.
USB Controller Host and Peripheral Modes Operation www.ti.com 3.2.1.4 IN Status Phase (following SETUP Phase or OUT Data Phase) For the IN Status Phase of a Control Transaction (Figure 12), the software driving the USB Host device needs to: 1. Set the STATUSPKT and REQPKT bits of HOST_CSR0 (bit 6 and bit 5, respectively). 2. Wait while the controller sends an IN token and receives a response from the USB peripheral device. Figure 12.
USB Controller Host and Peripheral Modes Operation www.ti.com 3. When the controller generates the Endpoint 0 interrupt, read HOST_CSR0 to establish whether the RXSTALL bit (bit 2), the ERROR bit (bit 4), the NAK_TIMEOUT bit (bit 7) or RXPKTRDY bit (bit 0) has been set. If RXSTALL bit is set, it indicates that the target could not complete the command and so has issued a STALL response.
USB Controller Host and Peripheral Modes Operation www.ti.com Figure 13.
USB Controller Host and Peripheral Modes Operation 3.2.2 www.ti.com Bulk Transactions 3.2.2.1 Host Mode: Bulk IN Transactions A Bulk IN transaction may be used to transfer non-periodic data from the external USB peripheral to the host. The following optional features are available for use with an Rx endpoint used in host mode to receive the data: • Double packet buffering: When enabled, up to two packets can be stored in the FIFO on reception from the host.
USB Controller Host and Peripheral Modes Operation www.ti.com 3.2.2.1.2 Operation When Bulk data is required from the USB peripheral device, the software should set the REQPKT bit in the corresponding HOST_RXCSR register (bit 5). The controller will then send an IN token to the selected peripheral endpoint and waits for data to be returned. If data is correctly received, RXPKTRDY bit of HOST_RXCSR (bit 0) is set.
USB Controller Host and Peripheral Modes Operation • • • www.ti.com The HOST_TXINTERVAL register needs to be written with the required value for the NAK limit (2 - 215 frames/microframes), or cleared to 0 if the NAK timeout feature is not required. The relevant interrupt enable bit in the INTRTXE register should be set (if an interrupt is required for this endpoint).
USB Controller Host and Peripheral Modes Operation www.ti.com 3.2.4 Isochronous Transactions 3.2.4.1 Host Mode: Isochronous IN Transactions An Isochronous IN transaction is used to transfer periodic data from the USB peripheral to the host. The following optional features are available for use with an Rx endpoint used in Host mode to receive this data: • Double packet buffering: When enabled, up to two packets can be stored in the FIFO on reception from the host.
USB Controller Host and Peripheral Modes Operation www.ti.com FIFO unload requests will probably be irregular. If the data sink for the endpoint is going to some external hardware, it may be better to minimize the requirement for additional buffering by waiting until the end of each frame before unloading the FIFO. This can be done by using the SOF_PULSE signal from the controller to trigger the unloading of the data packet. The SOF_PULSE is generated once per frame(/microframe).
USB Controller Host and Peripheral Modes Operation www.ti.com 3.2.4.2.2 Operation The operation starts when the software writes to the FIFO and sets TXPKTRDY bit of HOST_TXCSR (bit 0). This triggers the controller to send an OUT token followed by the first data packet from the FIFO.
USB Controller Host and Peripheral Modes Operation • • www.ti.com End of queue (EOQ) (only valid on EOP) Packet Length (only valid with SOP) Transmit buffer descriptors contain 16 bytes (4 words) and must begin on 16-byte aligned addresses. Transmit buffer descriptors may be linked together to form packets. Buffer descriptor SOP and EOP bits are used to delimit packets. Packets in turn may be linked together to form transmit queue.
USB Controller Host and Peripheral Modes Operation www.ti.com Table 9. Transmit Buffer Descriptor Word 3 (continued) Bits Name 28 EOQ Value Description End of Queue: The End of Queue bit is set by the DMA controller to indicate that all packets in the queue have been transmitted and the Tx queue is empty. This bit is valid only on when EOP is set.
USB Controller Host and Peripheral Modes Operation 3.3.1.4 www.ti.com Transmit Queue Figure 14 shows a Tx queue. Tx queue provide a logical queue of DMA packets for transmission through a channel. Each channel has one dedicated Tx queues. The queue has one associated Tx Queue Head Descriptor Pointer and one associated Tx Completion Pointer container in the channel Tx DMA state. The Tx queue is linked lists of Tx buffer descriptors that constitute one or more packets queued for transmission.
USB Controller Host and Peripheral Modes Operation www.ti.com clear the Ownership bit in the DMA packet’s SOP buffer descriptor and issue an interrupt to the processor by writing the DMA packet’s last buffer descriptor address to the queue’s Tx DMA State Completion Pointer (TCPPICOMPPTR register).
USB Controller Host and Peripheral Modes Operation www.ti.com RNDIS Mode Setup The setup of RNDIS mode DMA is similar to the default Transparent Mode as mentioned in the previous section. The following steps need to be taken for setting up RNDIS mode Tx DMA: • After reset the software must write zeroes to all Tx DMA State registers (TCPPIDMASTATEW0, TCPPIDMASTATEW1, TCPPIDMASTATEW2, TCPPIDMASTATEW3, TCPPIDMASTATEW4, TCPPIDMASTATEW5).
USB Controller Host and Peripheral Modes Operation www.ti.com 3.3.2.2 CPPI Receive Buffer Descriptor Rx buffer descriptors provide information about a single corresponding Rx data buffer.
USB Controller Host and Peripheral Modes Operation www.ti.com Table 13. Receive Buffer Descriptor Word 3 Bit Field 31 SOP 30 29 28 Value Description Start of Packet: SOP Indicates that the descriptor buffer is the first buffer in the packet. Software should clear the SOP bit when setting up the descriptor. 0 Not start of packet buffer 1 Start of packet buffer EOP End of Packet: EOP Indicates that the descriptor buffer is the last buffer in the packet.
USB Controller Host and Peripheral Modes Operation www.ti.com 3.3.2.4 Receive Queue Figure 15 shows an Rx Queue. Rx queue provide a logical queue of processor memory space for DMA packets to be received from DMA controller channel. Each channel has single Rx queue. There are no multiple queue as in transmit channels. Each queue has one associated Rx Queue Head Descriptor Pointer and one associated Rx Completion Pointer contained in the channel Rx DMA State.
USB Controller Host and Peripheral Modes Operation www.ti.com The software enables packet reception on a given channel by writing the address of the first buffer descriptor in the queue (nonzero value) to the channel’s head descriptor pointer (RCCPIDMASTATEW1) in the channel’s Rx DMA state. When packet reception begins on a given channel, the DMA controller fills each Rx buffer with data in order starting with the first buffer and proceeding through the Rx queue.
USB Controller Host and Peripheral Modes Operation www.ti.com 3.3.2.6 Receive Abort Handling The DMA controller sets ‘Rx Abort’ bit used to identify Rx packets which were aborted due to lack of buffers. Software must take care to inspect any Rx SOP packet for this bit and ignore all the buffers in that packet as the packet is incomplete. Also, for aborted packets, the packet length may not match the data size in the buffers. 3.3.2.
USB Controller Host and Peripheral Modes Operation www.ti.com If RXn_AUTOREQ (where n is the channel number) of AUTOREQ register is set with binary 11, IN tokens will be generated and sent to the target USB peripheral device even after the End Of DMA Packet is reached. This feature is useful to keep data reception operational across multiple DMA packets in a Rx queue. The host processor does not have to restart sending IN tokens for every DMA packet in the Rx queue.
USB Controller Host and Peripheral Modes Operation www.ti.com Table 15.
USB Controller Host and Peripheral Modes Operation 3.4.1 www.ti.com USB Core Interrupts There are two methods available for software to access USB core interrupts, selectable by the UINT bit of CTRLR. The UINT bit cleared to 0 selects the PDR 2.0 compliant register set (INTSRCR, INTSETR, INTCLRR, INTMSKR, INTMSKSETR, INTMSKCLRR, INTMASKEDR). This is the default, and should be used for most systems. The DRVVBUS level change interrupt is only available in the PDR compliant register.
www.ti.com 3.5.1 USB Controller Host and Peripheral Modes Operation TEST_SE0_NAK To enter the Test_SE0_NAK test mode, the software should set the Test_SE0-NAK bit by writing 0x01 to the TestMode register. The controller will then go into a mode in which it responds to any valid IN token with a NAK. 3.5.2 TEST_J To enter the Test_J test mode, the software should set the Test_J bit by writing 0x02 to the TestMode register.
USB Controller Host and Peripheral Modes Operation 3.5.4 www.ti.com TEST_PACKET To execute the Test_Packet, the software should: 1. Start a session (if the core is being used in Host mode). 2. Write the standard test packet (shown below) to the Endpoint 0 FIFO. 3. Write 0x8 to the TestMode register to enter Test_Packet test mode. 4. Set the TxPktRdy bit in the CSR0 register (D1). The 53 by test packet to load is as follows (all bytes in hex).
www.ti.com 3.5.6 USB Controller Host and Peripheral Modes Operation FORCE_HOST The Force Host test mode enables the user to instruct the core to operate in Host mode, regardless of whether it is actually connected to any peripheral, i.e., the state of the CID input and the LINESTATE and HOSTDISCON signals are ignored. (While in this mode, the state of the HOSTDISCON signal can be read from bit 7 of the DevCtl register.
USB Controller Host and Peripheral Modes Operation 3.6 www.ti.com Reset Considerations The USB controller has two reset sources: hardware reset and the soft reset (RESET bit in CTRLR register). 3.6.1 Software Reset Considerations When the RESET bit in CTRLR is set, all the USB controller registers and DMA operations are reset. The bit is cleared automatically. A software reset on the ARM or DSP CPUs does not affect the register values and operation of the USB controller. 3.6.
Registers www.ti.com 4 Registers Table 16 lists the memory-mapped registers for the universal serial bus (USB). See the device-specific data manual for the memory address of these registers. The base address is 01C6 4000h. Note: In some cases, a single register address can have different names or meanings depending on the mode (host/peripheral) or the setting of the index register. The meaning of some bit fields varies with the mode. Table 16.
Registers www.ti.com Table 16. Universal Serial Bus (USB) Registers (continued) Offset Acronym Register Description 124h RCPPIDMASTATEW1 Receive CPPI DMA State Word 1 Section 4.38 Section 128h RCPPIDMASTATEW2 Receive CPPI DMA State Word 2 Section 4.39 12Ch RCPPIDMASTATEW3 Receive CPPI DMA State Word 3 Section 4.40 130h RCPPIDMASTATEW4 Receive CPPI DMA State Word 4 Section 4.41 134h RCPPIDMASTATEW5 Receive CPPI DMA State Word 5 Section 4.
Registers www.ti.com Table 16. Universal Serial Bus (USB) Registers (continued) Offset Acronym Register Description 1DCh TCPPICOMPPTR Transmit CPPI Completion Pointer Section 4.36 Section 1E0h RCPPIDMASTATEW0 Receive CPPI DMA State Word 0 Section 4.37 1E4h RCPPIDMASTATEW1 Receive CPPI DMA State Word 1 Section 4.38 1E8h RCPPIDMASTATEW2 Receive CPPI DMA State Word 2 Section 4.39 1ECh RCPPIDMASTATEW3 Receive CPPI DMA State Word 3 Section 4.
Registers www.ti.com Table 16. Universal Serial Bus (USB) Registers (continued) Offset Acronym Register Description 41Bh HOST_NAKLIMIT0 Sets the NAK response timeout on Endpoint 0 (Index register set to select Endpoint 0) Section 4.68 Section HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint. (Index register set to select Endpoints 1-4) Section 4.
Registers www.ti.com Table 16. Universal Serial Bus (USB) Registers (continued) Offset Acronym Register Description Section Target Endpoint 1 Control Registers, Valid Only in Host Mode 488h TXFUNCADDR Address of the target function that has to be accessed through the associated Transmit Endpoint. Section 4.83 48Ah TXHUBADDR Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.
Registers www.ti.com Table 16. Universal Serial Bus (USB) Registers (continued) Offset Acronym Register Description 49Eh RXHUBADDR Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. Section 4.87 Section 49Fh RXHUBPORT Port of the hub that has to be accessed through the associated Receive Endpoint.
Registers www.ti.com Table 16. Universal Serial Bus (USB) Registers (continued) Offset Acronym Register Description 51Dh HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint. Section Section 4.71 Control and Status Register for Endpoint 2 520h TXMAXP Maximum Packet Size for Peripheral/Host Transmit Endpoint Section 4.
Registers www.ti.com Table 16. Universal Serial Bus (USB) Registers (continued) Offset 546h 4.1 Acronym Register Description PERI_RXCSR Control Status Register for Peripheral Receive Endpoint (peripheral mode) Section 4.62 Section HOST_RXCSR Control Status Register for Host Receive Endpoint (host mode) Section 4.63 548h RXCOUNT Number of Bytes in Host Receive endpoint FIFO Section 4.
Registers www.ti.com 4.2 Status Register (STATR) The Status Register (STATR) is shown in Figure 17 and described in Table 18. Figure 17. Status Register (STATR) 31 16 Reserved R-0 15 1 0 Reserved DRVVBUS R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 18. Status Register (STATR) Field Descriptions Bit Field 31-1 Reserved 0 DRVVBUS 4.3 Value 0 Description Reserved Current DRVVBUS value.
Registers 4.4 www.ti.com Auto Request Register (AUTOREQ) The Auto Request Register (AUTOREQ) is shown in Figure 19 and described in Table 20. Figure 19. Auto Request Register (AUTOREQ) 31 16 Reserved R-0 15 8 7 6 5 4 3 2 1 0 Reserved Rx4 Rx3 Rx2 Rx1 R-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 20.
Registers www.ti.com 4.5 USB Interrupt Source Register (INTSRCR) The USB Interrupt Source Register (INTSRCR) is shown in Figure 20 and described in Table 21. Figure 20. USB Interrupt Source Register (INTSRCR) 31 25 15 24 16 Reserved USB R-0 R-0 13 12 8 7 5 4 0 Reserved RX Reserved TX R-0 R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 21.
Registers 4.6 www.ti.com USB Interrupt Source Set Register (INTSETR) The USB Interrupt Source Set Register (INTSETR) is shown in Figure 21 and described in Table 22. Figure 21. USB Interrupt Source Set Register (INTSETR) 31 25 15 24 16 Reserved USB R-0 W-0 13 12 8 7 5 4 0 Reserved RX Reserved TX R-0 W-0 R-0 W-0 LEGEND: R = Read only; W = Write only; -n = value after reset Table 22.
Registers www.ti.com 4.7 USB Interrupt Source Clear Register (INTCLRR) The USB Interrupt Source Clear Register (INTCLRR) is shown in Figure 22 and described in Table 23. Figure 22. USB Interrupt Source Clear Register (INTCLRR) 31 25 15 24 16 Reserved USB R-0 W-0 13 12 8 7 5 4 0 Reserved RX Reserved TX R-0 W-0 R-0 W-0 LEGEND: R = Read only; W = Write only; -n = value after reset Table 23.
Registers 4.8 www.ti.com USB Interrupt Mask Register (INTMSKR) The USB Interrupt Mask Register (INTMSKR) is shown in Figure 23 and described in Table 24. Figure 23. USB Interrupt Mask Register (INTMSKR) 31 25 15 24 16 Reserved USB R-0 R-0 13 12 8 7 5 4 0 Reserved RX Reserved TX R-0 R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 24.
Registers www.ti.com 4.9 USB Interrupt Mask Set Register (INTMSKSETR) The USB Interrupt Mask Set Register (INTMSKSETR) is shown in Figure 24 and described in Table 25. Figure 24. USB Interrupt Mask Set Register (INTMSKSETR) 31 25 15 24 16 Reserved USB R-0 W-0 13 12 8 7 5 4 0 Reserved RX Reserved TX R-0 W-0 R-0 W-0 LEGEND: R = Read only; W = Write only; -n = value after reset Table 25.
Registers www.ti.com 4.10 USB Interrupt Mask Clear Register (INTMSKCLRR) The USB Interrupt Mask Clear Register (INTMSKCLRR) is shown in Figure 25 and described in Table 26. Figure 25. USB Interrupt Mask Clear Register (INTMSKCLRR) 31 25 15 24 16 Reserved USB R-0 W-0 13 12 8 7 5 4 0 Reserved RX Reserved TX R-0 W-0 R-0 W-0 LEGEND: R = Read only; W = Write only; -n = value after reset Table 26.
Registers www.ti.com 4.11 USB Interrupt Source Masked Register (INTMASKEDR) The USB Interrupt Source Masked Register (INTMASKEDR) is shown in Figure 26 and described in Table 27. Figure 26. USB Interrupt Source Masked Register (INTMASKEDR) 31 25 15 24 16 Reserved USB R-0 R-0 13 12 8 7 5 4 0 Reserved RX Reserved TX R-0 R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 27.
Registers www.ti.com 4.12 USB End of Interrupt Register (EOIR) The USB End of Interrupt Register (EOIR) is shown in Figure 27 and described in Table 28. Figure 27. USB End of Interrupt Register (EOIR) 31 16 Reserved R-0 15 8 7 0 Reserved VECTOR R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 28.
Registers www.ti.com 4.14 Transmit CPPI Control Register (TCPPICR) The Transmit CPPI Control Register (TCPPICR) is shown in Figure 29 and described in Table 30. Figure 29. Transmit CPPI Control Register (TCPPICR) 31 16 Reserved R-0 15 1 0 Reserved TCPPI_ENABLE R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 30.
Registers www.ti.com 4.16 CPPI DMA End of Interrupt Register (CPPIEOIR) Note: This register was previously named TCPPIEOIR, and that name will continue to exist in the CSL for backward compatibility. The CPPI DMA End of Interrupt Register (CPPIEOIR) is shown in Figure 31 and described in Table 32. Figure 31. CPPI DMA End of Interrupt Register (CPPIEOIR) 31 16 Reserved R-0 15 8 7 0 Reserved VECTOR R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 32.
Registers www.ti.com 4.17 Transmit CPPI Masked Status Register (TCPPIMSKSR) The Transmit CPPI Masked Status Register (TCPPIMSKSR) is shown in Figure 32 and described in Table 33. Figure 32. Transmit CPPI Masked Status Register (TCPPIMSKSR) 31 16 Reserved R-0 15 4 3 0 Reserved MASKED COMP_PENDING R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 33.
Registers www.ti.com 4.19 Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) The Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) is shown in Figure 34 and described in Table 35. Figure 34. Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) 31 16 Reserved R-0 15 4 3 0 Reserved COMP_PENDING_INTR_EN R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 35.
Registers www.ti.com 4.21 Receive CPPI Control Register (RCPPICR) The Receive CPPI Control Register (RCPPICR) is shown in Figure 36 and described in Table 37. Figure 36. Receive CPPI Control Register (RCPPICR) 31 16 Reserved R-0 15 1 0 Reserved RCPPI_ENABLE R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 37.
Registers www.ti.com 4.23 Receive CPPI Raw Status Register (RCPPIRAWSR) The Receive CPPI Raw Status Register (RCPPIRAWSR) is shown in Figure 38 and described in Table 39. Figure 38. Receive CPPI Raw Status Register (RCPPIRAWSR) 31 16 Reserved R-0 15 4 3 0 Reserved COMP_PENDING R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 39.
Registers www.ti.com 4.25 Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR) The Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR) is shown in Figure 40 and described in Table 41. Figure 40. Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR) 31 16 Reserved R-0 15 4 3 0 Reserved COMP_PENDING_INTR_EN R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 41.
Registers www.ti.com 4.27 Receive Buffer Count 1 Register (RBUFCNT1) The Receive Buffer Count 1 Register (RBUFCNT1) is shown in Figure 42 and described in Table 43. Figure 42. Receive Buffer Count 1 Register (RBUFCNT1) 31 16 Reserved R-0 15 0 BUFCNT R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 43.
Registers www.ti.com 4.29 Receive Buffer Count 3 Register (RBUFCNT3) The Receive Buffer Count 3 Register (RBUFCNT3) is shown in Figure 44 and described in Table 45. Figure 44. Receive Buffer Count 3 Register (RBUFCNT3) 31 16 Reserved R-0 15 0 BUFCNT R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 45.
Registers www.ti.com 4.31 Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1) The Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1) is shown in Figure 46 and described in Table 47. Figure 46. Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1) 31 16 SOP_DESCRIPTOR_PTR R/W-0 15 1 0 SOP_DESCRIPTOR_PTR 2 Reserved IN_PACKET R/W-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 47.
Registers www.ti.com Table 48. Transmit CPPI DMA State Word 2 (TCPPIDMASTATEW2) Field Descriptions (continued) Bit 0 Field Value Reserved Description 0 Reserved 4.33 Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3) The Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3) is shown in Figure 48 and described in Table 49. Figure 48. Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3) 31 0 CURR_BUFFER_PTR R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 49.
Registers www.ti.com Table 50. Transmit CPPI DMA State Word 4 (TCPPIDMASTATEW4) Field Descriptions (continued) Bit 15-0 Field Value CURR_BUFFER_LENGTH 0-FFFFh Description Current Buffer Length Indicates how many valid bytes remain in the current buffer that is being transmitted from 4.35 Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5) The Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5) is shown in Figure 50 and described in Table 51. Figure 50.
Registers www.ti.com Table 52. Transmit CPPI Completion Pointer (TCPPICOMPPTR) Field Descriptions Bit 31-2 Field Value DESC_ADDR Description 0-3FFF FFFFh Descriptor Address This field contains the 30-bit word aligned pointer of the end of packet descriptor that the DMA has last processed 1 Reserved 0 WRBK_MODE 0 Reserved Writeback/Compare Mode. This bit controls the action that is to be taken when this location is written. 0 Compare Mode.
Registers www.ti.com Figure 53. Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1) 31 16 RXQ_HEAD_PTR R/W-0 15 2 1 0 RXQ_HEAD_PTR Reserved R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 54.
Registers www.ti.com 4.39 Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2) The Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2) is shown in Figure 54 and described in Table 55. Figure 54. Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2) 31 16 SOP_DESCRIPTOR_PTR R/W-0 15 1 0 SOP_DESCRIPTOR_PTR 2 Reserved IN_PACKET R/W-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 55.
Registers 108 Universal Serial Bus (USB) Controller www.ti.
Registers www.ti.com 4.41 Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4) The Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4) is shown in Figure 56 and described in Table 57. Figure 56. Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4) 31 0 CURR_BUFFER_PTR R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 57.
Registers www.ti.com 4.43 Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6) The Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6) is shown in Figure 58 and described in Table 59. Figure 58. Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6) 31 16 SOP_BUFFER_BYTECNT R/W-0 15 0 CURR_BUFFER_BYTECNT R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 59.
Registers www.ti.com Table 60. Receive CPPI Completion Pointer (RCPPICOMPPTR) Field Descriptions (continued) Bit Field 0 Value Description RDBK_MODE Readback / Compare Mode 0 Compare Mode. Indicates that the value that is presented on bits 31:2 of the read data should be compared against the value that is currently contained in bits 31:2 of this location. If the two match, the interrupt bit corresponding to this Receive Queue should be deasserted. 1 Readback Mode.
Registers www.ti.com Table 62. Power Management Register (POWER) Field Descriptions (continued) Bit Field Value Description 3 RESET 0-1 This bit is set when Reset signaling is present on the bus. Note: This bit is Read/Write in Host Mode, but read-only in Peripheral Mode. 2 RESUME 0-1 Set to generate Resume signaling when the controller is in Suspend mode. The bit should be cleared after 10 ms (a maximum of 15 ms) to end Resume signaling.
Registers www.ti.com Figure 63. Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) 31 16 Reserved R-0 15 4 3 2 1 0 Reserved 5 EP4RX EP3RX EP2RX EP1RX Reserved R-0 R-0 R-0 R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 64.
Registers www.ti.com Figure 65. Interrupt Enable Register for INTRRX (INTRRXE) 15 8 Reserved R-0 7 4 3 2 1 0 Reserved 5 EP4RX EP3RX EP2RX EP1RX Reserved R-0 R/W-1 R/W-1 R/W-1 R/W-1 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 66.
Registers www.ti.com 4.51 Interrupt Register for Common USB Interrupts (INTRUSB) The Interrupt Register for Common USB Interrupts (INTRUSB) is shown in Figure 66 and described in Table 67. Reading this register causes all bits to be cleared. Note: Unless the UINT bit of CTRLR is set, do not read or write this register directly. Use the INTSRCR register instead. Figure 66.
Registers www.ti.com 4.52 Interrupt Enable Register for INTRUSB (INTRUSBE) The Interrupt Enable Register for INTRUSB (INTRUSBE) is shown in Figure 67 and described in Table 68. Note: Unless the UINT bit of CTRLR is set, do not read or write this register directly. Use the INTMSKSETR/INTMSKCLRR registers instead. Figure 67.
Registers www.ti.com 4.53 Frame Number Register (FRAME) The Frame Number Register (FRAME) is shown in Figure 68 and described in Table 69. Figure 68. Frame Number Register (FRAME) 15 11 10 0 Reserved FRAMENUMBER R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 69. Frame Number Register (FRAME) Field Descriptions Bit Field Value 15-11 Reserved 0 10-0 FRAMENUMBER Description Reserved 0-7FFh Last received frame number 4.
Registers www.ti.com 4.55 Register to Enable the USB 2.0 Test Modes (TESTMODE) The Register to Enable the USB 2.0 Test Modes (TESTMODE) is shown in Figure 70 and described in Table 71. Figure 70. Register to Enable the USB 2.0 Test Modes (TESTMODE) 7 6 5 4 3 2 1 0 FORCE_HOST FIFO_ACCESS FORCE_FS FORCE_HS TEST_PACKET TEST_K TEST_J TEST_SE0_NAK R/W-0 W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 71.
Registers www.ti.com 4.56 Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) The Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) is shown in Figure 71 and described in Table 72. Figure 71. Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) 15 11 10 0 Reserved MAXPAYLOAD R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 72.
Registers www.ti.com 4.57 Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) The Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) is shown in Figure 72 and described in Table 73. Figure 72.
Registers www.ti.com 4.58 Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) The Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) is shown in Figure 73 and described in Table 74. Figure 73.
Registers www.ti.com 4.59 Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) The Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) is shown in Figure 74 and described in Table 75. Figure 74.
Registers www.ti.com 4.60 Control Status Register for Host Transmit Endpoint (HOST_TXCSR) The Control Status Register for Host Transmit Endpoint (HOST_TXCSR) is shown in Figure 75 and described in Table 76. Figure 75.
Registers www.ti.com 4.61 Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) The Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) is shown in Figure 76 and described in Table 77. Figure 76. Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) 15 11 10 0 Reserved MAXPAYLOAD R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 77.
Registers www.ti.com 4.62 Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) The Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) is shown in Figure 77 and described in Table 78. Figure 77.
Registers www.ti.com 4.63 Control Status Register for Host Receive Endpoint (HOST_RXCSR) The Control Status Register for Host Receive Endpoint (HOST_RXCSR) is shown in Figure 78 and described in Table 79. Figure 78.
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Registers www.ti.com 4.64 Count 0 Register (COUNT0) The Count 0 Register (COUNT0) is shown in Figure 79 and described in Table 80. Figure 79. Count 0 Register (COUNT0) 15 7 6 0 Reserved EP0RXCOUNT R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 80. Count 0 Register (COUNT0) Field Descriptions Bit Field Value 15-7 Reserved 0 6-0 EP0RXCOUNT Description Reserved 0-7Fh Indicates the number of received data bytes in the Endpoint 0 FIFO.
Registers www.ti.com 4.66 Type Register (Host mode only) (HOST_TYPE0) The Type Register (Host mode only) (HOST_TYPE0) is shown in Figure 81 and described in Table 82. Figure 81. Type Register (Host mode only) (HOST_TYPE0) 7 6 5 0 SPEED Reserved R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 82.
Registers www.ti.com 4.68 NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) The NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) is shown in Figure 83 and described in Table 84. Figure 83. NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) 7 5 4 0 Reserved EP0NAKLIMIT R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 84.
Registers www.ti.com 4.70 Receive Type Register (Host mode only) (HOST_RXTYPE) The Receive Type Register (Host mode only) (HOST_RXTYPE) is shown in Figure 85 and described in Table 86. Figure 85. Receive Type Register (Host mode only) (HOST_RXTYPE) 7 6 5 4 3 0 SPEED PROT RENDPN R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 86.
Registers www.ti.com Table 87. Receive Interval Register (Host mode only) (HOST_RXINTERVAL) Field Descriptions Bit Field Value Description 7-0 POLINTVL_NAKLIMIT 0-FFh For Interrupt and Isochronous transfers, defines the polling interval for the currently-selected transmit endpoint For Bulk endpoints, this register sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses.
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Registers www.ti.com 4.73 Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) The Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) is shown in Figure 88 and described in Table 89. Figure 88. Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) 31 0 DATA R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 89.
Registers www.ti.com 4.74 Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) The Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) is shown in Figure 89 and described in Table 90. Figure 89. Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) 31 0 DATA R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 90.
Registers www.ti.com 4.76 Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) The Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) is shown in Figure 91 and described in Table 92. Figure 91. Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) 31 0 DATA R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 92.
Registers www.ti.com 4.78 OTG Device Control Register (DEVCTL) The OTG Device Control Register (DEVCTL) is shown in Figure 93 and described in Table 94. Figure 93. OTG Device Control Register (DEVCTL) 7 6 5 2 1 0 BDEVICE FSDEV LSDEV 4 VBUS 3 HOSTMODE HOSTREQ SESSION R-0 R-0 R-0 R-0 R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 94.
Registers www.ti.com 4.79 Transmit Endpoint FIFO Size (TXFIFOSZ) Section 2.5 describes dynamically setting endpoint FIFO sizes. The Transmit Endpoint FIFO Size (TXFIFOSZ) is shown in Figure 94 and described in Table 95. Figure 94. Transmit Endpoint FIFO Size (TXFIFOSZ) 7 5 4 3 0 Reserved DPB SZ R-0 R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 95.
Registers www.ti.com 4.81 Transmit Endpoint FIFO Address (TXFIFOADDR) Section 2.5 describes dynamically setting endpoint FIFO sizes. The Transmit Endpoint FIFO Address (TXFIFOADDR) is shown in Figure 96 and described in Table 97. Figure 96. Transmit Endpoint FIFO Address (TXFIFOADDR) 15 13 12 0 Reserved ADDR R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 97.
Registers www.ti.com 4.83 Transmit Function Address (TXFUNCADDR) The Transmit Function Address (TXFUNCADDR) is shown in Figure 98 and described in Table 99. Figure 98. Transmit Function Address (TXFUNCADDR) 7 6 0 Reserved FUNCADDR R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 99. Transmit Function Address (TXFUNCADDR) Field Descriptions Bit Field 7 Value Reserved 6-0 0 FUNCADDR 0-7Fh Description Reserved Address of target function 4.
Registers www.ti.com 4.86 Receive Function Address (RXFUNCADDR) The Receive Function Address (RXFUNCADDR) is shown in Figure 101 and described in Table 102. Figure 101. Receive Function Address (RXFUNCADDR) 7 6 0 Reserved FUNCADDR R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 102. Receive Function Address (RXFUNCADDR) Field Descriptions Bit Field 7 Value Reserved 6-0 0 FUNCADDR 0-7Fh Description Reserved Address of target function 4.
Registers 142 Universal Serial Bus (USB) Controller www.ti.
Appendix A www.ti.com Appendix A Revision History Table A-1 lists the changes made since the previous version of this document. Table A-1. Document Revision History Reference Section 1 Additions/Modifications/Deletions Added note. Section 1.3 Added section. Section 2.4 Changed section. Section 3.1.1 Renamed section. Section 3.1.2.1 Renamed section. Section 3.1.2.2 Renamed section. Section 3.2.1 Renamed section. Section 3.2.2.1 Renamed section. Section 3.2.3 Renamed section. Section 3.2.
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