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4.17 Transmit CPPI Masked Status Register (TCPPIMSKSR) .......................................................... 95
4.18 Transmit CPPI Raw Status Register (TCPPIRAWSR) ............................................................. 95
4.19 Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) ................................................. 96
4.20 Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR) ............................................... 96
4.21 Receive CPPI Control Register (RCPPICR) ......................................................................... 97
4.22 Receive CPPI Masked Status Register (RCPPIMSKSR) .......................................................... 97
4.23 Receive CPPI Raw Status Register (RCPPIRAWSR) .............................................................. 98
4.24 Receive CPPI Interrupt Enable Set Register (RCPPIENSETR) ................................................... 98
4.25 Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR) ............................................... 99
4.26 Receive Buffer Count 0 Register (RBUFCNT0) ..................................................................... 99
4.27 Receive Buffer Count 1 Register (RBUFCNT1) .................................................................... 100
4.28 Receive Buffer Count 2 Register (RBUFCNT2) .................................................................... 100
4.29 Receive Buffer Count 3 Register (RBUFCNT3) .................................................................... 101
4.30 Transmit CPPI DMA State Word 0 (TCPPIDMASTATEW0) ..................................................... 101
4.31 Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1) ..................................................... 102
4.32 Transmit CPPI DMA State Word 2 (TCPPIDMASTATEW2) ..................................................... 102
4.33 Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3) ..................................................... 103
4.34 Transmit CPPI DMA State Word 4 (TCPPIDMASTATEW4) ..................................................... 103
4.35 Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5) ..................................................... 104
4.36 Transmit CPPI Completion Pointer (TCPPICOMPPTR) .......................................................... 104
4.37 Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0) ...................................................... 105
4.38 Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1) ...................................................... 105
4.39 Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2) ...................................................... 107
4.40 Receive CPPI DMA State Word 3 (RCPPIDMASTATEW3) ...................................................... 107
4.41 Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4) ...................................................... 109
4.42 Receive CPPI DMA State Word 5 (RCPPIDMASTATEW5) ...................................................... 109
4.43 Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6) ...................................................... 110
4.44 Receive CPPI Completion Pointer (RCPPICOMPPTR) ........................................................... 110
4.45 Function Address Register (FADDR) ................................................................................ 111
4.46 Power Management Register (POWER) ............................................................................ 111
4.47 Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX) ................................... 112
4.48 Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) ....................................................... 112
4.49 Interrupt Enable Register for INTRTX (INTRTXE) ................................................................. 113
4.50 Interrupt Enable Register for INTRRX (INTRRXE) ................................................................ 113
4.51 Interrupt Register for Common USB Interrupts (INTRUSB) ...................................................... 115
4.52 Interrupt Enable Register for INTRUSB (INTRUSBE) ............................................................. 116
4.53 Frame Number Register (FRAME) .................................................................................. 117
4.54 Index Register for Selecting the Endpoint Status and Control Registers (INDEX) ............................ 117
4.55 Register to Enable the USB 2.0 Test Modes (TESTMODE) ..................................................... 118
4.56 Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) ..................................... 119
4.57 Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) ..................................... 120
4.58 Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) ......................................... 121
4.59 Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) .................................... 122
4.60 Control Status Register for Host Transmit Endpoint (HOST_TXCSR) ......................................... 123
4.61 Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) ..................................... 124
4.62 Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) ..................................... 125
4.63 Control Status Register for Host Receive Endpoint (HOST_RXCSR) ......................................... 126
4.64 Count 0 Register (COUNT0).......................................................................................... 128
4.65 Receive Count Register (RXCOUNT) ............................................................................... 128
4 Contents SPRUGH3 – November 2008
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