User's Manual
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2.1 Introduction
2.2 TMS320C64x+ CPU
Introduction
The C64x+ Megamodule (Figure 2-1 ) consists of the following components:
• TMS320C64x+ CPU
• Internal memory controllers:
– Level-1 program memory controller (L1P controller)
– Level-1 data memory controller (L1D controller)
– Level-2 unified memory controller (L2 controller)
– External memory controller (EMC)
– Internal direct memory access (IDMA) controller
• Internal peripherals
– Interrupt controller (INTC)
– Power-down controller (PDC)
The C64x+ Megamodule includes the C64x+ CPU. The C64x+ CPU is a member of the TMS320C6000™
generation of devices. The C6000™ devices execute up to eight 32-bit instructions per cycle. The CPU
consists of 64 general-purpose 32-bit registers and eight functional units. The eight functional units contain
two multipliers and six ALUs. For more information on the CPU, see the TMS320C64x/C64x+ DSP CPU
and Instruction Set Reference Guide (SPRU732 ).
Features of the C6000 devices include:
• Advanced VLIW CPU with eight functional units, including two multipliers and six arithmetic units
– Executes up to eight instructions per cycle for up to ten times the performance of typical DSPs
– Allows designers to develop highly effective RISC-like code for rapid development time
• Instruction packing
– Gives code-size equivalence for eight instructions that execute serially or in parallel
– Reduces code size, program fetches, and power consumption
• Conditional execution of most instructions
– Reduces costly branching
– Increases parallelism for higher sustained performance
• Efficient code execution on independent functional units
– Industry's most efficient C compiler on DSP benchmark suite
– Industry's first assembly optimizer for rapid development and improved parallelization
• 8/16/32-bit data support, providing efficient memory support for a variety of applications
• 40-bit arithmetic options add extra precision for vocoders and other computationally intensive
applications
• Saturation and normalization provide support for key arithmetic operations
• Field manipulation and instruction extract, set, clear, and bit counting support a common operation
found in control and data manipulation applications
The C64x+ devices include the following additional features:
• Each multiplier can perform two 16 × 16-bit or four 8 × 8-bit multiplies every clock cycle
• Quad 8-bit and dual 16-bit instruction set extensions with data flow support
• Support for nonaligned 32-bit (word) and 64-bit (double word) memory accesses
• Special communication-specific instructions to address common operations in error-correcting codes
• Bit count and rotate hardware extends support for bit-level algorithms
• Compact instructions: common instructions (AND, ADD, LD, MPY) have 16-bit versions to reduce code
size
16 TMS320C64x+ Megamodule SPRU978E – March 2008
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