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3.1 Memory Map
3.1.1 DSP Internal Memory (L1P, L1D, L2)
3.1.2 External Memory
3.1.3 Internal Peripherals
3.1.4 Device Peripherals
Memory Map
Refer to your device-specific data manual for memory-map information.
This section describes the configuration of the DSP internal memory in the DM643x DMP that consists of
L1P, L1D, and L2. In the DM643x DMP:
• L1P memory: The L1P controller allows you to configure part or all of the L1P RAM as normal program
RAM or as direct mapped cache. You can configure cache sizes of 0 KB, 4 KB, 8 KB, 16 KB, or 32 KB
of the RAM.
• L1D memory: The L1D controller allows you to configure part of the L1D RAM as normal data RAM or
as cache. You can configure cache sizes of 0 KB, 4 KB, 8 KB, 16 KB, or 32 KB of the RAM.
• L2 memory: The L2 controller allows you to configure part or all of the L2 RAM as normal RAM or as
cache. You can configure cache sizes of 0 KB, 32 KB, 64 KB, or 128 KB of the RAM.
Refer to device-specific data manual for the exact amount of RAM/cache. Refer to TMS320C64x+ DSP
Megamodule Reference Guide (SPRU871 ) for information on how to configure the cache.
The DSP has access to the following external memories:
• DDR2 synchronous DRAM
• Asynchronous EMIF/NOR/NAND Flash
The external memory controller (EMC) facilitates DSP access to these memories in the C64x+
Megamodule. The following external memories are accessible to the DSP:
• DDR2 port
• Asynchronous EMIF (for example, NOR and NAND Flash in 4 EM_CS regions)
For the memory-map locations of these external memories, refer to the memory-map section of the
device-specific data manual.
The following internal peripherals are accessible to the DSP:
• Power-down controller (PDC)
• Interrupt controller (INTC)
For more information on the internal peripherals, see the TMS320C64x+ DSP Megamodule Reference
Guide (SPRU871 ).
The DSP has access to all peripherals on the device. Refer to device-specific data manual for the full list
of peripherals.
System Memory26 SPRU978E – March 2008
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