User's Manual

www.ti.com
DSP Subsystem
SYSCLK1
SYSCLK3
SCR
EDMA
VPFE
VPBE
DACs
DDR2 PHY
DDR2 VTP
DDR2 Memory
controller
PLLDIV2 (/10)
PLLDIV1 (/2)
BPDIV
PLL Controller 2
PLL Controller 1
PLLDIV2 (/3)
PLLDIV3 (/6)
PLLDIV1 (/1)
SYSCLK2
UARTs (x2)
I2C
Timers (x3)
PWMs (x3)
EMAC
EMIFA
VLYNQ
HPI
McASP0
McBSP0
GPIO
McBSP1
PCI
MXI/CLKIN
(27 MHz)
PCLK
VPBECLK
OSCDIV1 (/1)
HECC
OBSCLK
(CLKOUT0 Pin)
BPDIV (/1)
SYSCLKBP
AUXCLK
Clock Domains
Figure 4-1. Overall Clocking Diagram
SPRU978E – March 2008 Device Clocking 31
Submit Documentation Feedback