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4.2.5 Video Processing Back End
3
2
0
1
0
1
2
PLLDIV2
CLK54
PLL2
DDR_CLKx2
PCLK
VPBECLK
MXI
CLK_VENC
CLK_DAC
1
0
venc_sclk_enc
CG OSD
VENC
DACs
venc_div2
venc_sclk_osd
VPSS
VPSS_CLKCTL.MUXSEL
CLK54 CLK_VENC CLK_DAC
0 27 MHzOff 27 MHz
1h 54 54 MHz 54 MHz
2h Off VPBECLK VPBECLK
3h Off PCLK Off
PLLDIV1
PLLC1
SYSCLKBP
VPSS_CLKCTL.MUXSEL
Clock Domains
The video processing back end (VPBE) is a submodule of the video processing subsystem (VPSS). The
VPBE must interface with a variety of LCDs, as well as the 4-channel DAC module. There are many
different types of LCDs, which require many different specific frequencies. The range of frequencies that
the pin interface needs to run is 6.25 MHZ to 75 MHZ.
There are two asynchronous clock domains in the VPBE: the external clock domain (6.25 MHZ to 75
MHZ) and the internal (system) clock domain, which is at the DSP ÷ 3 clock rate.
The external clock domain can get its clock from 4 sources:
• PLLC1 SYSCLKBP (typically 27 MHZ, MXI/CLKIN divide by 1)
• The VPBECLK input pin
• The VPFE pixel clock input (PCLK)
• PLLC2 SYSCLK2 (a divide down from PLL2)
The 4 DACs are hooked up to the VENC module that is in the VPBE. The data flow between the VPBE
and DACs is synchronous. The various possible clocking modes are shown in Figure 4-2 and described in
Table 4-6 .
The DACs can have their clocks independently gated off when the DACs are not being used. This is
described in Chapter 7 .
Figure 4-2. VPBE/DAC Clocking
SPRU978E – March 2008 Device Clocking 35
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