User's Manual

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Clock Domains
Table 4-6. Possible Clocking Modes
VPSS_CLKCTL.MUXSEL Bit Clocking Mode Description
0 MXI mode Both the VENC and the DAC get their clock from PLLC1 SYSCLKBP, which
defaults to the MXI 27 MHZ crystal input divide by 1.
1h PLL2 mode The PLL2 (divided-down) generates a 54 MHZ clock. Both the DAC and the
VENC receive the 54 MHZ. The VENC can optionally divide it by 2 to create a
27 MHZ clock. Note this mode requires the DDR2 clock setting (from PLL2) to
be an even multiple of 27 MHZ so that an integer divisor can be used to
create the 54 MHZ DAC clock. Thus, this mode limits the available DDR2
clock frequencies.
2h VPBECLK mode Both the DAC and the VENC receive the VPBECLK. The VENC has the
option of dividing it by 2 for progressive scan support driving in 54 MHZ on
VPBECLK.
3h PCLK mode The VENC receives the PCLK. The DAC receives no clock, and should be
disabled. PCLK can be inverted for negative edge support, selectable by a
memory-mapped register bit.
Device Clocking36 SPRU978E – March 2008
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