User's Manual

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5.3.2.2 Initialization to PLL Mode from PLL Power Down
PLL2 Control
If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), you must follow the procedure below
to change PLL2 frequencies.
1. Select the clock mode by programming the CLKMODE bit in PLLCTL.
2. Before changing the PLL frequency, switch to PLL bypass mode:
a. Clear the PLLENSRC bit in PLLCTL to 0 to allow PLLCTL.PLLEN to take effect.
b. Clear the PLLEN bit in PLLCTL to 0 (select PLL bypass mode).
c. Wait for 4 MXI cycles to ensure PLLC switches to bypass mode properly.
3. Clear the PLLRST bit in PLLCTL to 0 (reset PLL)
4. Set the PLLDIS bit in PLLCTL to 1 (disable PLL output).
5. Clear the PLLPWRDN bit in PLLCTL to 0 to bring the PLL out of power-down mode.
6. Clear the PLLDIS bit in PLLCTL to 0 (enable the PLL) to allow PLL outputs to start toggling. Note that
the PLLC is still at PLL bypass mode; therefore, the toggling PLL output does not get propagated to
the rest of the device.
7. Wait for PLL stabilization time. See the device-specific data manual for PLL stabilization time.
8. Program the required multiplier value in PLLM.
9. If necessary, program PLLDIV1 and PLLDIV2 registers to change the SYSCLK1 and SYSCLK2 divide
values:
a. Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in
progress.
b. Program the RATIO field in PLLDIV1 and PLLDIV2 with the desired divide factors. For PLLC2,
there is no specific frequency ratio requirements between SYSCLK1 and SYSCLK2. Make sure in
this step you leave the PLLDIV1.D1EN and PLLDIV2.D2EN bits set (default).
c. Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition. During this transition,
SYSCLK1 and SYSCLK2 are paused momentarily.
d. Wait for N number of PLLDIV n source clock cycles to ensure divider changes have completed. See
Section 5.3.2.4 for the formula on calculating the number of cycles N.
e. Wait for the GOSTAT bit in PLLSTAT to clear to 0.
10. Wait for PLL to reset properly. See the device-specific data manual for PLL reset time.
11. Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset.
12. Wait for PLL to lock. See the device-specific data manual for PLL lock time.
13. Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode.
For information on initializing the DDR2 memory controller, see the TMS320DM643x DMP DDR2 Memory
Controller User's Guide (SPRU986 ).
SPRU978E – March 2008 PLL Controller 45
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