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5.3.2.4 Changing SYSCLK Dividers
PLL2 Control
This section discusses the software sequence to change the SYSCLK dividers. The SYSCLK divider
change sequence is also referred to as GO operation, as it involves hitting the GO bit (GOSET bit in
PLLCMD) to initiate the divider change.
1. Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in
progress.
2. Program the RATIO field in PLLDIV1 and PLLDIV2 with the desired divide factors. For PLLC2, there is
no specific frequency ratio requirements between SYSCLK1 and SYSCLK2. Make sure in this step you
leave the PLLDIV1.D1EN and PLLDIV2.D2EN bits set (default).
3. Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition. During this transition, SYSCLK1
and SYSCLK2 are paused momentarily.
4. Wait for N number of PLLDIV n source clock cycles to ensure divider changes have completed. See the
following formula for calculating the number of cycles N.
5. Wait for the GOSTAT bit in PLLSTAT to clear to 0.
The following formula should be used to calculate the number of PLLDIV n source clock cycles:
N = (2 × Least Common Multiple [LCM] of all the old SYSCLK divide values) + 50 cycles overhead
Example 5-2. Calculating Number of Clock Cycles N
This example calculates the number of clock cycles N.
• Settings before divider change:
– PLLDIV1.RATIO = 1 (divide-by-2)
– PLLDIV2.RATIO = 9 (divide-by-10)
• New divider settings:
– PLLDIV1.RATIO = 1 (divide-by-2)
– PLLDIV2.RATIO = 19 (divide-by-20)
The least common multiple between the old divider values of /2 and /10 is /10; therefore, the number of
cycles N is:
N = (2 × 10) + 50 cycles overhead = 70 PLLDIV n source clock cycles
If PLLC2 is in PLL mode (PLLCTL.PLLEN = 1), the PLLDIV n source clock is the PLL2 output clock. If
PLLC2 is in PLL bypass mode (PLLCTL.PLLEN = 0), the PLLDIV n source clock is the device clock
source MXI/CLKIN.
SPRU978E – March 2008 PLL Controller 47
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