User's Manual

List of Tables
4-1 System Clock Modes and Fixed Ratios for Core Clock Domains.................................................... 30
4-2 Example PLL1 Frequencies and Dividers (27 MHZ Clock Input) .................................................... 32
4-3 Example PLL2 Frequencies (Core Voltage = 1.2V) ................................................................... 33
4-4 Example PLL2 Frequencies (Core Voltage = 1.05V) .................................................................. 33
4-5 Peripheral I/O Domain Clock ............................................................................................. 34
4-6 Possible Clocking Modes.................................................................................................. 36
5-1 System PLLC1 Output Clocks ............................................................................................ 39
5-2 DDR PLLC2 Output Clocks ............................................................................................... 43
5-3 PLL and Reset Controller List ............................................................................................ 48
5-4 PLL and Reset Controller Registers ..................................................................................... 48
5-5 Peripheral ID Register (PID) Field Descriptions ........................................................................ 49
5-6 Reset Type Status Register (RSTYPE) Field Descriptions ........................................................... 49
5-7 PLL Control Register (PLLCTL) Field Descriptions .................................................................... 50
5-8 PLL Multiplier Control Register (PLLM) Field Descriptions ........................................................... 51
5-9 PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions .................................................... 51
5-10 PLL Controller Divider 2 Register (PLLDIV2) Field Descriptions .................................................... 52
5-11 PLL Controller Divider 3 Register (PLLDIV3) Field Descriptions .................................................... 52
5-12 Oscillator Divider 1 Register (OSCDIV1) Field Descriptions ......................................................... 53
5-13 Bypass Divider Register (BPDIV) Field Descriptions .................................................................. 54
5-14 PLL Controller Command Register (PLLCMD) Field Descriptions................................................... 55
5-15 PLL Controller Status Register (PLLSTAT) Field Descriptions ....................................................... 55
5-16 PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions ........................................ 56
5-17 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions ........................................... 57
5-18 Clock Enable Control Register (CKEN) Field Descriptions ........................................................... 58
5-19 Clock Status Register (CKSTAT) Field Descriptions .................................................................. 59
5-20 SYSCLK Status Register (SYSTAT) Field Descriptions .............................................................. 60
6-1 DM643x DMP Default Module Configuration ........................................................................... 63
6-2 Module States .............................................................................................................. 64
6-3 IcePick Emulation Commands ............................................................................................ 66
6-4 PSC Interrupt Events ...................................................................................................... 66
6-5 Power and Sleep Controller (PSC) Registers .......................................................................... 68
6-6 Peripheral Revision and Class Information Register (PID) Field Descriptions ..................................... 69
6-7 Interrupt Evaluation Register (INTEVAL) Field Descriptions ......................................................... 69
6-8 Module Error Pending Register 1 (MERRPR1) Field Descriptions .................................................. 70
6-9 Module Error Clear Register 1 (MERRCR1) Field Descriptions ..................................................... 70
6-10 Power Domain Transition Command Register (PTCMD) Field Descriptions ....................................... 71
6-11 Power Domain Transition Status Register (PTSTAT) Field Descriptions ........................................... 71
6-12 Power Domain Status 0 Register (PDSTAT0) Field Descriptions ................................................... 72
6-13 Power Domain Control 0 Register (PDCTL0) Field Descriptions .................................................... 73
6-14 Module Status n Register (MDSTAT n) Field Descriptions ............................................................ 74
6-15 Module Control n Register (MDCTL n) Field Descriptions ............................................................. 75
7-1 Power Management Features ............................................................................................ 78
9-1 TMS320DM643x DMP Master IDs ....................................................................................... 88
9-2 TMS320DM643x DMP Default Master Priorities ....................................................................... 89
10-1 Reset Types ................................................................................................................. 92
A-1 Document Revision History ............................................................................................... 97
SPRU978E – March 2008 List of Tables 7
Submit Documentation Feedback