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6.7.7 Power Domain Status 0 Register (PDSTAT0)
PSC Registers
The power domain status n register (PDSTAT0) is shown in Figure 6-8 and described in Table 6-12 .
PDSTAT0 applies to the AlwaysOn power domain.
Figure 6-8. Power Domain Status 0 Register (PDSTAT0)
31 16
Reserved
R-0
15 10 9 8 7 5 4 0
Reserved PORDONE POR Reserved STATE
R-0 R-1 R-1 R-0 R-1
LEGEND: R = Read only; - n = value after reset
Table 6-12. Power Domain Status 0 Register (PDSTAT0) Field Descriptions
Bit Field Value Description
31-10 Reserved 0 Reserved
9 PORDONE Power_On_Reset (POR) done status.
0 Power domain POR is not done.
1 Power domain POR is done.
8 POR Power domain Power_On_Reset (POR) status. This bit reflects the POR status for this power domain
including all modules in the domain.
0 Power domain POR is asserted.
1 Power domain POR is de-asserted.
7-5 Reserved 0 Reserved
4-0 STATE Power domain status
0 Power domain is in the off state.
1 Power domain is in the on state.
72 Power and Sleep Controller SPRU978E – March 2008
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