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6.7.8 Power Domain Control 0 Register (PDCTL0)
PSC Registers
The power domain control n register (PDCTL0) is shown in Figure 6-9 and described in Table 6-13 .
PDCTL0 applies to the AlwaysOn power domain.
Figure 6-9. Power Domain Control 0 Register (PDCTL0)
31 16
Reserved
R-0
15 1 0
Reserved NEXT
R-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 6-13. Power Domain Control 0 Register (PDCTL0) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reserved
0 NEXT Power domain next state.
0 Power domain off.
1 Power domain on. AlwaysOn domain must always be programmed to this value.
SPRU978E – March 2008 Power and Sleep Controller 73
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