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6.7.10 Module Control n Register (MDCTLn)
PSC Registers
The module control n register (MDCTL0-MDCTL39) is shown in Figure 6-11 and described in Table 6-15 .
Figure 6-11. Module Control n Register (MDCTL n)
31 16
Reserved
R-0
15 11 10 9 8 7 3 2 0
Reserved EMUIHBIE EMURSTIE LRST Reserved NEXT
R-0 R/W-0 R/W-0 R/W-1 R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 6-15. Module Control n Register (MDCTL n) Field Descriptions
Bit Field Value Description
31-11 Reserved 0 Reserved
10 EMUIHBIE Interrupt enable for emulation alters module state. This bit applies to the DSP module only (module 39).
Program this field to 0 for all other modules.
0 Disable interrupt.
1 Enable interrupt.
9 EMURSTIE Interrupt enable for emulation alters reset. This bit applies to the DSP module only (module 39).
Program this field to 0 for all other modules.
0 Disable interrupt.
1 Enable interrupt.
8 LRST Module local reset control. This bit applies to the DSP module only (module 39). Program this field to 1
for all other modules.
0 Assert local reset.
1 De-assert local reset.
7-3 Reserved 0 Reserved
2-0 NEXT 0-7h Module next state.
0 SwRstDisable state
1h SyncReset state
2h Disable state
3h Enable state
4h-7h Reserved
SPRU978E – March 2008 Power and Sleep Controller 75
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