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7.4.2.2 DSP Module Clock Off

7.5 3.3 V I/O Power Down

7.6 Video DAC Power Down

3.3 V I/O Power Down

In the clock Disable state, the DSP’s module clock is disabled, while DSP reset remains de-asserted. This

state is typically used to disable the DSP clock to save power. As mentioned in Section 7.4.2 , the DSP

cannot put itself in Disable state. An external host is responsible for performing this task. For example, it

can be an external host interfacing through the HPI or PCI peripheral.

• Host: Notify the DSP to prepare for power-down.

• DSP: Drain all existing operations and ensure there are no accesses to the C64x+ megamodule prior

to DSP power-down.

– Program the PSC to disable all master peripherals (except the Host) that are capable of initiating

transfers to the C64x+ Megamodule.

– Check EDMA transfer status to ensure there is no outstanding EDMA transfers that can access the

C64x+ Megamodule.

• DSP: Prepare for power-down.

– Set PDCCMD to 0001 5555h. PDCCMD is a control register in the DSP power-down controller

module.

Note: This register can only be written while the DSP is in supervisor mode.

– Enable one of the interrupts that the host would like to use to wake the DSP in the DSP clock-on

sequence.

– Execute the IDLE instruction. IDLE is a program instruction in the C64x+ CPU instruction set. When

the CPU executes IDLE, the PDC is notified and initiates DSP power-down according to the bits

that you set in the PDCCMD (0181 0000h) register. See the TMS320C64x+ DSP Megamodule

Reference Guide (SPRU871 ) for more information on the PDC and the IDLE instruction.

• Host: Disable the DSP clock.

– Wait for the GOSTAT[0] bit in PTSTAT to clear to 0. You must wait for the power domain to finish

any previously initiated transitions before initiating a new transition.

– Set the NEXT bit in MDCTL39 to 2h to prepare the DSP module for a disable transition.

– Set the GO[0] bit in PTCMD to 1 to initiate the state transition.

– Wait for the GOSTAT[0] bit in PTSTAT to clear to 0. The domain is only safely in the new state

after the GOSTAT[0] bit is cleared to 0.

– Wait for the STATE bit in MDSTAT39 to change to 2h. The module is only safely in the new state

after the STATE bit in MDSTAT39 changes to reflect the new state.

The 3.3 V I/O drivers are fabricated out of 1.8 V transistors with design techniques that require a DC bias

current. These I/O cells have a power-down mode that turns off the DC current. The VDD3P3V_PWDN

more details on the VDD3P3V_PWDN register.

The DM643x DMP video processing back end (VPBE) includes four video digital-to-analog converters

(DACs) to drive analog television displays. The Video Encoder (VENC) module of the VPBE includes

registers for enabling/disabling the DACs. You can use the VIE bit in VMOD to force the analog output of

the 4 DACs to a low level, regardless of the video signal. Furthermore, you can use the DAPD[3:0] bits in

DACTST to disable each DAC independently. See the TMS320DM643x DMP Video Processing Back End

(VPBE) User's Guide (SPRU952 ) for register descriptions and more detailed information on DAC

power-down.

SPRU978E – March 2008 Power Management 81

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