TMS320TCI648x Serial RapidIO (SRIO) User's Guide Literature Number: SPRUE13A September 2006
SPRUE13A – September 2006 Submit Documentation Feedback
Contents Preface.............................................................................................................................. 14 1 Overview .................................................................................................................. 16 2 1.1 General RapidIO System ...................................................................................... 16 1.2 RapidIO Feature Support in SRIO............................................................................
5.23 LSU Interrupt Condition Clear Register (LSU_ICCR) .................................................... 141 5.24 Error, Reset, and Special Event Interrupt Condition Status Register (ERR_RST_EVNT_ICSR).................................................................................... 142 5.25 Error, Reset, and Special Event Interrupt Condition Clear Register (ERR_RST_EVNT_ICCR) ................................................................................... 143 5.
.69 Port Link Maintenance Request CSR n (SPn_LM_REQ) ................................................ 200 5.70 Port Link Maintenance Response CSR n (SPn_LM_RESP) ............................................ 201 5.71 Port Local AckID Status CSR n (SPn_ACKID_STAT) ................................................... 202 5.72 Port Error and Status CSR n (SPn_ERR_STAT) ......................................................... 203 5.73 Port Control CSR n (SPn_CTL) .......................................
List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 6 RapidIO Architectural Hierarchy .......................................................................................... RapidIO Interconnect Architecture ....................................................................................... Serial RapidIO Device to Device Interface Diagrams ...........................................................
50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 RX CPPI Interrupt Condition Status and Clear Registers ............................................................. 89 TX CPPI Interrupt Condition Status and Clear Registers ............................................................. 89 LSU Interrupt Condition Status and Clear Registers ..............................................................
102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 8 LSUn FLOW_MASK Fields .............................................................................................. Queue n Transmit DMA Head Descriptor Pointer Register (QUEUEn_TXDMA_HDP) ......................... Queue n Transmit DMA Completion Pointer Register (QUEUEn_TXDMA_CP) .............
155 156 157 158 159 160 161 162 Port IP Mode CSR (SP_IP_MODE) - Address Offset 12004h ...................................................... Port IP Prescaler Register (IP_PRESCAL) - Address Offset 12008h ............................................. Port-Write-In Capture CSRs ............................................................................................. Port Reset Option CSR n (SPn_RST_OPT) ..........................................................................
List of Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 10 TI Devices Supported By This Document ............................................................................... 20 Registers Checked for Multicast DeviceID .............................................................................. 21 Packet Types .................................................................................................
50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 RapidIO DEVICEID1 Register (DEVICEID_REG1) Field Descriptions ............................................ RapidIO DEVICEID2 Register (DEVICEID_REG2) Field Descriptions ............................................ PF_16B_CNTL Registers ................................................................................................
99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 12 LSUn_REG6 Registers and the Associated LSUs ................................................................... LSUn Control Register 6 (LSUn_REG6) Field Descriptions ........................................................ LSUn_FLOW_MASKS Registers and the Associated LSUs ...............................
150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 Error Reporting Block Header Register (ERR_RPT_BH) Field Descriptions ..................................... Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions ...................................... Logical/Transport Layer Error Enable CSR (ERR_EN) Field Descriptions .......................................
Preface SPRUE13A – September 2006 Read This First About This Manual This document describes the Serial RapidIO® (SRIO) peripheral on the TMS320TCI648x™ devices. Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number represents 40 hexadecimal (decimal 64): 40h. • Registers in this document are shown in figures and described in tables.
www.ti.com Related Documentation From Texas Instruments Trademarks TMS320TCI648x, C6000, TMS320C62x, TMS320C67x, TMS320C6000, Code Composer Studio are trademarks of Texas Instruments. RapidIO is a registered trademark of RapidIO Trade Association. InfiniBand is a trademark of the InfiniBand Trade Association.
User's Guide SPRUE13A – September 2006 Serial RapidIO (SRIO) 1 Overview The RapidIO peripheral used in the TMS320TCI648x is called a serial RapidIO (SRIO). This chapter describes the general operation of a RapidIO system, how this module is connected to the outside world, the definitions of terms used within this document, and the features supported and not supported for SRIO. 1.1 General RapidIO System RapidIO®is a non-proprietary high-bandwidth system level interconnect.
www.ti.com Overview Figure 1. RapidIO Architectural Hierarchy Logical specification Information necessary for the end point to process the transaction (i.e., transaction type, size, physical address) I/O system Transport specification Information to transport packet from end to end in the system (i.e., routing address) Physical specification Information necessary to move packet between two physical devices (i.e.
www.ti.com Overview 1.1.2 RapidIO Interconnect Architecture The interconnect architecture is defined as a packet switched protocol independent of a physical layer implementation. Figure 2 illustrates the interconnection system. Figure 2.
www.ti.com Overview Figure 3. Serial RapidIO Device to Device Interface Diagrams 1x Device 1x Device TD[0] RD[0] TD[0] RD[0] RD[0] TD[0] RD[0] TD[0] Serial RapidIO 1x Device to 1x Device Interface Diagram 4x Device 4x Device TD[0-3] RD[0-3] TD[0-3] RD[0-3] RD[0-3] TD[0-3] RD[0-3] TD[0-3] Serial RapidIO 4x Device to 4x Device Interface Diagram 1.2 RapidIO Feature Support in SRIO Features Supported in SRIO Peripheral: • RapidIO Interconnect Specification V1.2 compliance, Errata 1.
www.ti.com Overview Features Not Supported: • Compliance with the Global Shared Memory specification (GSM) • 8/16 LP-LVDS compatible • Destination support of RapidIO Atomic Operations • Simultaneous mixing of frequencies between 1x ports (all ports must be the same frequency) • Target atomic operations (including increment, decrement, test-and-swap, set, and clear) for internal L2 memory and registers 1.3 Standards The SRIO peripheral is compliant to V1.
www.ti.com SRIO Functional Description 2 SRIO Functional Description 2.1 Overview 2.1.1 Peripheral Data Flow This peripheral is designed to be an externally driven slave module that is capable of acting as a master in the DSP system. This means that an external device can push (burst write) data to the DSP as needed, without having to generate an interrupt to the CPU or without relying on the DSP EDMA. This has several benefits.
www.ti.
www.ti.com SRIO Functional Description SRIO endpoints are typically not connected directly to each other but instead have intervening connection fabric devices. Control symbols are used to manage the flow of transactions in the SRIO physical interconnect. Control symbols are used for packet acknowledgment, flow control information, and maintenance functions. Figure 5 shows how a packet progresses through the system. Figure 5.
www.ti.com SRIO Functional Description Figure 6. 1x/4x RapidIO Packet Data Stream (Streaming-Write Class) n*64+80 PHY 10 acklD rsv 5 prio 3 2 tt ftype destID 2 4 8 sourcelD 4 address rsrv xamsbs 8 1 29 LOG TRA 2 LOG TRA 16 ...
www.ti.com SRIO Functional Description The type of received packet determines how the packet routing is handled. Reserved or undefined packet types are destroyed before being processed by the logical layer functional blocks. This prevents erroneous allocation of resources to them. Unsupported packet types are responded to with an error response packet. Section 2.1.2.4 details the handling of such packets. 2.1.2.
www.ti.com SRIO Functional Description Table 4. Pin Description Pin Count Signal Direction RIOTX3/ RIOTX3 2 Output Transmit Data – Differential point-to-point unidirectional bus. Transmits packet data to a receiving device’s RX pins. Most significant bits in 1 port 4X device. Used in 4 port 1X device. RIOTX2/ RIOTX2 2 Output Transmit Data – Differential point-to-point unidirectional bus. Transmits packet data to a receiving device’s RX pins. Bit used in 4 port 1x device and 1 port 4X device.
www.ti.com SRIO Functional Description Figure 8. SRIO Component Block Diagram DMA bus Load/Store units (LSUs) TX direct I/O TXU Messaging Maintenance 4.5 KB TX shared buffer Memory access unit (MAU) RX direct I/O RXU Messaging 4.
www.ti.com SRIO Functional Description 2.3.2 SERDES Macro and its Configurations SRIO offers many benefits to customers by allowing a scalable non-proprietary interface. With the use of TI’s SERDES macros, the peripheral is very adaptable and bandwidth scalable. The same peripheral can be used for all three frequency nodes specified in V1.2 of the RapidIO Interconnect Specification (1.25, 2.5, and 3.125 Gbps).
www.ti.com SRIO Functional Description Table 5. SERDES Macro Configuration Register 0 (SERDES_CFG0_CNTL) Field Descriptions Bit 31–10 9–8 Field Value Description Reserved 0000h Reserved LB 7–6 Reserved 5–1 MPY 0 Loop bandwidth. Specify loop bandwidth settings. Jitter on the reference clock will degrade both the transmit eye and receiver jitter tolerance thereby impairing system performance.
www.ti.com SRIO Functional Description Table 6. Line Rate versus PLL Output Clock Frequency Rate Line Rate PLL Output Frequency RATESCALE Full x Gbps 0.5x GHz 0.5 Half x Gbps x GHz 1 Quarter x Gbps 2x GHz 2 RIOCLK and RIOCLKFREQ = LINERATE × RATESCALE MPY The rate is defined by the RATE bits of the SERDES_CFGRXn_CNTL register and the SERDES_CFGTXn_CNTL register, respectively.
www.ti.com SRIO Functional Description The clock recovery algorithms listed in the CDR bits operate to adjust the clocks used to sample the received message so that the data samples are taken midway between data transitions. The second order algorithm can be optionally disabled, and both can be configured to optimize their dynamics. Both algorithms use the same basic technique for determining whether the sampling clock is ideally placed, and if not whether it needs to be moved earlier or later.
www.ti.com SRIO Functional Description Table 9. SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) Field Descriptions (continued) Bit Reserved 23 Reserved 22–19 EQ 18–16 CDR 15–14 13–12 11 10–8 7 6–5 32 Field 25–24 Value Always write 0s to these reserved bits. 0 This read-only bit returns 0 when read. 0000b–1111b 000b First order. Phase offset tracking up to ±488 ppm. 001b Second order.
www.ti.com SRIO Functional Description Table 9. SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) Field Descriptions (continued) Bit Field Value Description 4–2 BUSWIDTH 000b Bus width. Always write 000b to this field, to indicate a 10-bit-wide parallel bus to the clock. All other values are reserved. See Section 2.3.2.1 for an explanation of the bus. 1 Reserved 0 ENRX 0 Always write 0 to this reserved bit. Enable receiver 0 Disable this receiver.
www.ti.com SRIO Functional Description Table 11. SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL) Field Descriptions (continued) Bit Field 15–12 DE 11–9 SWING 8 7 6–5 4–2 Value 0000b–1111b 000b–111b CM Reserved 0 ENTX Output swing. Selects one of 8 outputs amplitude settings between 125 and 1250mVdfpp. See Table 13. 0 Normal common mode. Common mode not adjusted. 1 Raised common mode. Common mode raised by 5% of difference between RIOTXn and RIOTXn Invert polarity.
www.ti.com SRIO Functional Description Table 13. SWING Bits of SERDES_CFGTXn_CNTL 2.3.2.4 SWING Bits Amplitude (mVdfpp) 000b 125 001b 250 010b 500 011b 625 100b 750 101b 1000 110b 1125 111b 1250 SERDES Configuration Example //full sample rate at 3.125 Gbps //SERDES reference clock (RIOCLK) 125 MHz //MPY = 12.5 125MHz = ((3.125 Gbps)(.
www.ti.com SRIO Functional Description Figure 12.
www.ti.com SRIO Functional Description Table 14. LSU Control/Command Register Fields (continued) LSU Register Field RapidIO Packet Header Field DestID RapidIO destinationID field specifying the target device. Packet Type 4 MSBs: 4-bit ftype field for all packets 4 LSBs: 4-bit trans field for packet types 2, 5, and 8 OutPortID Not available in RapidIO header. Indicates the output port number for the packet to be transmitted from. Specified by the CPU along with NodeID.
www.ti.com SRIO Functional Description Figure 13. LSU Registers Timing T0 T1 T3 T2 LSUn_REG1 T4 After Transaction Completes Tn T5 Valid LSUn_REG2 Valid LSUn_REG3 Valid LSUn_REG4 Valid LSUn_REG5 Valid Rdy/BSY Completion Valid Valid The following code illustrates an LSU registers programming example.
www.ti.com SRIO Functional Description Figure 14.
www.ti.com SRIO Functional Description Figure 15. Load/Store Module Data Flow Diagram UDI RapidIO transport and physical layers Peripheral boundary Load/Store module Write transfer descriptors Port x transmission FIFO queues Control and arbitrator TX FIFO I/O pins RX FIFO Response timer LSU4 LSU3 LSU2 LSU1 MMR command Shared TX buffer Config bus access CPU DMA request Shared RX buffer L2 memory DMA response = Shared resource for CPPI and MAU 2.3.3.
www.ti.com SRIO Functional Description Data leaves the shared TX buffer sequentially in order of receipt, not based on the packet priority. However, if fabric congestion occurs, priority can affect the order in which the data leaves the TX FIFOs. A reordering mechanism exists here, which transmits the highest priority packets first if RETRY acknowledges. For posted WRITE operations, which do not require a RapidIO response packet, a core may submit multiple outstanding requests.
www.ti.com SRIO Functional Description Segmentation: The LSU handles two types of segmentation of outbound requests. The first type is when the Byte_Count of Read/Write requests exceeds 256 bytes (up to 4K bytes). The second type is when Read/Write request RapidIO address is non-64-bit aligned. In both cases, the outgoing request is broken up into multiple RapidIO request packets. For example, assume that the CPU wants to perform a 1K-byte store operation to an external RapidIO device.
www.ti.
www.ti.com SRIO Functional Description • • • • • • • 2.3.4.1 Out-of-order responses are allowed. A RETRY response is issued to the first received segment of a multi-segment message when the RX queue is busy servicing another request. – Subsequent RETRY responses may have to be sent for received pipeline segments or additional pipelined messages to the same queue. In-order message reception for dedicated flows is mode programmable.
www.ti.com SRIO Functional Description Figure 17. Message Request Packet n*64+64 PHY 10 acklD rsv 5 3 ftype = 1011 prio tt 2 2 ftype destID sourcelD msglen 4 8 8 4 ssize 4 TRA 2 TRA 16 LOG 4 letter mbox msgseg/xmbox double-word 0 double-word 1 2 2 4 PHY 16 LOG n*64+16 64 64 ...
www.ti.com SRIO Functional Description Figure 18.
www.ti.com SRIO Functional Description If a RX message’s length is greater than that of the targeted buffer descriptor, an ERROR response is sent back to the source device. In addition, the DSP is notified with the use of the CC field of the RX CPPI buffer descriptor, described as follows. This situation can result from a DSP software error (misallocating a buffer for the queue), or as a result of sender error (sending to a wrong mailbox).
www.ti.com SRIO Functional Description Table 18. RX Buffer Descriptor Field Descriptions (continued) Field Description ownership Ownership: Indicates ownership of the message and is valid only on sop. This bit is set by the DSP core and cleared by the port when the message has been transmitted. The DSP core uses this bit to reclaim buffers.
www.ti.com SRIO Functional Description Although the switch fabric delivers the segments of multi-packet messages in the order they were sent, buffer resources at the receiving endpoint may only become available after the initial segment(s) of a message have had to be retried. The peripheral can accept out-of-order segments and track completion of the overall message. Scenario A in Figure 20 shows this concept.
www.ti.com SRIO Functional Description In addition, multiple messages can be interleaved at the receive port due to ordering within a connected switch’s output queue. This can occur when using a single or multiple priorities. The RX CPPI block can handle simultaneous interleaved multi-segment messages. This implies that state information (write pointers and sourceID) is maintained on each simultaneous message to properly store the segments in memory.
www.ti.com SRIO Functional Description Figure 21. CPPI Boundary Diagram Peripheral boundary CPPI block Config bus access CPPI control registers Data buffer 32 CPU 32 DMA Buffer descriptor dual-port SRAM (Nx20B) 32 128 L2 memory 2.3.4.2 TX Operation Outgoing messages are handled similarly, with buffer descriptor queues that are assigned by the CPUs. The queues are configured and initialized upon reset.
www.ti.com SRIO Functional Description Table 20. TX DMA State Completion Pointer (CP) (Address Offset 58h–5BCh) Bit Name Description 31–0 TX Queue Completion Pointer TX Queue Completion Pointer: This field is the DSP core memory address for the transmit queue completion pointer. This register is written by the DSP core with the buffer descriptor address for the last buffer processed by the DSP core during interrupt processing.
www.ti.com SRIO Functional Description Table 21. TX Buffer Descriptor Field Definitions (continued) Field Description retry_count Message Retry Count: Set by the DSP core to indicate the total number of retries allowed for this message, including all segments. Decremented by the port each time a message is retried. 000000b: Infinite Retries 000001b: Retry Message 1 time 000002b: Retry Message 2 times ... 111111b: Retry Message 63 times cc Completion Code: Set by the port. 000: Good Completion.
www.ti.com SRIO Functional Description Table 21. TX Buffer Descriptor Field Definitions (continued) Field Description ssize RIO standard message payload size. Indicates how the hardware should segment the outgoing message by specifying the maximum number of double-words per packet. If the message is a multi-segment message, this field remains the same for all outgoing segments. All segments of the message, except for the last segment, have payloads equal to this size.
www.ti.com SRIO Functional Description TX_Queue_Map has been programmed to send two messages from Queue 0 before moving to Queue 1, it will re-attempt to send the same message from Queue 0 before moving on. Whether it is successful or not, the next attempt will come from Queue 1. Within a given queue, the hardware will always try to send the head buffer descriptor and can not move to the next buffer descriptor in the queue until a completion code is written.
www.ti.com SRIO Functional Description Figure 23.
www.ti.com SRIO Functional Description Table 22. Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh) (continued) Field Pair TX_Queue_Map2 TX_Queue_Map3 Register[Bits] Pointer to a queue. This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues. TX_QUEUE_CNTL0[23–20] Number of Msgs 0h to Fh Number of contiguous messages (descriptors) to process before moving to TX_Queue_Map3. TX_QUEUE_CNTL0[27–24] Queue Pointer 0h to Fh Pointer to a queue.
www.ti.com SRIO Functional Description Table 22. Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh) (continued) Field Pair TX_Queue_Map11 TX_Queue_Map12 TX_Queue_Map13 TX_Queue_Map14 TX_Queue_Map15 Register[Bits] Field Value Description TX_QUEUE_CNTL2[27–24] Queue Pointer 0h to Fh Pointer to a queue. This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues.
www.ti.com SRIO Functional Description A transaction timeout is used by all outgoing message and direct I/O packets. It has the same value and is analogous to the request-to-response timer discussed in the RX CPPI and LSU sections, which is defined by the 24-bit value in the port response time-out CSR (See Section 2.3.3.3 ). The RapidIO Interconnect Specification states that the maximum time interval (all 1s) is between 3 and 6 seconds.
www.ti.com SRIO Functional Description 2.3.4.
www.ti.
www.ti.com SRIO Functional Description Figure 24.
www.ti.com SRIO Functional Description Figure 25. TX Buffer Descriptors Descriptor Buffer Descriptor Buffer TX queue head descriptor pointer Port TX DMA state Start Message Passing 2.3.5 SRIO_REGS->Queue0_RXDMA_HDP = (int )RX_DESCP0_0 ; SRIO_REGS->Queue0_TXDMA_HDP = (int )TX_DESCP0_0 ; Maintenance The type 8 MAINTENANCE packet format accesses the RapidIO capability registers (CARs), command and status registers (CSRs), and data structures.
www.ti.com SRIO Functional Description for any desired purpose; see the RapidIO Interconnect Specification, Section 3.1.4, Type 10 Packet Formats (Doorbell Class), for information about the info field. A processing element that receives a doorbell transaction takes the packet and puts it in a doorbell message queue within the processing element. This queue may be implemented in hardware or in local memory. This behavior is similar to that of typical message passing mailbox hardware.
www.ti.com SRIO Functional Description SRIO_REGS->LSU1_REG0 SRIO_REGS->LSU1_REG1 SRIO_REGS->LSU1_REG2 SRIO_REGS->LSU1_REG3 SRIO_REGS->LSU1_REG4 = = = = = SRIO_REGS->LSU1_REG5 = 2.3.
www.ti.com SRIO Functional Description Since CCPs do not have guaranteed delivery and can be dropped by the fabric, an implicit method of enabling an Xoff’d flow must exist. A simple timeout method is used. Additionally, flow control checks can be enabled or disabled through the Transmit Source Flow Control Masks. Received CCPs are not passed through the DMA bus interface. 2.3.8.1 Detailed Description To avoid large and complex table management, a basic scheme is implemented for congestion management.
www.ti.com SRIO Functional Description Table 24. Flow Control Table Entry Register n (FLOW_CNTLn) Field Descriptions Bit Field 31–18 Reserved 17–16 TT 15–0 Value Description 0 These read-only bits return 0s when read. Transfer type for flow n FLOW_CNTL_ID 00b 8-bit destination IDs 01b 16-bit destination IDs 1xb Reserved 0000h–FFFFh Destination ID for flow n. When 8-bit destination IDs are used (TT = 00b), the 8 MSBs of this field are don't care bits.
www.ti.com SRIO Functional Description Table 25.
www.ti.com SRIO Functional Description 2.3.9.1 Translation for MMR space There are no Endian translation requirements for accessing the local MMR space. Regardless of the device memory Endian configuration, all configuration bus accesses are performed on 32-bit values at a fixed address position. The bit positions in the 32-bit word are defined by this specification. This means that a memory image which will be copied to a MMR is identical between Little Endian and Big Endian configurations.
www.ti.com SRIO Functional Description 2.3.10 Reset and Power Down The RapidIO peripheral allows independent software controlled shutdown for the logical blocks listed in Table 26. With the exception of BLK0_EN for the memory-mapped registers (MMRs), when the BLKn_EN signals are deasserted, the clocks are gated to these blocks, effectively providing a shutdown function. Table 26.
www.ti.com SRIO Functional Description 2.3.10.1 Reset and Power Down Summary After reset, the state of the peripheral depends on the default register values. Software can also perform a hard reset of each logical block within the peripheral via the GBL_EN and BLKn_EN bits. The GBL_EN bit resets the peripheral, while the rest of the device is not reset.
www.ti.com SRIO Functional Description Table 27. Global Enable and Global Enable Status Field Descriptions Register (Bit) Field GBL_EN(31–1) Reserved GBL_EN(0) GBL_EN_STAT(31–10) GBL_EN_STAT(9) GBL_EN_STAT(8) GBL_EN_STAT(7) GBL_EN_STAT(6) GBL_EN_STAT(5) GBL_EN_STAT(4) GBL_EN_STAT(3) GBL_EN_STAT(2) GBL_EN_STAT(1) GBL_EN_STAT(0) Value Description 0 These read-only bits return 0s when read. EN Global enable. This bit controls reset to all clock domains within the peripheral.
www.ti.com SRIO Functional Description Figure 35. BLK0_EN_STAT (Address 003Ch) 31 1 0 Reserved EN_STAT R-0 R-1 LEGEND: R = Read, W = Write, -n = Value after reset Figure 36. BLK1_EN (Address 0040h) 31 1 0 Reserved EN R-0 R/W-1 LEGEND: R = Read, W = Write, -n = Value after reset Figure 37. BLK1_EN_STAT (Address 0044h) 31 1 0 Reserved EN_STAT R-0 R-1 LEGEND: R = Read, W = Write, -n = Value after reset • • • Figure 38.
www.ti.com SRIO Functional Description 2.3.10.3 Software Shutdown Details Power consumption is minimized for all logical blocks that are in shutdown. In addition to simply asserting the appropriate reset signal to each logical block within the peripheral, clocks are gated off to the corresponding logical block as well. Clocks are allowed to run for 32 clock cycles, which is necessary to fully reset each logical block.
www.ti.com SRIO Functional Description Table 29. Peripheral Control Register (PCR) Field Descriptions (continued) Bit Field 1 SOFT 0 Value Description Soft stop. This bit and the FREE bit determine how the SRIO peripheral behaves during emulation halts. 0 Hard stop. All status registers are frozen in default state. (This mode is not supported on the SRIO peripheral.) 1 Soft stop FREE Free run 0 The SOFT bit takes effect. 1 Free run.
www.ti.com SRIO Functional Description The physical layer buffers act like a FIFO unless there is a retry of a packet from the connected device, in which case a re-ordering algorithm is used. The algorithm searches backward through the buffer group for the first packet with the highest priority. If there are no higher priority packets in the queue, the current packet is sent again.
www.ti.com SRIO Functional Description For multi-segment messages, if the transfer is unsuccessful after 256 times of credit request for the first segment, the TXU moves to the next queue in the round-robin loop. The TXU tries to send the unsent message again the next time around the loop. After the first segment is granted outbound credit and is sent to the physical layer for transmission, all subsequent segments are given 64K attempts to gain outbound credit.
www.ti.com SRIO Functional Description SRIO_REGS->SERDES_CFG0_CNTL = 0x00000013; SRIO_REGS->SERDES_CFG1_CNTL = 0x00000000; SRIO_REGS->SERDES_CFG2_CNTL = 0x00000000; SRIO_REGS->SERDES_CFG3_CNTL = 0x00000000; SRIO_REGS->SERDES_CFGRX0_CNTL SRIO_REGS->SERDES_CFGRX1_CNTL SRIO_REGS->SERDES_CFGRX2_CNTL SRIO_REGS->SERDES_CFGRX3_CNTL SRIO_REGS->SERDES_CFGTX0_CNTL SRIO_REGS->SERDES_CFGTX1_CNTL SRIO_REGS->SERDES_CFGTX2_CNTL SRIO_REGS->SERDES_CFGTX3_CNTL 2.3.13.
www.ti.
www.ti.com SRIO Functional Description 4. 5. 6. 7. 8. DSP executes idle instruction. RapidIO ports send Idle control symbols to train PHYs. Host enabled to explore system with RapidIO Maintenance packets. Host identifies, enumerates and initializes the RapidIO device. Host controller configures DSP peripherals through maintenance packets. • SRIO Device IDs are set for DSPs (either by pin strapping or by host manipulation) 9. Boot Code sent from host controller to DSP L2 memory base address via NWRITE.
www.ti.com SRIO Functional Description Table 31. Multicast DeviceID Operation 2.3.15.2 Device Local DeviceID Register Offset Multicast DeviceID Register Offset TMS320TCI6482 0080h 0084h Endpoint Device Requirements Accepts discrete multiple DestIDs from incoming packet Daisy Chain Operation and Packet Forwarding Some applications may require daisy chaining of devices together versus using a switch fabric. Typically, these applications are low cost implementations.
www.ti.com SRIO Functional Description Figure 43. Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTLn) Offsets 0x0094, 0x009C, 0x00A4, 0x00AC 31 18 17 16 Reserved OUT_BOUND_ PORT R-0 R/W-3 15 8 8BIT_DEVID_UP_BOUND R/W-FFh 7 0 8BIT_DEVID_LOW_BOUND R/W-FFh LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset Table 33.
www.ti.com Logical/Transport Error Handling and Logging 3 Logical/Transport Error Handling and Logging Error management registers allow detection and logging of logical/transport layer errors. The detectable errors are captured in the logical layer error detect CSR (see Figure 44). Table 34 names the functional block(s) involved for each detectable error condition, and includes brief descriptions of the errors captured. Figure 44.
www.ti.com Logical/Transport Error Handling and Logging Table 34. Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions (continued) Bit Field 25 MSG_REQ_TIMEOUT 24 23 22 21–8 7 6 5–0 84 Value Message request timeout (endpoint device only) 0 A timeout has not been detected by RXU. 1 A timeout has been detected by the RXU. A required message request has not been received by the RXU within the specified time-out interval. To clear this bit, write 0 to it.
www.ti.com Interrupt Conditions 4 Interrupt Conditions This section defines the CPU interrupt capabilities and requirements of the peripheral. 4.1 CPU Interrupts The following interrupts are supported by the RIO peripheral. • Error status: Event indicating that a run-time error was reached. The CPU should reset/resynchronize the peripheral. • Critical error: Event indicating that a critical error state was reached. The CPU should reset the system.
www.ti.com Interrupt Conditions The DOORBELL packet’s 16-bit INFO field indicates which DOORBELL register interrupt bit to set. There are four DOORBELL registers, each currently with 16 bits, allowing 64 interrupt sources or circular buffers (see Table 23 for assignment of the 16 bits of DOORBELL_INFO field). Each bit can be assigned to any core as described by the Interrupt Condition Routing Registers. Additionally, each status bit is user-defined for the application.
www.ti.com Interrupt Conditions Table 35. Interrupt Condition Status and Clear Bits Field Access Reset Value Value ICSx R 0 0 Condition not present 1 Condition present 0 No effect 1 Clear the condition status bit (ICSx) ICCx 4.3.1 W 0 Function Doorbell Interrupt Condition Status and Clear Registers The interrupt condition status registers (ICSRs) and the interrupt condition clear registers (ICCRs) for the four doorbells are shown in Figure 46 through Figure 49.
www.ti.com Interrupt Conditions Figure 48.
www.ti.com Interrupt Conditions For transmission, the clearing of any ICSR bit is dependent on the CPU writing to the CP register for the queue (QUEUEn_TXDMA_CP). The CPU acknowledges the interrupt after reclaiming all available buffer descriptors by writing the CP value. This value is compared against the port written value in the CP register. If the values are equal, the interrupt is deasserted. Figure 50.
www.ti.com Interrupt Conditions Figure 52.
www.ti.com Interrupt Conditions Table 36. Interrupt Conditions Shown in LSU_ICSR and Cleared With LSU_ICCR (continued) 4.3.
www.ti.com Interrupt Conditions The interrupt status bits found in the ERR_RST_EVNT (0x0270) can be cleared by writing to the ICCR register (0x0278) in the same manner as other interrupts. However, in order for new event detection and interrupt generation to occur for these special interrupts, additional register bits must be cleared. The following table notes the additional interrupt source register bits that need to be cleared and the appropriated sequence.
www.ti.com Interrupt Conditions Table 38.
www.ti.com Interrupt Conditions When doorbell packets are received by the SRIO peripheral, these ICRRs route doorbell interrupt requests to interrupt destinations. For example, if ICS6 = 1 in DOORBELL2_ICSR and ICR6 = 0010b in DOORBELL2_ICRR, the interrupt request from Doorbell 2, bit 6 is sent to interrupt destination 2. Figure 54.
www.ti.com Interrupt Conditions Figure 56.
www.ti.com Interrupt Conditions Figure 57.
www.ti.com Interrupt Conditions Figure 58.
www.ti.com Interrupt Conditions each bit in the ISDR. Bits within the LSU interrupt condition status register (ICSR) are logically grouped for a given core and ORed together into a single bit (bit 31) of the decode register. Similarly, the bits within the Error, Reset, and Special Event ICSR are ORed together into bit 30 of the decode register. The TX CPPI and RX CPPI interrupt sources (one for each buffer descriptor queue) can be mapped to bits 31–16 as shown in Figure 60.
www.ti.com Interrupt Conditions Figure 61. Example Diagram of Interrupt Status Decode Register Mapping The following are suggestions for minimizing the number of register reads to identifying the interrupt source: • Dedicate each doorbell ICSR to one core. The CPU can then determine the interrupt source from a single read of the decode register. • Assign the RX and TX CPPI queues orthogonally to different cores. The CPU can then determine the interrupt source from a single read of the decode registers.
www.ti.com Interrupt Conditions immediately starts down-counting each time the CPU writes these registers. When the rate control counter register is written, and the counter value reaches zero (note that the CPU may write zero immediately for a zero count), the interrupt pulse generation logic is allowed to fire a single pulse if any bits in the corresponding ICSR register bits are set (or become set after the zero count is reached). The counter remains at zero.
www.ti.
www.ti.com SRIO Registers 5 SRIO Registers 5.1 Introduction Table 40 lists the names and address offsets of the memory-mapped registers for the Serial RapidIO (SRIO) peripheral. See the device-specific data manual for the exact memory addresses of these registers. Table 40. Serial RapidIO (SRIO) Registers 102 Offset Acronym Register Description 0000h PID Peripheral Identification Register Section 5.2 Section 0004h PCR Peripheral Control Register Section 5.
www.ti.com SRIO Registers Table 40. Serial RapidIO (SRIO) Registers (continued) Offset Acronym Register Description 011Ch SERDES_CFGTX3_CNTL SERDES Transmit Channel Configuration Register 3 Section 5.14 0120h SERDES_CFG0_CNTL SERDES Macro Configuration Register 0 Section 5.15 0124h SERDES_CFG1_CNTL SERDES Macro Configuration Register 1 Section 5.15 0128h SERDES_CFG2_CNTL SERDES Macro Configuration Register 2 Section 5.
www.ti.com SRIO Registers Table 40. Serial RapidIO (SRIO) Registers (continued) 104 Offset Acronym Register Description 030Ch INTDST3_DECODE INTDST Interrupt Status Decode Register 3 Section 5.31 Section 0310h INTDST4_DECODE INTDST Interrupt Status Decode Register 4 Section 5.31 0314h INTDST5_DECODE INTDST Interrupt Status Decode Register 5 Section 5.31 0318h INTDST6_DECODE INTDST Interrupt Status Decode Register 6 Section 5.
www.ti.com SRIO Registers Table 40. Serial RapidIO (SRIO) Registers (continued) Offset Acronym Register Description 0504h QUEUE1_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 1 Section 5.41 Section 0508h QUEUE2_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 2 Section 5.41 050Ch QUEUE3_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 3 Section 5.41 0510h QUEUE4_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 4 Section 5.
www.ti.com SRIO Registers Table 40. Serial RapidIO (SRIO) Registers (continued) 106 Offset Acronym Register Description 063Ch QUEUE15_RXDMA_HDP Queue Receive DMA Head Descriptor Pointer Register 15 Section 5.43 Section 0680h QUEUE0_RXDMA_CP Queue Receive DMA Completion Pointer Register 0 Section 5.44 0684h QUEUE1_RXDMA_CP Queue Receive DMA Completion Pointer Register 1 Section 5.44 0688h QUEUE2_RXDMA_CP Queue Receive DMA Completion Pointer Register 2 Section 5.
www.ti.com SRIO Registers Table 40. Serial RapidIO (SRIO) Registers (continued) Offset Acronym Register Description 0838h RXU_MAP_L7 MailBox-to-Queue Mapping Register L7 Section 5.50 Section 083Ch RXU_MAP_H7 MailBox-to-Queue Mapping Register H7 Section 5.50 0840h RXU_MAP_L8 MailBox-to-Queue Mapping Register L8 Section 5.50 0844h RXU_MAP_H8 MailBox-to-Queue Mapping Register H8 Section 5.50 0848h RXU_MAP_L9 MailBox-to-Queue Mapping Register L9 Section 5.
www.ti.com SRIO Registers Table 40. Serial RapidIO (SRIO) Registers (continued) 108 Offset Acronym Register Description 08F0h RXU_MAP_L30 MailBox-to-Queue Mapping Register L30 Section 5.50 Section 08F4h RXU_MAP_H30 MailBox-to-Queue Mapping Register H30 Section 5.50 08F8h RXU_MAP_L31 MailBox-to-Queue Mapping Register L31 Section 5.50 08FCh RXU_MAP_H31 MailBox-to-Queue Mapping Register H31 Section 5.50 0900h FLOW_CNTL0 Flow Control Table Entry Register 0 Section 5.
www.ti.com SRIO Registers Table 40. Serial RapidIO (SRIO) Registers (continued) Offset Acronym Register Description 117Ch SP1_CTL Port 1 Control CSR Section 5.73 Section 1180h SP2_LM_REQ Port 2 Link Maintenance Request CSR Section 5.69 1184h SP2_LM_RESP Port 2 Link Maintenance Response CSR Section 5.70 1188h SP2_ACKID_STAT Port 2 Local AckID Status CSR Section 5.71 1198h SP2_ERR_STAT Port 2 Error and Status CSR Section 5.72 119Ch SP2_CTL Port 2 Control CSR Section 5.
www.ti.com SRIO Registers Table 40. Serial RapidIO (SRIO) Registers (continued) 110 Offset Acronym Register Description 2100h SP3_ERR_DET Port 3 Error Detect CSR Section 5.82 Section 2104h SP3_RATE_EN Port 3 Error Enable CSR Section 5.83 2108h SP3_ERR_ATTR_CAPT_DBG0 Port 3 Attributes Error Capture CSR 0 Section 5.84 210Ch SP3_ERR_CAPT_DBG1 Port 3 Packet/Control Symbol Error Capture CSR 1 Section 5.
www.ti.com SRIO Registers 5.2 Peripheral Identification Register (PID) The peripheral identification register (PID) is a read-only register that contains the ID and ID revision number for that peripheral. The PID stores version information used to identify the peripheral. Writes have no effect to this register. The values are hard coded and will not change from their reset state. The peripheral ID register (PID) is shown in Figure 63 and described in Table 41. Figure 63.
www.ti.com SRIO Registers 5.3 Peripheral Control Register (PCR) The peripheral control register (PCR) contains a bit that enables or disables data flow in the logical layer of the entire peripheral. In addition, the PCR has emulation control bits that control the peripheral behavior during emulation halts. PCR is shown in Figure 64 and described in Table 42. For additional programming information, see Section 2.3.11. Figure 64.
www.ti.com SRIO Registers 5.4 Peripheral Settings Control Register (PER_SET_CNTL) The peripheral settings control register (PER_SET_CNTL) is shown in Figure 65 and described in Table 43. For additional programming information, see Section 2.3.12. Figure 65.
www.ti.com SRIO Registers Table 43. Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions (continued) Bit 17–15 Field TX_PRI1_WM Value 000b–111b Description Transmit credit threshold. Sets the required number of logical layer TX buffers needed to send priority 1 packets across the UDI. This is valid for all ports in 1x mode only.
www.ti.com SRIO Registers Table 43. Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions (continued) Bit Field Value Description 3 ENPLL4 0 Not used. Should always be programmed as "0". See Section 2.3.2.1 to enable SERDES PLL. 2 ENPLL3 0 Not used. Should always be programmed as "0". See Section 2.3.2.1 to enable SERDES PLL. 1 ENPLL2 0 Not used. Should always be programmed as "0". See Section 2.3.2.1 to enable SERDES PLL. 0 ENPLL1 0 Not used.
www.ti.com SRIO Registers 5.5 Peripheral Global Enable Register (GBL_EN) GBL_EN is implemented with a single enable bit for the entire SRIO peripheral. This bit is logically ORed with the reset input to the module and is fanned out to all logical blocks within the peripheral. GBL_EN is shown in Figure 66 and described in Table 44. For additional programming information, see Section 2.3.10. Figure 66.
www.ti.com SRIO Registers 5.6 Peripheral Global Enable Status Register (GBL_EN_STAT) The peripheral global enable status register (GBL_EN_STAT) is shown in Figure 67 and described in Table 45. For additional programming information, see Section 2.3.10. Figure 67.
www.ti.com SRIO Registers Table 45. Peripheral Global Enable Status Register (GBL_EN_STAT) Field Descriptions (continued) Bit 1 0 118 Field Value BLK0_EN_STAT Block 0 enable status. Logical block 0 is the set of memory-mapped registers (MMRs) for the SRIO peripheral. 0 Logical block 0 is in reset with its clock off. 1 Logical block 0 is enabled with its clock running. GBL_EN_STAT Serial RapidIO (SRIO) Description Global enable status 0 The peripheral is in reset with all its clocks off.
www.ti.com SRIO Registers 5.7 Block n Enable Register (BLKn_EN) There are nine of these registers, one for each of nine logical blocks in the peripheral. The registers and the blocks they support are listed in Table 46. The general form for a block n enable register (BLKn_EN) is shown in Figure 68 and described in Table 47. For additional programming information, see Section 2.3.10. Table 46.
www.ti.com SRIO Registers 5.8 Block n Enable Status Register (BLKn_EN_STAT) There are nine of these registers, one for each of nine logical blocks in the peripheral. The registers and the blocks they support are listed in Table 48. The general form for a block n enable status register (BLKn_EN_STAT) is shown in Figure 69 and described in Table 49. For additional programming information, see Section 2.3.10. Table 48.
www.ti.com SRIO Registers 5.9 RapidIO DEVICEID1 Register (DEVICEID_REG1) The RapidIO DEVICEID1 register (DEVICEID_REG1) is shown in Figure 70 and described in Table 50. Figure 70. RapidIO DEVICEID1 Register (DEVICEID_REG1) (Offset 0080h) 31 24 23 16 Reserved 8BNODEID R-00h R/W-FFh 15 0 16BNODEID R/W-FFFFh LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset Table 50.
www.ti.com SRIO Registers 5.10 RapidIO DEVICEID2 Register (DEVICEID_REG2) The RapidIO DEVICEID2 register (DEVICEID_REG2 is shown in Figure 71 and described in Table 51. For additional programming information, see Section 2.3.15.1 and Section 2.3.15.3. Figure 71. RapidIO DEVICEID2 Register (DEVICEID_REG2) (Offset 0x0084) 31 24 23 16 Reserved 8BNODEID R-00h R/W-FFh 15 0 16BNODEID R-FFFFh LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset Table 51.
www.ti.com SRIO Registers 5.11 Packet Forwarding Register n for 16-Bit Device IDs (PF_16B_CNTLn) There are four of these registers (see Table 52). The general form of a packet forwarding register for 16-bit DeviceIDs is shown in Figure 72 and described in Table 53. For additional programming information, see Section 2.3.15 and Section 2.3.15.3. Table 52. PF_16B_CNTL Registers Register Address Offset PF_16B_CNTL0 0090h PF_16B_CNTL1 0098h PF_16B_CNTL2 00A0h PF_16B_CNTL3 00A8h Figure 72.
www.ti.com SRIO Registers 5.12 Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTLn) There are four of these registers (see Table 54). The general form of a packet forwarding register for 16-bit DeviceIDs is shown in Figure 73 and described in Table 55. For additiona programming information see Section 2.3.15 and and Section 2.3.15.3. Table 54. PF_8B_CNTL Registers Register Address Offset PF_8B_CNTL0 0094h PF_8B_CNTL1 009Ch PF_8B_CNTL2 00A4h PF_8B_CNTL3 00ACh Figure 73.
www.ti.com SRIO Registers 5.13 SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) There are four of these registers, to support four ports (see ). The general form for a SERDES receive channel configuration register is summarized by Figure 74 and Table 57. See Section 2.3.2.2 for a complete explanation of the programming of these registers. Table 56.
www.ti.com SRIO Registers Table 57. SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) Field Descriptions (continued) Bit Field 15–14 LOS 13–12 11 10–8 7 6–5 4–2 Value Description Loss of signal. Enables loss of signal detection with 2 selectable thresholds. 00b Disabled. Loss of signal detection disabled. 01b High threshold. Loss of signal detection threshold in the range 85 to 195mVdfpp. This setting is suitable for Infiniband. 10b Low threshold.
www.ti.com SRIO Registers Table 58.
www.ti.com SRIO Registers 5.14 SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL) There are four of these registers, to support four ports (see Table 59). The general form for a SERDES transmit channel configuration register is summarized by Figure 75 and Table 60. See Section 2.3.2.3 for a complete explanation of the programming for these registers. Table 59.
www.ti.com SRIO Registers Table 60. SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL) Field Descriptions (continued) Bit Field 0 ENTX Value Description Enable transmitter 0 Disable this transmitter. 1 Enable this transmitter. Table 61. DE Bits of SERDES_CFGTXn_CNTL Amplitude Reduction DE Bits % dB 0000b 0 0 0001b 4.76 –0.42 0010b 9.52 –0.87 0011b 14.28 –1.34 0100b 19.04 –1.83 0101b 23.8 –2.36 0110b 28.56 –2.92 0111b 33.32 –3.52 1000b 38.08 –4.
www.ti.com SRIO Registers 5.15 SERDES Macro Configuration Register n (SERDES_CFGn_CNTL) There are four of these registers, to support four ports (see Table 63). The general form for a SERDES transmit channel configuration register is summarized by Figure 76 and Table 64. See Section 2.3.2.1 for a complete explanation of the programming of this register. Table 63.
www.ti.com SRIO Registers Table 64. SERDES Macro Configuration Register n (SERDES_CFGn_CNTL) Field Descriptions (continued) Bit Field 5–1 MPY 0 Value PLL multiply. Select PLL multiply factors between 4 and 60. 00000b 4x 00001b 5x 00010b 6x 00011b Reserved 00100b 8x 00101b 10x 00110b 12x 00111b 12.
www.ti.com SRIO Registers 5.16 DOORBELLn Interrupt Condition Status Register (DOORBELLn_ICSR) The four doorbell interrupts are mapped to these registers (see Table 65). The general form of a doorbell interrupt condition status register is shown in Figure 77 and described in Table 66. For additional programming information, see Section 4.3.1 and Section 2.3.6. Table 65.
www.ti.com SRIO Registers 5.17 DOORBELLn Interrupt Condition Clear Register (DOORBELLn_ICCR) The four doorbells interrupts that are mapped are cleared by this register (see Table 67). The general form of a doorbell interrupt condition clear register is shown in Figure 78 and described in Table 68. For additional programming information, see Section 4.4.1 and Section 2.3.6. Table 67.
www.ti.com SRIO Registers 5.18 RX CPPI Interrupt Status Register (RX_CPPI_ICSR) The bits in this register indicate any active interrupt requests from RX buffer descriptor queues. The RX CPPI interrupt status register (RX_CPPI_ICSR) is shown in Figure 79 and described in Table 69. For additional programming information, see Section 4.3.2. Figure 79.
www.ti.com SRIO Registers 5.19 RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) This register is used to clear bits in RX_CPPI_ICSR to acknowledge interrupts from the RX buffer descriptor queues. The RX CPPI interrupt clear register (RX_CPPI_ICCR) is shown in Figure 80 and described in Table 70. For additional programming information, see Section 4.3.2. Figure 80.
www.ti.com SRIO Registers 5.20 TX CPPI Interrupt Status Register (TX_CPPI_ICSR) The bits in this register indicate any active interrupt requests from TX buffer descriptor queues. TX_CPPI_ICSR is shown in Figure 81 and described in Table 71. Figure 81.
www.ti.com SRIO Registers 5.21 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) This register is used to clear bits in TX_CPPI_ICSR to acknowledge interrupts from the TX buffer descriptor queues. TX_CPPI_ICCR is shown in Figure 82 and described in Table 72. Figure 82.
www.ti.com SRIO Registers 5.22 LSU Interrupt Condition Status Register (LSU_ICSR) Each of the status bits in this register indicates the occurrence of a particular type of transaction interrupt condition for a particular LSU. LSU_ICSR is shown in Figure 83 and described in Table 73. For additional programming information, see Section 4.3.3. Figure 83.
www.ti.com SRIO Registers Table 73. LSU Interrupt Condition Status Register (LSU_ICSR) Field Descriptions (continued) Bit Field Value 19 ICS19 0 LSU3 interrupt condition not detected. 1 LSU3 interrupt condition detected. Transaction was not sent due to unsupported transaction type or invalid field encoding. 0 LSU3 interrupt condition not detected. 1 LSU3 interrupt condition detected. Transaction was not sent due to Xoff condition. 0 LSU3 interrupt condition not detected.
www.ti.com SRIO Registers Table 73. LSU Interrupt Condition Status Register (LSU_ICSR) Field Descriptions (continued) Bit Field Value 1 ICS1 0 LSU1 interrupt condition not detected. 1 LSU1 interrupt condition detected. Non-posted transaction received ERROR response, or error in response payload. 0 LSU1 interrupt condition not detected. 1 LSU1 interrupt condition detected. Transaction complete, No errors (posted/non-posted).
www.ti.com SRIO Registers 5.23 LSU Interrupt Condition Clear Register (LSU_ICCR) Setting a bit in this register clears the corresponding bit in LSU_ICSR, to acknowledge the interrupt. LSU_ICCR is shown in Figure 84 and described in Table 74. For additional programming information, see Section 4.3.3. Figure 84.
www.ti.com SRIO Registers 5.24 Error, Reset, and Special Event Interrupt Condition Status Register (ERR_RST_EVNT_ICSR) Each of the nonreserved bits in this register indicate the status of a particular interrupt condition in one or more of the SRIO ports. ERR_RST_EVNT_ICSR is shown in Figure 85 and described in Table 75. For additional programming information, see Section 4.3.4. Figure 85.
www.ti.com SRIO Registers 5.25 Error, Reset, and Special Event Interrupt Condition Clear Register (ERR_RST_EVNT_ICCR) Each bit in this register is used to clear the corresponding status bit in ERR_RST_EVNT_ICSR. The field of ERR_RST_EVNT_ICCR are shown in Figure 86 and described in Table 76. For additional programming information, see Section 4.3.4. Figure 86.
www.ti.com SRIO Registers 5.26 DOORBELLn Interrupt Condition Routing Registers (DOORBELLn_ICRR and DOORBELLn_ICRR2) When doorbell packets are received by the SRIO peripheral, these ICRRs route doorbell interrupt requests from the associated doorbell ICSR to user-selected interrupt destinations. Each of the four doorbells can be mapped to these registers (see Table 77). The general field description in Table 78 applies to an ICRx field of either register.
www.ti.com SRIO Registers 5.27 RX CPPI Interrupt Condition Routing Registers (RX_CPPI_ICRR and RX_CPPI_ICRR2) Figure 88 and Table 79 summarize the ICRRs for the RXU. These registers route queue interrupts to interrupt destinations. For example, if ICS6 = 1 in RX_CPPI_ICSR and ICR6 = 0010b in RX_CPPI_ICRR, the interrupt request from RX buffer descriptor queue 6 is sent to interrupt destination 2. For additional programming see Section 4.4.1.1. Figure 88.
www.ti.com SRIO Registers 5.28 TX CPPI Interrupt Condition Routing Registers (TX_CPPI_ICRR and TX_CPPI_ICRR2) Figure 89 and Table 80 summarize the ICRRs for the TXU. These registers route queue interrupts to interrupt destinations. For example, if ICS6 = 1 in TX_CPPI_ICSR and ICR6 = 0011b in TX_CPPI_ICRR, the interrupt request from TX buffer descriptor queue 6 is sent to interrupt destination 3. For additional programming see Section 4.4.1.1. Figure 89.
www.ti.com SRIO Registers 5.29 LSU Interrupt Condition Routing Registers (LSU_ICRR0–LSU_ICRR3) Figure 90 shows the ICRRs for the LSU interrupt requests, and Table 81 shows the general description for an ICRx field in any of the four registers. These registers route LSU interrupt requests from LSU_ICSR to interrupt destinations.
www.ti.com SRIO Registers Table 81. LSU Interrupt Condition Routing Register Field Descriptions Field Value ICRx (x = 0 to 31) 148 Description Interrupt condition routing. Routes the associated LSU interrupt request to one of eight interrupt destinations (INTDST0–INTDST7). Bits ICR0–ICR7 are for LSU1; bits ICR8–ICR15, for LSU2; bits ICR16–ICR23, for LSU3; bits ICR24–ICR31, for LSU4.
www.ti.com SRIO Registers 5.30 Error, Reset, and Special Event Interrupt Condition Routing Registers (ERR_RST_EVNT_ICRR, ERR_RST_EVNT_ICRR2, and ERR_RST_EVNT_ICRR3) The ICRRs shown in Figure 91 route port interrupt requests from ERR_RST_EVNT_ICSR to interrupt destinations. For example, if ICS8 = 1 in ERR_RST_EVNT_ICSR and ICR8 = 0001b in ERR_RST_EVNT_ICRR2, port 0 has generated an error interrupt request, and that request is routed to interrupt destination 1.
www.ti.com SRIO Registers 5.31 Interrupt Status Decode Register (INTDSTn_DECODE) There are eight of these registers, one for each interrupt destination (see Table 83). This type of register is shown in Figure 92 and described in Table 84. Interrupt sources are mapped to an interrupt decode register only if the ICRRs routes the interrupt source to the corresponding physical interrupt. Each status decode bit is a logical OR of multiple interrupt sources that are mapped to the same bit.
www.ti.com SRIO Registers Table 84. Interrupt Status Decode Register (INTDSTn_DECODE) Field Descriptions (continued) Bit Field Value 27 ISD27 0 Description No interrupt request routed to this bit. 1 Interrupt request detected. Possible interrupt sources: • TX buffer descriptor queue 4 (bit 4 of TX_CPPI_ICSR) • RX buffer descriptor queue 4 (bit 4 of RX_CPPI_ICSR) 26 ISD26 0 No interrupt request routed to this bit. 1 Interrupt request detected.
www.ti.com SRIO Registers Table 84. Interrupt Status Decode Register (INTDSTn_DECODE) Field Descriptions (continued) Bit Field Value 15 ISD15 0 Description No interrupt request routed to this bit. 1 Interrupt request detected.
www.ti.com SRIO Registers Table 84. Interrupt Status Decode Register (INTDSTn_DECODE) Field Descriptions (continued) Bit Field Value 7 ISD7 0 Description No interrupt request routed to this bit. 1 Interrupt request detected.
www.ti.com SRIO Registers 5.32 INTDSTn Interrupt Rate Control Register (INTDSTn_RATE_CNTL) There are eight interrupt rate control registers, one for each interrupt destination (see Table 85). Figure 93 and Table 86 provide a general description for an interrupt rate control register. These registers are used to set the rate at which an interrupt can be generated for each interrupt destination. A write to one of the registers reloads a counter and immediately starts the counter decrementing.
www.ti.com SRIO Registers 5.33 LSUn Control Register 0 (LSUn_REG0) There are four of these registers, one for each LSU (see Table 87). The general description for an LSU control register 0 is shown in Figure 94 and described in Table 88. For additional programming see Section 2.3.3. Table 87. LSUn_REG0 Registers and the Associated LSUs Register Address Offset Associated LSU LSU1_REG0 0400h LSU1 LSU2_REG0 0420h LSU2 LSU3_REG0 0440h LSU3 LSU4_REG0 0460h LSU4 Figure 94.
www.ti.com SRIO Registers 5.34 LSUn Control Register 1 (LSUn_REG1) There are four of these registers, one for each LSU (see ). This register's content is shown in Figure 95 and described in Table 90. For additional programming see Section 2.3.3. Table 89. LSUn_REG1 Registers and the Associated LSUs Register Address Offset Associated LSU LSU1_REG1 0404h LSU1 LSU2_REG1 0424h LSU2 LSU3_REG1 0444h LSU3 LSU4_REG1 0464h LSU4 Figure 95.
www.ti.com SRIO Registers 5.35 LSUn Control Register 2 (LSUn_REG2) There are four of these registers, one for each LSU (see Table 91). LSUn_REG2 is shown in Figure 96 and described in Table 92. For additional programming see Section 2.3.3. Table 91. LSUn_REG2 Registers and the Associated LSUs Register Address Offset Associated LSU LSU1_REG2 0408h LSU1 LSU2_REG2 0428h LSU2 LSU3_REG2 0448h LSU3 LSU4_REG2 0468h LSU4 Figure 96.
www.ti.com SRIO Registers 5.36 LSUn Control Register 3 (LSUn_REG3) There are four of these registers, one for each LSU (see Table 93). LSUn_REG3 is shown in Figure 97 and described in Table 94. For additional programming see Section 2.3.3. Table 93. LSUn_REG3 Registers and the Associated LSUs Register Address Offset Associated LSU LSU1_REG3 040Ch LSU1 LSU2_REG3 042Ch LSU2 LSU3_REG3 044Ch LSU3 LSU4_REG3 046Ch LSU4 Figure 97.
www.ti.com SRIO Registers 5.37 LSUn Control Register 4 (LSUn_REG4) There are four of these registers, one for each LSU (see Table 95). LSUn_REG4 is shown in Figure 98 and described in Table 96. For additional programming see Section 2.3.3. Table 95. LSUn_REG4 Registers and the Associated LSUs Register Address Offset Associated LSU LSU1_REG4 0410h LSU1 LSU2_REG4 0430h LSU2 LSU3_REG4 0450h LSU3 LSU4_REG4 0470h LSU4 Figure 98.
www.ti.com SRIO Registers 5.38 LSUn Control Register 5 (LSUn_REG5) There are four of these registers, one for each LSU (see Table 97). LSUn_REG5 is shown in Figure 99 and described in Table 98. For additional programming see Section 2.3.3. Table 97. LSUn_REG5 Registers and the Associated LSUs Register Address Offset Associated LSU LSU1_REG5 0414h LSU1 LSU2_REG5 0434h LSU2 LSU3_REG5 0454h LSU3 LSU4_REG5 0474h LSU4 Figure 99.
www.ti.com SRIO Registers 5.39 LSUn Control Register 6 (LSUn_REG6) There are four of these registers, one for each LSU (see Table 99). LSUn_REG6 is shown in Figure 100 and described in Table 100. For additional programming see Section 2.3.3. Table 99. LSUn_REG6 Registers and the Associated LSUs Register Address Offset Associated LSU LSU1_REG6 0418h LSU1 LSU2_REG6 0438h LSU2 LSU3_REG6 0458h LSU3 LSU4_REG6 0478h LSU4 Figure 100.
www.ti.com SRIO Registers 5.40 LSUn Congestion Control Flow Mask Register (LSUn_FLOW_MASKS) There are four of these registers, one for each LSU (see Table 101). The fields of an LSUn_FLOW_MASKS register are summarized by Figure 101 and described in Table 102. The 16 bits within each FLOW_MASK field are summarized by Figure 102 and Table 103. For additional programming see Section 2.3.8. Table 101.
www.ti.com SRIO Registers Table 103.
www.ti.com SRIO Registers 5.41 Queue n Transmit DMA Head Descriptor Pointer Register (QUEUEn_TXDMA_HDP) There are sixteen of these registers (see Table 104). QUEUEn_TXDMA_HDP is shown in Figure 103 and described in Table 105. For additional programming information, see Section 2.3.4.2 . Table 104.
www.ti.com SRIO Registers 5.42 Queue n Transmit DMA Completion Pointer Register (QUEUEn_TXDMA_CP) There are sixteen of these registers (see Table 106). QUEUEn_TXDMA_CP is shown in Figure 104 and described in Table 107. For additional programming information, see Section 2.3.4.2 . Table 106.
www.ti.com SRIO Registers 5.43 Queue n Receive DMA Head Descriptor Pointer Register (QUEUEn_RXDMA_HDP) There are sixteen of these registers (see Table 108). QUEUEn_RXDMA_HDP is shown in Figure 105 and described in Table 109. For additional programming information, see Section 2.3.4.1 . Table 108.
www.ti.com SRIO Registers 5.44 Queue n Receive DMA Completion Pointer Register (QUEUEn_RXDMA_CP) There are sixteen of these registers (see Table 110). QUEUEn_RXDMA_CP is shown in Figure 106 and described in Table 111. For additional programming information, see Section 2.3.4.1 . Table 110.
www.ti.com SRIO Registers 5.45 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) Each bit in this register corresponds to one of the 16 TX buffer descriptor queues. If a 1 is written to a bit, the teardown process is initiated for the associated queue. TX_QUEUE_TEAR_DOWN is shown in Figure 107 and described in Table 112. Figure 107.
www.ti.com SRIO Registers 5.46 Transmit CPPI Supported Flow Mask Registers (TX_CPPI_FLOW_MASKS[0–7]) Each of the eight TX CPPI flow mask registers holds the flow masks for two TX descriptor buffer queues (see Table 113). Figure 108 shows the registers, and Figure 109 shows the general form of a flow mask. Each bit of a flow mask selects or deselects a flow for the associated TX queue (see Table 114). For additional programming information, see Section 2.3.8 . Table 113.
www.ti.com SRIO Registers Figure 108.
www.ti.com SRIO Registers Table 114.
www.ti.com SRIO Registers 5.47 Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) Each of this register's bits corresponds to one of the 16 RX buffer descriptor queues. If a 1 is written to a bit, the teardown process is started for the associated queue. RX_QUEUE_TEAR_DOWN is shown in Figure 110 and described in Table 115. For additional programming information, see Section 2.3.4.1 . Figure 110.
www.ti.com SRIO Registers 5.48 Receive CPPI Control Register (RX_CPPI_CNTL) Each bit in this register indicates whether the associated RX buffer descriptor queue must receive messages in the order the source device attempts to transmit them. RX_CPPI_CNTL is shown in and described in Table 116. For additional programming information, see Section 2.3.4.1 . Figure 111.
www.ti.com SRIO Registers 5.49 Transmit CPPI Weighted Round Robin Control Registers (TX_QUEUE_CNTL[0–3]) The transmission order among TX buffer descriptor queues is based on the programmable weighted round-robin scheme explained in Section 2.3.4.2. As part of this scheme, software must program the 16 mappers to determine the order in which the queues are serviced and how many messages are handled in each queue during each time around the round-robin cycle.
www.ti.com SRIO Registers Table 117. Transmit CPPI Weighted Round Robin Control Register Field Descriptions Field Pair Register[Bits] TX_Queue_Map0 TX_Queue_Map3 0h to Fh Pointer to a queue. This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues. TX_QUEUE_CNTL0[7–4] Number of Msgs 0h to Fh Number of contiguous messages (descriptors) to process before moving to TX_Queue_Map1. TX_QUEUE_CNTL0[11–8] Queue Pointer 0h to Fh Pointer to a queue.
www.ti.com SRIO Registers Table 117. Transmit CPPI Weighted Round Robin Control Register Field Descriptions (continued) Field Pair TX_Queue_Map9 TX_Queue_Map10 TX_Queue_Map11 TX_Queue_Map12 TX_Queue_Map13 TX_Queue_Map14 TX_Queue_Map15 176 Serial RapidIO (SRIO) Register[Bits] Field Value Description TX_QUEUE_CNTL2[11–8] Queue Pointer 0h to Fh Pointer to a queue. This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues.
www.ti.com SRIO Registers 5.50 Mailbox to Queue Mapping Registers (RXU_MAP_Ln and RXU_MAP_Hn) Messages addressed to any of the 64 mailbox locations can be received on any of the RapidIO ports simultaneously. Packets are handled sequentially in order of receipt. A block of 32 mappers directs the inbound messages to the appropriate RX queues. After a device reset, software must configure each of the mappers to map incoming messages with selected mailbox and letter numbers to the desired queue.
www.ti.com SRIO Registers Table 118.
www.ti.com SRIO Registers Figure 113.
www.ti.com SRIO Registers Table 120. Mailbox-to-Queue Mapping Register Hn (RXU_MAP_Hn) Field Descriptions (continued) Bit Field 7–6 Reserved 5–2 QUEUE_ID 1 0 180 Value 0 0–15 PROMISCUOUS These read-only bits return 0s when read. Queue identification number. This field selects which of the 16 RX buffer queues is associated with mapper n. Promiscuous access 0 Mapper n checks the incoming sourceID (access is restricted to one sender).
www.ti.com SRIO Registers 5.51 Flow Control Table Entry Register n (FLOW_CNTLn) There are sixteen of these registers (see Table 121). FLOW_CNTLn is shown in Figure 114 and described in Table 122. For additional programming information, see Section 2.3.8. Table 121.
www.ti.com SRIO Registers 5.52 Device Identity CAR (DEV_ID) The device identity CAR (DEV_ID) is shown in Figure 115 and described in Table 123. Writes have no effect to this register. The values are hard coded and will not change from their reset state. Figure 115. Device Identity CAR (DEV_ID) - Address Offset 1000h 31 16 15 0 DEVICEIDENTITY DEVICE_VENDORIDENTITY R-0000h R-0030h LEGEND: R = Read only; -n = Value after reset Table 123.
www.ti.com SRIO Registers 5.53 Device Information CAR (DEV_INFO) The device information CAR (DEV_INFO) is shown in Figure 116 and described in Table 124. Writes have no effect to this register. The values are hard coded and will not change from their reset state. Figure 116. Device Information CAR (DEV_INFO) - Address Offset 1004h 31 0 DEVICEREV R-00000000h LEGEND: R = Read only; -n = Value after reset Table 124.
www.ti.com SRIO Registers 5.54 Assembly Identity CAR (ASBLY_ID) The assembly identity CAR (ASBLY_ID) is shown in Figure 117 and described in Table 125. Writes have no effect to this register. The values are hard coded and will not change from their reset state. Figure 117. Assembly Identity CAR (ASBLY_ID) - Address Offset 1008h 31 16 15 0 ASSY_IDENTITY ASSY_VENDORIDENTITY R-0000h R-0030h LEGEND: R = Read only; -n = Value after reset Table 125.
www.ti.com SRIO Registers 5.55 Assembly Information CAR (ASBLY_INFO) The assembly information CAR (ASBLY_INFO) is shown in Figure 118 and described in Table 126. This register is used by SERDES vendor to designate endpoints among the various function blocks of registers. Writes have no effect to this register. The values are hard coded and will not change from their reset state. Figure 118.
www.ti.com SRIO Registers 5.56 Processing Element Features CAR (PE_FEAT) The processing element features CAR (PE_FEAT) is shown in Figure 119 and described in Table 127. Figure 119.
www.ti.com SRIO Registers Table 127. Processing Element Features CAR (PE_FEAT) Field Descriptions (continued) Bit Field 2–0 EXTENDED_ADDRESSING_SUPPORT SPRUE13A – September 2006 Submit Documentation Feedback Value Description Indicates the number address bits supported by the PE both as a source and target of an operation. All PEs shall at minimum support 34 bit addresses. Encodings other than below are reserved.
www.ti.com SRIO Registers 5.57 Source Operations CAR (SRC_OP) The source operations CAR (SRC_OP) is shown in Figure 120 and described in Table 128. Figure 120.
www.ti.com SRIO Registers 5.58 Destination Operations CAR (DEST_OP) The destination operations CAR (DEST_OP) is shown in Figure 121 and described in Table 129. Figure 121.
www.ti.com SRIO Registers 5.59 Processing Element Logical Layer Control CSR (PE_LL_CTL) The processing element logical layer control CSR (PE_LL_CTL) is shown in Figure 122 and described in Table 130. Figure 122. Processing Element Logical Layer Control CSR (PE_LL_CTL) - Address Offset 104Ch 31 16 Reserved R-0 15 3 2 0 Reserved EXTENDED_ ADDRESSING_ CONTROL R-0 R/W-001 LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset Table 130.
www.ti.com SRIO Registers 5.60 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) The local configuration space base address 0 CSR (LCL_CFG_HBAR) is shown in Figure 123 and described in Table 131. Figure 123. Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) - Address Offset 1058h 31 30 0 Reserved LCSBA R-0 R-00000000h LEGEND: R = Read only; -n = Value after reset Table 131.
www.ti.com SRIO Registers 5.61 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) The local configuration space base address 1 CSR (LCL_CFG_BAR) is shown in Figure 124 and described in Table 132. Figure 124. Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) - Address Offset 105Ch 31 0 LCSBA R-00000000h LEGEND: R = Read only; -n = Value after reset Table 132.
www.ti.com SRIO Registers 5.62 Base Device ID CSR (BASE_ID) The base device ID CSR (BASE_ID) is shown in Figure 125 and described in Table 133. Figure 125. Base Device ID CSR (BASE_ID) - Address Offset 1060h 31 24 23 16 Reserved BASE_DEVICEID R-00h R/W-FFh 15 0 LARGE_BASE_DEVICEID R/W-FFFFh LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset Table 133.
www.ti.com SRIO Registers 5.63 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) See Section 2.4.2 of the RapidIO Common Transport Specification for a description of this register. It provides a lock function that is write-once/reset-able. The host base device ID lock CSR (HOST_BASE_ID_LOCK) is shown in Figure 126 and described in Table 134. Figure 126.
www.ti.com SRIO Registers 5.64 Component Tag CSR (COMP_TAG) The component Tag CSR (COMP_TAG) is shown in Figure 127 and described in Table 135. Figure 127. Component Tag CSR (COMP_TAG) - Address Offset 106Ch 31 0 COMPONENT_TAG R/W-00000000h LEGEND: R/W = Read/Write; -n = Value after reset Table 135.
www.ti.com SRIO Registers 5.65 1x/4x LP Serial Port Maintenance Block Header Register (SP_MB_HEAD) The 1x/4x LP_Serial port maintenance block header register (SP_MB_HEAD) is shown in Figure 128 and described in Table 136. Figure 128. 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) - Address Offset 1100h 31 16 15 0 EF_PTR EF_ID R-1000h R-0001h LEGEND: R = Read only; -n = Value after reset Table 136.
www.ti.com SRIO Registers 5.66 Port Link Time-Out Control CSR (SP_LT_CTL) The port link time-out control CSR (SP_LT_CTL) is shown in Figure 129 and described in Table 137. Figure 129. Port Link Time-Out Control CSR (SP_LT_CTL) - Address Offset 1120h 31 TIMEOUT_VALUE R/W-FFFFFFh 8 7 0 TIMEOUT_VALUE Reserved R/W-FFFFFFh R-00h LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset Table 137.
www.ti.com SRIO Registers 5.67 Port Response Time-Out Control CSR (SP_RT_CTL) The port response time-out control CSR (SP_RT_CTL) is shown in Figure 130 and described in Table 138 For additional programming information, see Section 2.3.3.3 and Section 2.3.3. Figure 130. Port Response Time-Out Control CSR (SP_RT_CTL) - Address Offset 1124h 31 TIMEOUT_VALUE RW-FFFFFFh 8 7 0 TIMEOUT_VALUE Reserved RW-FFFFFFh R-00h LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset Table 138.
www.ti.com SRIO Registers 5.68 Port General Control CSR (SP_GEN_CTL) The port general control CSR (SP_GEN_CTL) is shown in Figure 131 and described in Table 139. Figure 131. Port General Control CSR (SP_GEN_CTL) - Address Offset 113Ch 31 30 29 HOST MASTER_ ENABLE 28 0 DISCOVERED Reserved R/W-0 R/W-0 R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset Table 139.
www.ti.com SRIO Registers 5.69 Port Link Maintenance Request CSR n (SPn_LM_REQ) Each of the four ports is supported by a register of this type (see Table 140). SPn_LM_REQ is shown in Figure 132 and described in Table 141. Table 140. SPn_LM_REQ Registers and the Associated Ports Register Address Offset Associated Port SP0_LM_REQ 1140h Port 0 SP1_LM_REQ 1160h Port 1 SP2_LM_REQ 1180h Port 2 SP3_LM_REQ 11A0h Port 3 Figure 132.
www.ti.com SRIO Registers 5.70 Port Link Maintenance Response CSR n (SPn_LM_RESP) Each of the four ports is supported by a register of this type (see Table 142). The port link maintenance response CSR n (SPn_LM_RESP) is shown in Figure 133 and described in Table 143. Table 142. SPn_LM_RESP Registers and the Associated Ports Register Address Offset Associated Port SP0_LM_RESP 1144h Port 0 SP1_LM_RESP 1164h Port 1 SP2_LM_RESP 1184h Port 2 SP3_LM_RESP 11A4h Port 3 Figure 133.
www.ti.com SRIO Registers 5.71 Port Local AckID Status CSR n (SPn_ACKID_STAT) Each of the four ports is supported by a register of this type (see Table 144). The port local ackID status CSR n (SPn_ACKID_STAT) is shown in Figure 134 and described in Table 145. Table 144. SPn_ACKID_STAT Registers and the Associated Ports Register Address Offset Associated Port SP0_ACKID_STAT 1148h Port 0 SP1_ACKID_STAT 1168h Port 1 SP2_ACKID_STAT 1188h Port 2 SP3_ACKID_STAT 11A8h Port 3 Figure 134.
www.ti.com SRIO Registers 5.72 Port Error and Status CSR n (SPn_ERR_STAT) Each of the four ports is supported by a register of this type (see Table 146). The port error and status CSR n (SPn_ERR_STAT) is shown in Figure 135 and described in Table 147. Table 146. SPn_ERR_STAT Registers and the Associated Ports Register Address Offset Associated Port SP0_ERR_STAT 1158h Port 0 SP1_ERR_STAT 1178h Port 1 SP2_ERR_STAT 1198h Port 2 SP3_ERR_STAT 11B8h Port 3 Figure 135.
www.ti.com SRIO Registers Table 147. Port Error and Status CSR n (SPn_ERR_STAT) Field Descriptions (continued) Bit 23–21 20 19 18 17 16 15–11 10 9 Value 0 OUTPUT_RETRY_ENC The output port has not encountered a retry condition. 1 The output port has encountered a retry condition. This bit is set when bit 18 is set. Output retried. OUTPUT_RETRIED is a read-only bit. 0 The output port has not received a packet-retry control symbol.
www.ti.com SRIO Registers Table 147. Port Error and Status CSR n (SPn_ERR_STAT) Field Descriptions (continued) Bit 1 0 Field Value PORT_OK Port OK. This bit is a read-only bit. 0 Port not-OK condition 1 Port OK condition. The input and output ports are initialized, and the port is exchanging error-free control symbols with the attached device. PORT_UNINITIALIZED SPRUE13A – September 2006 Submit Documentation Feedback Description Port uninitialized. PORT_UNINITIALIZED is a read-only bit.
www.ti.com SRIO Registers 5.73 Port Control CSR n (SPn_CTL) Each of the four ports is supported by a register of this type (see Table 148). The port control CSR n (SPn_CTL) is shown in Figure 136 and described in Table 149. To change from 1 lane to 4 lanes there are 2 registers that need to be programmed. The SP_IP_MODE (offset 0x12004) bits 31-30 are set to be 1x/4p or 4 ports (1x mode each). The PER_SET_CNTL (offset 0x0020) bit 8 is set up for port (1x/4p) or priority based (1x mode each). Table 148.
www.ti.com SRIO Registers Table 149. Port Control CSR n (SPn_CTL) Field Descriptions (continued) Bit 26–24 Field Value PORT_WIDTH_OVERRIDE Port width override. This read-only field is available as a software means to override the hardware width. 000b No override 001b Reserved 010b Force single lane, lane 0 011b Force single lane, lane 2 100b–111b 23 22 21 20 19 18–4 3 2 1 Description PORT_DISABLE Reserved Port disable 0 Port receivers/drivers are enabled.
www.ti.com SRIO Registers Table 149. Port Control CSR n (SPn_CTL) Field Descriptions (continued) Bit 0 208 Field PORT_TYPE Serial RapidIO (SRIO) Value 1 Description Port type. This read-only bit indicates that the port is a serial port rather than a parallel port.
www.ti.com SRIO Registers 5.74 Error Reporting Block Header Register (ERR_RPT_BH) The Error Reporting Block Header Register (ERR_RPT_BH) is shown in Figure 137 and described in Table 150. Figure 137. Error Reporting Block Header Register (ERR_RPT_BH) - Address Offset 2000h 31 16 15 0 EF_PTR EF_ID R-0000h R-0007h LEGEND: R = Read only; -n = Value after reset Table 150.
www.ti.com SRIO Registers 5.75 Logical/Transport Layer Error Detect CSR (ERR_DET) This register allows for the detection of logical/transport layer errors. The detectable errors are captured in the fields shown in Figure 138 and described in Table 151. For additional programming information, see Section 3 . Figure 138.
www.ti.com SRIO Registers Table 151. Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions (continued) Bit Field 25 MSG_REQ_TIMEOUT 24 23 22 21–8 7 6 5–0 Value Message request timeout (endpoint device only) 0 A timeout has not been detected by RXU. 1 A timeout has been detected by the RXU. A required message request has not been received by the RXU within the specified time-out interval. To clear this bit, write 0 to it.
www.ti.com SRIO Registers 5.76 Logical/Transport Layer Error Enable CSR (ERR_EN) The logical/transport layer error enable CSR (ERR_EN) is shown in Figure 139 and described in Table 152. Figure 139.
www.ti.com SRIO Registers Table 152. Logical/Transport Layer Error Enable CSR (ERR_EN) Field Descriptions (continued) Bit Field 24 PKT_RESP_TIMEOUT_ENABLE 23 22 21–8 7 6 5–0 Value Packet response time-out error reporting enable 0 Disable reporting of a packet response time-out error. 1 Enable reporting of a packet response time-out error (endpoint device only). Save and lock original request address in Logical/Transport Layer Address Capture CSRs.
www.ti.com SRIO Registers 5.77 Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) The logical/transport layer high address capture CSR (H_ADDR_CAPT) is shown in Figure 140 and described in Table 153. Figure 140. Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) - Address Offset 2010h 31 0 ADDRESS_63_32 R-00000000h LEGEND: R = Read only; -n = Value after reset Table 153.
www.ti.com SRIO Registers 5.78 Logical/Transport Layer Address Capture CSR (ADDR_CAPT) The logical/transport layer address capture CSR (ADDR_CAPT) is shown in Figure 141 and described in Table 154. Figure 141. Logical/Transport Layer Address Capture CSR (ADDR_CAPT) - Address Offset 2014h 31 16 ADDRESS_31_3 R-0000h 15 3 2 1 0 ADDRESS_31_3 Reserved XAMSBS R-0000h R-0 R-00 LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset Table 154.
www.ti.com SRIO Registers 5.79 Logical/Transport Layer Device ID Capture CSR (ID_CAPT) The logical/transport layer device ID capture CSR (ID_CAPT) is shown in Figure 142 and described in Table 155. Figure 142. Logical/Transport Layer Device ID Capture CSR (ID_CAPT) - Address Offset 2018h 31 24 23 16 MSB_DESTID DESTID R-00h R-00h 15 8 7 0 MSB_SOURCEID SOURCEID R-00h R-00h LEGEND: R = Read only; -n = Value after reset Table 155.
www.ti.com SRIO Registers 5.80 Logical/Transport Layer Control Capture CSR (CTRL_CAPT) The logical/transport layer control capture CSR (CTRL_CAPT) is shown in Figure 143 and described in Table 156. Figure 143. Logical/Transport Layer Control Capture CSR (CTRL_CAPT) - Address Offset 201Ch 31 28 27 24 23 16 FTYPE TTYPE MSGINFO R-0h R-0h R-00h 15 0 IMP_SPECIFIC R-0000h LEGEND: R = Read only; -n = Value after reset Table 156.
www.ti.com SRIO Registers 5.81 Port-Write Target Device ID CSR (PW_TGT_ID) The port-write target device ID CSR (PW_TGT_ID) is shown in Figure 144 and described in Table 157. For additional programming information, see Section 2.3.5. Figure 144. Port-Write Target Device ID CSR (PW_TGT_ID) - Address Offset 2028h 31 24 23 16 DEVICEID_MSB DEVICEID R/W-00h R/W-00h 15 0 Reserved R-0000h LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset Table 157.
www.ti.com SRIO Registers 5.82 Port Error Detect CSR n (SPn_ERR_DET) Each of the four ports is supported by a register of this type (see Table 158). The port error detect CSR n (SPn_ERR_DET) is shown in Figure 145 and described in Table 159. Table 158. SPn_ERR_DET Registers and the Associated Ports Register Address Offset Associated Port SP0_ERR_DET 2040h Port 0 SP1_ERR_DET 2080h Port 1 SP2_ERR_DET 20C0h Port 2 SP3_ERR_DET 2100h Port 3 Figure 145.
www.ti.com SRIO Registers Table 159. Port Error Detect CSR n (SPn_ERR_DET) Field Descriptions (continued) Bit Field 20 RCVD_PKT_NOT_ACCPT 19 1 The port received a packet-not-accepted acknowledge control symbol. Unexpected ackID in packet 0 The port did not receive a packet with unexpected/out-of-sequence ackID. 1 The port received a packet with unexpected/out-of-sequence ackID. Bad CRC in packet 0 The port did not receive a packet with a bad CRC value.
www.ti.com SRIO Registers 5.83 Port Error Rate Enable CSR n (SPn_RATE_EN) Each of the four ports is supported by a register of this type (see Table 160). The port error rate enable CSR n (SPn_RATE_EN) is shown in Figure 146 and described in Table 161. Table 160. SPn_RATE_EN Registers and the Associated Ports Register Address Offset Associated Port SP0_RATE_EN 2044h Port 0 SP1_RATE_EN 2084h Port 1 SP2_RATE_EN 20C4h Port 2 SP3_RATE_EN 2104h Port 3 Figure 146.
www.ti.com SRIO Registers Table 161. Port Error Rate Enable CSR n (SPn_RATE_EN) Field Descriptions (continued) Bit Field 19 PKT_UNEXPECTED_ACKID_EN 18 4 Disable error rate counting of packets with unexpected/out-of-sequence ackIDs 1 Enable error rate counting of packets with unexpected/out-of-sequence ackIDs. Rate counting enable for packets with bad CRC 0 Disable error rate counting of packets with a bad CRC values. 1 Enable error rate counting of packets with a bad CRC values.
www.ti.com SRIO Registers 5.84 Port n Attributes Error Capture CSR 0 (SPn_ERR_ATTR_CAPT_DBG0) Each of the four ports is supported by a register of this type (see ). The port n attributes error capture CSR 0 (SPn_ERR_ATTR_CAPT_DBG0) is shown in Figure 147 and described in Table 163. Table 162.
www.ti.com SRIO Registers 5.85 Port n Error Capture CSR 1 (SPn_ERR_CAPT_DBG1) Each of the four ports is supported by a register of this type (see Table 164). SPn_ERR_CAPT_DBG1 is shown in Figure 148 and described in Table 165. Table 164. SPn_ERR_CAPT_DBG1 Registers and the Associated Ports Register Address Offset Associated Port SP0_ERR_CAPT_DBG1 204Ch Port 0 SP1_ERR_CAPT_DBG1 208Ch Port 1 SP2_ERR_CAPT_DBG1 20CCh Port 2 SP3_ERR_CAPT_DBG1 210Ch Port 3 Figure 148.
www.ti.com SRIO Registers 5.86 Port n Error Capture CSR 2 (SPn_ERR_CAPT_DBG2) Each of the four ports is supported by a register of this type (see Table 166). SPn_ERR_CAPT_DBG2 is shown in Figure 149 and described in Table 167. Table 166. SPn_ERR_CAPT_DBG2 Registers and the Associated Ports Register Address Offset Associated Port SP0_ERR_CAPT_DBG2 2050h Port 0 SP1_ERR_CAPT_DBG2 2090h Port 1 SP2_ERR_CAPT_DBG2 20D0h Port 2 SP3_ERR_CAPT_DBG2 2110h Port 3 Figure 149.
www.ti.com SRIO Registers 5.87 Port n Error Capture CSR 3 (SPn_ERR_CAPT_DBG3) Each of the four ports is supported by a register of this type (see Table 168). SPn_ERR_CAPT_DBG3 is shown in Figure 150 and described in Table 169. Table 168. SPn_ERR_CAPT_DBG3 Registers and the Associated Ports Register Address Offset Associated Port SP0_ERR_CAPT_DBG3 2054h Port 0 SP1_ERR_CAPT_DBG3 2094h Port 1 SP2_ERR_CAPT_DBG3 20D4h Port 2 SP3_ERR_CAPT_DBG3 2114h Port 3 Figure 150.
www.ti.com SRIO Registers 5.88 Port n Error Capture CSR 4 (SPn_ERR_CAPT_DBG4) Each of the four ports is supported by a register of this type (see Table 170). The port n packet/control symbol error capture CSR 4 (SPn_ERR_CAPT_DBG4) is shown in Figure 151 and described in Table 171. Table 170.
www.ti.com SRIO Registers 5.89 Port Error Rate CSR n (SPn_ERR_RATE) Each of the four ports is supported by a register of this type (see Table 172). SPn_ERR_RATE is shown in Figure 152 and described in Table 173. Table 172. SPn_ERR_RATE Registers and the Associated Ports Register Address Offset Associated Port SP0_ERR_RATE 2068h Port 0 SP1_ERR_RATE 20A8h Port 1 SP2_ERR_RATE 20E8h Port 2 SP3_ERR_RATE 2128h Port 3 Figure 152.
www.ti.com SRIO Registers 5.90 Port Error Rate Threshold CSR n (SPn_ERR_THRESH) Each of the four ports is supported by a register of this type (see ). The port error rate threshold CSR n (SPn_ERR_THRESH) is shown in Figure 153 and described in Table 175. Table 174. SPn_ERR_THRESH Registers and the Associated Ports Register Address Offset Associated Port SP0_ERR_THRESH 206Ch Port 0 SP1_ERR_THRESH 20ACh Port 1 SP2_ERR_THRESH 20ECh Port 2 SP3_ERR_THRESH 212Ch Port 3 Figure 153.
www.ti.com SRIO Registers 5.91 Port IP Discovery Timer for 4x Mode Register (SP_IP_DISCOVERY_TIMER) The port IP discovery timer for 4x mode register (SP_IP_DISCOVERY_TIMER) is shown in Figure 154 and described in Table 176. Figure 154.
www.ti.com SRIO Registers 5.92 Port IP Mode CSR (SP_IP_MODE) The port IP mode CSR (SP_IP_MODE) is shown in Figure 155 and described in Table 177. For additional programming information, see Section 2.3.13.2 . Figure 155.
www.ti.com SRIO Registers Table 177. Port IP Mode CSR (SP_IP_MODE) Field Descriptions (continued) Bit 3 2 1 0 232 Field Value RST_EN Reset Interrupt Enable. If enabled, the interrupt signal is High when the 4 reset control symbols are received in a sequence 0 Reset interrupt disable 1 Reset interrupt enable RST_CS Reset received status bit. It is set when Once set, the RST_CS bit remains set until software writes a 1 to it. The rst_irq output signal is driven by this bit.
www.ti.com SRIO Registers 5.93 Port IP Prescaler Register (IP_PRESCAL) The port IP prescaler register (IP_PRESCAL) is shown in Figure 156 and described in Table 178. This register defines a prescaler for different frequencies of the DMA clock.
www.ti.com SRIO Registers 5.94 Port-Write-In Capture CSRs (SP_IP_PW_IN_CAPT[0–3]) Four registers are used to capture the incoming 128-bit payload of a Port-Write. These four registers are shown in Figure 157. As can be seen in Table 179, each of the registers captures one of the four 32-bit words of the payload. Figure 157.
www.ti.com SRIO Registers 5.95 Port Reset Option CSR n (SPn_RST_OPT) Each of the four ports is supported by a register of this type (see Table 180). SPn_RST_OPT is shown in Figure 158 and described in Table 181. Table 180. SPn_RST_OPT Registers and the Associated Ports Register Address Offset Associated Port SP0_RST_OPT 14000h Port 0 SP1_RST_OPT 14100h Port 1 SP2_RST_OPT 14200h Port 2 SP3_RST_OPT 14300h Port 3 Figure 158.
www.ti.com SRIO Registers 5.96 Port Control Independent Register n (SPn_CTL_INDEP) Each of the four ports is supported by a register of this type (see Table 182). The port control independent register n (SPn_CTL_INDEP) is shown in Figure 159 and described in Table 183. Table 182. SPn_CTL_INDEP Registers and the Associated Ports Register Address Offset Associated Port SP0_CTL_INDEP 14004h Port 0 SP1_CTL_INDEP 14104h Port 1 SP2_CTL_INDEP 14204h Port 2 SP3_CTL_INDEP 14304h Port 3 Figure 159.
www.ti.com SRIO Registers Table 183. Port Control Independent Register n (SPn_CTL_INDEP) Field Descriptions (continued) Bit Field 23 DEBUG Value Description Mode of operation. 0 Normal mode 1 Debug mode. The debug mode unlocks capture registers for write and enable debug packet generator feature. 22 SEND_DBG_PKT Send debug packet. Write 1 to force the sending of a debug packet. This bit is set by software and cleared after debug packet is sent. Writes when the bit is set are ignored.
www.ti.com SRIO Registers 5.97 Port Silence Timer n Register (SPn_SILENCE_TIMER) Each of the four ports is supported by a register of this type (see Table 184). The port silence timer n register (SPn_SILENCE_TIMER) is shown in Figure 160 and described in Table 185. Table 184.
www.ti.com SRIO Registers 5.98 Port Multicast-Event Control Symbol Request Register n (SPn_MULT_EVNT_CS) Each of the four ports is supported by a register of this type (see Table 186). The port multicast-event control symbol request register n (SPn_MULT_EVNT_CS) is shown in Figure 161 and described in Table 187. Table 186.
www.ti.com SRIO Registers 5.99 Port Control Symbol Transmit n Register (SPn_CS_TX) Each of the four ports is supported by a register of this type (see Table 188). The port control symbol transmit n register (SPn_CS_TX) is shown in Figure 162 and described in Table 189. Table 188. SPn_CS_TX Registers and the Associated Ports Register Address Offset Associated Port SP0_CS_TX 14014h Port 0 SP1_CS_TX 14114h Port 1 SP2_CS_TX 14214h Port 2 SP3_CS_TX 14314h Port 3 Figure 162.
Index SPRUE13A – September 2006 Index 1x/4x LP serial port maintenance block header register 196 1x/4x mode selection field for ports 231 1X_MODE field of PER_SET_SNTL 113 2 MSBs of address for LSUn 159 4x/1x mode selection field for ports 231 4x mode data path in SRIO component block diagram 26 discovery timer period field 230 8-bit/10-bit coding and decoding 21 8BIT_DEVID_LOW_BOUND field of PF_8B_CNTL 124 8BIT_DEVID_UP_BOUND field of PF_8B_CNTL 124 8-bit device IDs lower boundary for packet forwarding 12
SRIO Registers BYTE_COUNT field of LSUn_REG3 158 B bad CRC in control symbol at port n rate counting enable field 221 status field 219 bad CRC in packet at port n rate counting enable field 222 status field 220 bandwidth per differential pair based on 1x/4x LP-Serial specification 18 BASE_DEVICEID field of BASE_ID 193 BASE_ID 193 base address registers for local configuration space 191, 192 base device ID CSR 193 base device ID for host PE 194 Big Endian versus Little Endian 68 binary notational convention
SRIO Registers at port n rate counting enable field 222 status field 220 bad CRC in control symbol at port n rate counting enable field 221 status field 219 detect 4 reset control symbols at port 232 detect multicast-event control symbol at port 231 enable interrupt if 4 reset control symbols received at port 232 enable interrupt if multicast-event control symbol received at port 231 force insertion of control symbol in outbound packet 240 initiate self reset interrupt if 4 link-request control symbols acce
SRIO Registers DEV_INFO 183 DEVICE_VENDORIDENTITY field of DEV_ID 182 DEVICEID_MSB field of PW_TGT_ID 218 DEVICEID_REG1 121 DEVICEID_REG2 122 device ID capture CSR for logical/transport errors 216 device identity CAR 182 DEVICEIDENTITY field of DEV_ID 182 DEVICEID field of PW_TGT_ID 218 device IDs base device ID for host PE 194 base device ID for large common transport system 193 base device ID for small common transport system 193 device ID for port-write target 218 disable base ID match requirement field
SRIO Registers ENPLL2 field of PER_SET_CNTL 113 ENPLL3 field of PER_SET_CNTL 113 ENPLL4 field of PER_SET_CNTL 113 ENPLL field of SERDES_CFGn_CNTL 130 ENRX field of SERDES_CFGRXn_CNTL 125 ENTX field of SERDES_CFGTXn_CNTL 128 eop field of RX buffer descriptor 47 eop field of TX buffer descriptor 52 eoq field of RX buffer descriptor 47 eoq field of TX buffer descriptor 52 EQ field of SERDES_CFGRXn_CNTL 125 equalizer control field 125 ERR_DET 210 ERR_EN 212 ERR_MSG_FORMAT_ENABLE field of ERR_EN 212 ERR_MSG_FORM
SRIO Registers G GBL_EN 116 GBL_EN_STAT 117 global enable bit 116 global enable status bit 118 global enabling/disabling of all logical blocks 71 H H_ADDR_CAPT 214 head descriptor pointer field for RX queue n 166 head descriptor pointer field for TX queue n 164 header fields doorbell operation 64 message request packet 44 hexadecimal notational convention 14 HOP_COUNT field of LSUn_REG5 160 host base device ID lock CSR 194 host device mode field 199 I ID_CAPT 216 ID_SIZE field of LSUn_REG4 159 idle error
SRIO Registers limiting which devices can access a mailbox 45 line rate versus PLL output clock frequency 29 LINK_STATUS field of SPn_LM_RESP 201 LINK_TIMEOUT_EN field of SPn_RATE_EN 221 LINK_TIMEOUT field of SPn_ERR_DET 219 link maintenance command field for port n 240 link-request control symbol generation register 200 link responses acknowledge or link-response control symbol overdue at port n rate counting enable field 222 status field 220 link-response valid field 201 link status received 201 non-outst
SRIO Registers MAX_RETRY_ERR field of SPn_CTL_INDEP 236 MAX_RETRY_THR field of SPn_CTL_INDEP 236 maximum packet size exceeded at port n rate counting enable field 222 status field 220 maximum retry error at port n reporting enable field 237 reporting threshold field 237 status field 237 memory access unit.
SRIO Registers OUTBOUND_ACKID field of SPn_ACKID_STAT 202 outbound credit 75 outbound port number for packet forwarding 124 out-of-order reception of message packets 49 out-of-order responses during message-passing TX operation 58 OUTPORTID field of LSUn_REG4 159 OUTPUT_DEGRD_ENC field of SPn_ERR_STAT 203 OUTPUT_ERROR_ENC field of SPn_ERR_STAT 203 OUTPUT_ERROR_STP field of SPn_ERR_STAT 203 OUTPUT_FLD_ENC field of SPn_ERR_STAT 203 OUTPUT_PKT_DROP field of SPn_ERR_STAT 203 OUTPUT_PORT_ENABLE field of SPn_CTL
SRIO Registers in SRIO component block diagram 26 PID register 111 pins/differential signals 25 PKT_RESP_TIMEOUT_ENABLE field of ERR_EN 212 PKT_RSPNS_TIMEOUT field of ERR_DET 210 PKT_UNEXPECTED_ACKID_EN field of SPn_RATE_EN 221 PKT_UNEXPECTED_ACKID field of SPn_ERR_DET 219 PLL block for SERDES 21, 28 PLL enable bit 131 PLL multiply field for SERDES macro 131 PLL output clock frequency versus line rate 29 pointer to the next block in the data structure 196 polarity inversion bit for RIORX and RIORX (receptio
SRIO Registers PW_DIS field of SP_IP_MODE 231 PW_EN field of SP_IP_MODE 231 PW_IRQ field of SP_IP_MODE 231 PW_TGT_ID 218 PW_TIMER field of SP_IP_DISCOVERY_TIMER 230 Q QUEUE_ID field of RXU_MAP_Hn 178 QUEUEn_FLOW_MASK fields of TX_CPPI_FLOW_MASKS[0–7] 169 QUEUEn_IN_ORDER fields of RX_CPPI_CNTL 173 QUEUEn_RXDMA_CP 167 QUEUEn_RXDMA_HDP 166 QUEUEn_TEAR_DWN fields of RX_QUEUE_TEAR_DOWN 172 QUEUEn_TEAR_DWN fields of TX_QUEUE_TEAR_DOWN 168 QUEUEn_TXDMA_CP 165 QUEUEn_TXDMA_HDP 164 queue n receive DMA completion po
SRIO Registers for doorbell interrupt conditions 144 for error, reset, and special event (port) interrupt conditions 149 for LSU interrupt conditions 147 RST_CS field of SP_IP_MODE 231 RST_EN field of SP_IP_MODE 231 rules for CPPI data traffic 43 RX_CP field of QUEUEn_RXDMA_CP 167 RX_CPPI_CNTL 173 RX_CPPI_ICCR 135 RX_CPPI_ICRR 145 RX_CPPI_ICRR2 145 RX_CPPI_ICSR 134 RX_CPPI_SECURITY_ENABLE field of ERR_EN 212 RX_CPPI_SECURITY field of ERR_DET 210 RX_HDP field of QUEUEn_RXDMA_HDP 166 RX_IO_DMA_ACCESS field of
SRIO Registers SPn_ERR_CAPT_DBG1 224 SPn_ERR_CAPT_DBG2 225 SPn_ERR_CAPT_DBG3 226 SPn_ERR_CAPT_DBG4 227 SPn_ERR_DET 219 SPn_ERR_RATE 228 SPn_ERR_STAT 203 SPn_ERR_THRESH 229 SPn_LM_REQ 200 SPn_LM_RESP 201 SPn_MULT_EVNT_CS 239 SPn_RATE_EN 221 SPn_RST_OPT 235 SPn_SILENCE_TIMER 238 src_id field of RX buffer descriptor 47 SRC_OP 188 SRIO peripheral component block diagram 26 data flow overview 21 emulation halt behavior 74 initialization example 77 packets 22 packet types 25 peripheral block diagram 21 pins/diffe
SRIO Registers transmitter enabling for SERDES macro introduction 33 transmitter enable bit 129 transport error handling and logging 83 transport layer content in SRIO data stream 22 definition 16 in Load/Store module data flow diagram 39 transport type field for message reception 179 TRA.
SRIO Registers Xoff 65 SPRUE13A – September 2006 Submit Documentation Feedback Xon 65 Index 255
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
