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TMS320C6457 DSP

Turbo-Decoder Coprocessor 2 (TCP2)

User's Guide

Literature Number: SPRUGK1

March 2009

Summary of content (79 pages)

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TMS320C6457 DSP Turbo-Decoder Coprocessor 2 (TCP2) User's Guide Literature Number: SPRUGK1 March 2009
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SPRUGK1 – March 2009 Submit Documentation Feedback
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Contents Preface ........................................................................................................................................ 8 1 Features.............................................................................................................................. 9 2 Introduction ....................................................................................................................... 10 3 Overview ....................................................................
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www.ti.com 8 Architecture ....................................................................................................................... 59 8.1 9 10 11 12 13 4 Sub-block and Sliding Window Segmentation ....................................................................... 60 ............................................................................ ............................................................................ 8.4 Added Features ..............................................
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www.ti.com List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 3GPP and IS2000 Turbo-Encoder Block Diagram ..................................................................... 3GPP and IS2000 Turbo-Decoder Block Diagram..................................................................... TCP2 Block Diagram ..........................................................................................
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www.ti.com 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 6 TCP2 Endian Register (TCPEND) ....................................................................................... TCP2 Error Register (TCPERR).......................................................................................... TCP2 Status Register (TCPSTAT) ...............................................................................
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www.ti.com List of Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Frame Sizes for Standalone (SA) Mode and Shared-Processing (SP) Mode...................................... Interleaver Data............................................................................................................. TCP2 Registers .............................................................................................................
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Preface SPRUGK1 – March 2009 Read This First About This Manual Channel decoding of high bit-rate data channels found in third-generation (3G) cellular standards requires decoding of turbo-encoded data. The turbo-decoder coprocessor (TCP2) in some of the digital signal processors (DSPs) of the TMS320C6000™ DSP family has been designed to perform this operation for IS2000 and 3GPP wireless standards. This document describes the operation and programming of the TCP2 for the TMS320C6457 DSPs.
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User's Guide SPRUGK1 – March 2009 TMS320C6457 Turbo-Decoder Coprocessor 2 Channel decoding of high bit-rate data channels found in third-generation (3G) cellular standards requires decoding of turbo-encoded data. The turbo-decoder coprocessor (TCP2) in some of the digital signal processor (DSPs) of the TMS320C6000E DSP family has been designed to perform this operation for IS2000 and 3GPP wireless standards. This document describes the operation and programming of the TCP2.
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Introduction 2 www.ti.com Introduction Encoding is done as shown in Figure 1. The 3GPP and IS2000 turbo encoders employ two recursive, systematic, convolutional (RSC) encoders connected in parallel, with an interleaver (the turbo interleaver) preceding the second recursive convolutional encoder. The two recursive convolutional codes are called the constituent encoders of the turbo code and have a constraint length K = 4. Figure 1.
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Overview www.ti.com uses the corresponding estimates from the other decoder as a priori likelihood. The a priori information is seen as beforehand knowledge, meaning that some messages are more likely to occur than others. A posteriori information adds to the a priori information the knowledge gained by the decoding. The uncoded information bits (corrupted by the noisy channel) are available to each decoder to initialize the a priori likelihoods.
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Standalone (SA) Mode www.ti.com Figure 3. TCP2 Block Diagram TCP2_INT TCPXEVT TCPREVT 32-bit configuration bus 64-bit EDMA3 bus CPU interrupt generation REVT/XEVT generation TCP2 control EDMA3 I/F unit Memory block Processing unit Turbo-decoder coprocessor (TCP2) Table 1.
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Standalone (SA) Mode www.ti.com One iteration of turbo decoding consists of 2 MAPs processing, the first MAP with the initial switch position (as shown in Figure 4), the second MAP with the other position of the switch. After each MAP, a stopping test can be performed based on the following methods. These tests are user configurable.
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Standalone (SA) Mode www.ti.com Figure 5. Systematic/Parity Data for Rates 1/2, 1/3, 1/4, 1/5, and 3/4 63:62 61:56 55:50 49:44 43:38 37:32 31:30 29:24 23:18 17:12 11:6 5:0 RSVD SP9 SP8 SP7 SP6 SP5 RSVD SP4 SP3 SP2 SP1 SP0 Figure 6.
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Standalone (SA) Mode www.ti.com Figure 11. EN = 0 (Big-Endian Mode) Rate = 1/4 SP4 B0' SP3 0 SP4 B2' SP3 0 Word N SP2 B0 Word N+2 SP2 B2 SP1 A0 SP0 X0 SP9 B1' SP8 A1' SP1 A2 SP0 X2 SP9 B3' SP8 A3' Word N+1 SP7 0 Word N+3 SP7 0 SP6 A1 SP5 X1 SP6 A3 SP5 X3 SP1 A0 SP0 X0 SP1 A2 SP0 X2 SP6 A1 SP5 X1 SP6 A3 SP5 X3 SP1 A0 SP0 X0 SP1 0 SP0 X2 SP1 0 SP0 X2 Figure 12.
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Standalone (SA) Mode www.ti.com Figure 15. Rate 3/4 EN = 0 (Big-Endian Mode) Rate = 3/4 Word N SP4 0 SP3 0 SP2 0 Word N+1 SP1 A0 SP0 X0 SP9 0 SP8 0 Word N+2 SP4 0 SP3 0 SP2 0 4.1.2 SP3 0 SP2 0 SP6 0 SP5 X1 SP6 0 SP5 X3 SP6 0 SP5 X5 Word N+3 SP1 0 SP0 X2 SP9 0 SP8 A3' Word N+4 SP4 0 SP7 0 SP7 0 Word N+5 SP1 0 SP0 X4 SP9 0 SP8 0 SP7 0 Interleaver Indexes Each index is a 15-bit value being effectively saved as 16 bits right-justified.
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www.ti.com Standalone (SA) Mode The CRC-based stopping criterion can be used by setting the CRC polynomial length (CRCLEN) and the number of CRC iterations required to pass CRCITERPASS. After each iteration, hard decisions are computed and a CRC is performed. The CRC polynomial is a programmable 32-bit number.
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Shared-Processing (SP) Mode www.ti.com The CRC will process one sub-block at time using the data stored from the previous sub-block. The decision bit will be used by a CRC block. After all sub-blocks have been processed, the CRC bits in the CRC block are checked and compared with the last crc_length bits of the frame. If they all match, then the CRC passes. 4.4.3 Parameter Termination The parameters min_iter and max_iter need to be set prior to decode.
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Shared-Processing (SP) Mode www.ti.com Figure 16. Shared-Processing (SP) Mode Block Diagram A for MAP 1 and A’ for MAP2 MAP decoder unit B for MAP1 and B’ for MAP2 (only rate 1/4) X for MAP1 or X’ for MAP2 EXT1: extrinsics after MAP1 EXT2: extrinsics after MAP2 EXT1,2 The shared-processing mode allows the DSP/TCP2 system to support frames strictly larger than 20730. The DSP breaks the large frame into 2 or more smaller frames of 20480 or less. Each frame is called a subframe.
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Shared-Processing (SP) Mode www.ti.com Figure 17. Subframe Equations ǒ Num Subframe + CEIL Size Block SizeMAX_Subframe ǒ256 SizeNum Ǔ Block Size Subframe + CEIL Subframe whileǒ Size Block u SizeMAX_Subsystem Ǔ Ǔ 256 { Size Block + SizeBlock * SizeSubframe } if(SizeBlock u 128) Size Last_Subframe + SizeBlock if(SizeBlock v 128) { Num Subframe + Num Subframe * 1 Size Last_Subframe + SizeBlock ) SizeMAX_Subframe } Figure 18.
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Shared-Processing (SP) Mode www.ti.com Each sub-frame is independent of each other. There are three types of sub-frames. The first sub-frame starts the trellis from the zero state. The last sub-frame ends the trellis from a known state. The remaining middle subframes do not start or end from a known state. The EDMA3 transfers ACNT*BCNT number of bytes in A-Sync Mode and ACNT*BCNT*CCNT number of bytes in AB-Sync Mode. The total number of bytes for both modes should be a multiple of 8.
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Shared-Processing (SP) Mode www.ti.com Figure 19. TCP2 Shared Processing Block Diagram MAP 1: Parity A or MAP 2: Parity A’ MAP 1: Parity B or MAP 2: Parity B’ Void input MAP decoder unit MAP 1: Systemic or MAP 2: Interleaved (systematic) MAP 1: De−interlaced (Apriori 2) or MAP 2: Interleaved (Apriori 1) MAP 1: Apriori 1 or MAP 2: Apriori 2 5.1 Extrinsic saved as apriori Input Data Format 5.1.
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Shared-Processing (SP) Mode www.ti.com Figure 23. EN = 1 (Little-Endian Mode) Rate = 1/3 SP9 0 SP8 A1' SP9 0 SP8 A3' Word N+1 SP7 0 Word N+3 SP7 0 SP6 A1 SP5 X1 SP4 0 SP3 A0' SP6 A3 SP5 X3 SP4 0 SP3 A2' Word N SP2 0 Word N+2 SP2 0 SP1 A0 SP0 X0 SP1 A2 SP0 X2 SP6 A1 SP5 X1 SP6 A3 SP5 X3 SP1 A0 SP0 X0 SP1 A2 SP0 X2 SP6 A1 SP5 X1 SP6 A3 SP5 X3 SP1 A0 SP0 X0 SP1 A2 SP0 X2 Figure 24.
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Shared-Processing (SP) Mode www.ti.com Figure 28. EN = 0 (Big-Endian Mode) Rate = 1/5 SP4 B0' SP3 A0' SP4 B2' SP3 A2 Word N SP2 B0 Word N+2 SP2 B2 SP1 A0 SP0 X0 SP9 B1' SP8 A1' SP1 A2 SP0 X2 SP9 B3' SP8 A3' Word N+1 SP7 B1 Word N+3 SP7 B3 SP6 A1 SP5 X1 SP6 A3 SP5 X3 SP1 A0 SP0 X0 SP1 0 SP0 X2 SP1 0 SP0 X2 SP6 0 SP5 X1 SP6 0 SP5 X3 SP6 0 SP5 X5 Figure 29.
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Registers www.ti.com 6 Registers The TCP2 contains several memory-mapped registers accessible via the CPU, QDMA, and EDMA3. A peripheral-bus access is faster than an EDMA3-bus access for isolated accesses (typically when accessing control registers). EDMA3-bus accesses are intended to be used for EDMA3 transfers and are meant to provide maximum throughput to/from the TCP2.
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Registers www.ti.com Table 4.
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Registers www.ti.com 6.1 Peripheral Identification Register (PID) The peripheral identification register (PID) is a constant register that contains the ID and ID revision number for that peripheral. The PID stores version information used to identify the peripheral. All bits within this register are read-only (writes have no effect) meaning that the values within this register should be hard-coded with the appropriate values and must not change from their reset state.
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Registers 6.2 www.ti.com TCP2 Input Configuration Register 0 (TCPIC0) The TCP2 input configuration register 0 (TCPIC0) is shown in Figure 33 and described in Table 6. TCPIC0 configures the TCP. Figure 33.
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Registers www.ti.com 6.3 TCP2 Input Configuration Register 1 (TCPIC1) The TCP2 input configuration register 1 (TCPIC1) is shown in Figure 34 and described in Table 7. TCPIC1 configures the TCP. Figure 34. TCP2 Input Configuration Register 1 (TCPIC1) 31 23 22 16 15 0 Reserved R Reserved R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7.
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Registers 6.5 www.ti.com TCP2 Input Configuration Register 3 (TCPIC3) The TCP2 input configuration register 3 (TCPIC3) is shown in Figure 36 and described in Table 9. TCPIC3 informs the TCP2 on the EDMA3 data flow segmentation. Figure 36.
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Registers www.ti.com 6.6 TCP2 Input Configuration Register 4 (TCPIC4) The TCP2 input configuration register 4 (TCPIC4) is shown in Figure 37 and described in Table 10. TCPIC4 informs the TCP2 on the EDMA3 data flow segmentation. Figure 37. TCP2 Input Configuration Register 4 (TCPIC4) 31 16 Reserved R/W-0 15 13 12 8 7 6 5 0 Reserved CRCITERPASS Reserved CRCLEN R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 10.
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Registers 6.7 www.ti.com TCP2 Input Configuration Register 5 (TCPIC5) The TCP2 input configuration register 5 (TCPIC5) is shown in Figure 38 and described in Table 11. TCPIC5 provides the 32-bit CRC Polynomial to TCP2. Figure 38. TCP2 Input Configuration Register 5 (TCPIC5) 31 0 CRCPOLY R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 11. TCP2 Input Configuration Register 5 (TCPIC5) Field Descriptions Bit 31-0 Field Value CRCPOLY 0 Description CRC polynomial.
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Registers www.ti.com 6.9 TCP2 Input Configuration Register 6 (TCPIC6) The TCP2 input configuration register 6 (TCPIC6) is shown in Figure 39 and described in Table 13. TCPIC6 sets the tail bits used by the TCP. Figure 39. TCP2 Input Configuration Register 6 (TCPIC6) 31 18 17 0 Reserved TAIL1 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 13.
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Registers www.ti.com 6.10 TCP2 Input Configuration Register 7 (TCPIC7) The TCP2 input configuration register 7 (TCPIC7) is shown in Figure 40 and described in Table 14. TCPIC7 sets set the tail bits used by the TCP. Figure 40. TCP2 Input Configuration Register 7 (TCPIC7) 31 18 17 0 Reserved TAIL2 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 14.
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Registers www.ti.com 6.11 TCP2 Input Configuration Register 8 (TCPIC8) The TCP2 input configuration register 8 (TCPIC8) is shown in Figure 41 and described in Table 15. TCPIC8 sets the tail bits used by the TCP. Figure 41. TCP2 Input Configuration Register 8 (TCPIC8) 31 18 17 0 Reserved TAIL3 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 15.
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Registers www.ti.com 6.12 TCP2 Input Configuration Register 9 (TCPIC9) The TCP2 input configuration register 9 (TCPIC9) is shown in Figure 42 and described in Table 16. TCPIC9 sets the tail bits used by the TCP. Figure 42. CP2 Input Configuration Register 9 (TCPIC9) 31 18 17 0 Reserved TAIL4 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 16.
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Registers www.ti.com 6.13 TCP2 Input Configuration Register 10 (TCPIC10) The TCP2 input configuration register 10 (TCPIC10) is shown in Figure 43 and described in Table 17. TCPIC10 sets the tail bits used by the TCP. Figure 43. TCP2 Input Configuration Register 10 (TCPIC10) 31 18 17 0 Reserved TAIL5 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 17.
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Registers www.ti.com Figure 44. TCP2 Input Configuration Register 11 (TCPIC11) 31 18 17 0 Reserved TAIL6 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 18. TCP2 Input Configuration Register 11 (TCPIC11) Field Descriptions Bit Field 31-18 Reserved 17-0 TAIL6 • • • • • 38 Value 0 0-FFFF FFFFh Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Tail bit.
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Registers www.ti.com 6.15 TCP2 Input Configuration Register 12 (TCPIC12) The TCP2 input configuration register 12 (TCPIC12) is shown in Figure 45 and described in Table 19. Figure 45. TCP2 Input Configuration Register 12 (TCPIC12) 31 24 23 0 Reserved EXT_SCALE_0_3 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 19.
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Registers www.ti.com 6.17 TCP2 Input Configuration Register 14 (TCPIC14) The TCP2 input configuration register 14 (TCPIC14) is shown in Figure 47 and described in Table 21. Figure 47. TCP2 Input Configuration Register 14 (TCPIC14) 31 24 23 0 Reserved EXT_SCALE_8_11 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 21.
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Registers www.ti.com 6.18 TCP2 Input Configuration Register 15 (TCPIC15) The TCP2 input configuration register 15 (TCPIC15) is shown in Figure 48 and described in Table 22. Figure 48. TCP2 Input Configuration Register 15 (TCPIC15) 31 24 23 0 Reserved EXT_SCALE_12_15 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22.
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Registers www.ti.com 6.19 TCP2 Output Parameter Register 0 (TCPOUT0) The TCP2 output parameter register 0 (TCPOUT0) is shown in Figure 49 and described in Table 24. Figure 49. TCP2 Output Parameter Register 0 (TCPOUT0) 31 29 28 24 23 20 19 0 Reserved FINAL_ITER Reserved SNR_M1 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 24.
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Registers www.ti.com 6.21 TCP2 Output Parameter Register 2 (TCPOUT2) The TCP2 output parameter register 2 (TCPOUT2) is shown in Figure 51 and described in Table 26. Figure 51. TCP2 Output Parameter Register 2 (TCPOUT2) 31 16 15 0 CNT_RE_MAP1 CNT_RE_MAP0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 26.
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Registers www.ti.com 6.23 TCP2 Endian Register (TCPEND) The TCP2 endian register (TCPEND) is shown in Figure 53 and described in Table 28. TCPEND should only be used when the DSP is set to big-endian mode. Figure 53. TCP2 Endian Register (TCPEND) 31 8 Reserved R/W-0 7 2 1 0 Reserved ENDIAN_ EXTR ENDIAN_ INTR R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 28.
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Registers www.ti.com 6.24 TCP2 Error Register (TCPERR) The TCP2 error register (TCPERR) is shown in Figure 54 and described in Table 29. In case of an error, the coprocessor sends an interrupt to the C6457 CPU. The following errors are feedback in the error word. Figure 54.
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Registers www.ti.com Table 29. TCP2 Error Register (TCPERR) Field Descriptions (continued) Bit 4 Field 3 Reserved 2 P 1 Value SF Description Subframe length. 0 No error 1 Subframe length > 5114 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Prolog length. 0 No error 1 Prolog length < 4 or> 48 F Frame length.
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Registers www.ti.com 6.25 TCP2 Status Register (TCPSTAT) The TCP2 status register (TCPSTAT) is shown in Figure 55 and described in Table 30. Figure 55.
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Registers www.ti.com Table 30. TCP2 Status Register (TCPSTAT) Field Descriptions (continued) Bit Field 7 REXT 6 5 4 3 2 1 0 48 Value Defines if the TCP2 is waiting for extrinsic memory 0 data to be read. 0 Not waiting 1 Waiting for RAM extrinsic memory 0 to be read WAP Defines if the TCP2 is waiting for a extrinsic memory 1 data to be written.
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Registers www.ti.com 6.26 TCP2 Emulation Register (TCPEMU) In emulation mode, the access to TCP2 memories can be done in read or write. TCP2 supports emulation mode. Emulation support helps in system debug. Emulation modes are achieved with the programmable SOFT and FREE bits in the TCP2 Emulation Register (TCPEMU) at the configuration bus address 0x00070. The TCP2 emulation register (TCPEMU) is shown in Figure 56 and described in Table 31. Figure 56.
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Endianness www.ti.com The TCP2 is halted (or paused) after processing the ongoing frame. Any current frame processing must complete. Sync vents for the new frame will be hold until TCP_EMUSUSP is released. The TCP2 is restarted from the paused state and begins the next frame operations. In TCP_STATE = 14, the TCP_EMUSUSP will have no effect. The TCP2 will go to the next state (TCP_STATE=0) and then the emususp will be processed.
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Endianness www.ti.com Figure 61. Data Memory 63:62 RSVD 61:56 SP9 55:50 SP8 49:44 SP7 43:38 SP6 37:32 SP5 31:30 RSVD 29:24 SP4 23:18 SP3 17:12 SP2 11:6 SP1 5:0 SP0 Figure 62.
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Endianness www.ti.com Figure 67. EN = 0 (Big-Endian Mode) Rate = 1/4 SP4 B0' SP3 0 SP4 B2' SP3 0 Word N SP2 B0 Word N+2 SP2 B2 SP1 A0 SP0 X0 SP9 B1' SP8 A1' SP1 A2 SP0 X2 SP9 B3' SP8 A3' Word N+1 SP7 0 Word N+3 SP7 0 SP6 A1 SP5 X1 SP6 A3 SP5 X3 SP1 A0 SP0 X0 SP1 A2 SP0 X2 SP6 A1 SP5 X1 SP6 A3 SP5 X3 SP1 A0 SP0 X0 SP1 0 SP0 X2 SP1 0 SP0 X2 Figure 68.
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Endianness www.ti.com Figure 71. EN = 0 (Big-Endian Mode) Rate = 3/4 Word N SP4 0 SP3 0 SP2 0 Word N+1 SP1 A0 SP0 X0 SP9 0 SP8 0 Word N+2 SP4 0 SP3 0 SP2 0 7.1.1 SP3 0 SP2 0 SP6 0 SP5 X1 SP6 0 SP5 X3 SP6 0 SP5 X5 Word N+3 SP1 0 SP0 X2 SP9 0 SP8 A3' Word N+4 SP4 0 SP7 0 SP7 0 Word N+5 SP1 0 SP0 X4 SP9 0 SP8 0 SP7 0 Hard Decision Data 1. OUT_ORDER = 0 EN = 1 (Little-Endian Mode) OUT_ORDER = 0 results in ordering the hard decision data from 0 to 31 in the 32-bit word output.
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Endianness www.ti.com Figure 77. Destination of Endianness Manager (OUT_ORDER = 0) 63 62 32 31 1 0 Stage N - 32 Stage N - 33 Stage N - 63 Stage N Stage N - 30 Stage N - 31 4. OUT_ORDER = 1 EN = 1 (Little-Endian Mode) Figure 78. Trellis Stage Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 1) 63 62 32 31 1 0 Stage N Stage N-1 Stage N - 31 Stage N - 32 Stage N - 62 Stage N - 63 Figure 79.
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Endianness www.ti.com Figure 82. TCP_ENDIAN Register 31 16 Reserved R/W 15 2 1 0 Reserved ENDIAN_ EXTR ENDIAN_ INTR R/W R/W R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 33. TCP_ENDIAN Programming Register Data Native Format DSP Memory Format TCP_ENDIAN Interleaver Indexes 16 bits (15 bits right justified) 16 bits NATIVE ENDIAN_INTR = 1 Packed on 32 bits ENDIAN_INTR = 0 8 bits NATIVE ENDIAN_EXTR = 1 Packed on 32 bits ENDIAN_EXTR = 0 Extrinsic Data 7.
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Endianness www.ti.com Figure 83. Interleaver Indexes in DSP Memory (ENDIAN_INTR = 1) Endian_Intr=1 Memory 63 0 INTER0 INTER3 INTER1 Base 6 Endianness manager INTER2 INTER2 INTER3 Base 4 INTER3 INTER1 Kernel INTER2 Base 2 EDMA3 INTER1 INTER0 INTER0 Base 0 TCP 63 0 They have to be swapped as described in Figure 84 and Figure 85. Figure 84. Data Source - EDMA3 (ENDIAN_INTR = 1) 63 48 47 INTER0 32 31 INTER1 16 15 1 INTER2 INTER3 Figure 85.
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Endianness www.ti.com Figure 87. Data Source - EDMA3 (ENDIAN_INTR = 0) 63 48 47 32 INTER1 31 INTER0 16 15 1 INTER3 INTER2 Figure 88. Data Destination - Kernel (ENDIAN_INTR = 0) 63 48 47 32 INTER3 7.1.4 31 INTER2 16 15 1 INTER1 INTER0 Extrinsic Data Table 37. Extrinsic Data 7.1.4.
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Endianness www.ti.com Figure 90. Data Source - Kernel (ENDIAN_EXTR = 1) 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 EXT7 EXT6 EXT5 EXT4 EXT3 EXT2 EXT1 EXT0 Figure 91.
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Architecture www.ti.com 7.1.4.2 ENDIAN_EXTR = 0 If ENDIAN_EXTR = 0, data are saved in word format (32 bits) in the DSP (see Table 39). Table 39. Extrinsic in DSP Memory (ENDIAN_EXTR = 0) Address (hex bytes) Data Base EXT3 Base + 1 EXT2 Base + 2 EXT1 Base + 3 EXT0 Base + 4 EXT7 Base + 5 EXT6 Base + 6 EXT5 Base + 7 EXT4 Figure 92.
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Architecture www.ti.com Figure 95. MAP Unit Block Diagram Data from memory Beta Beta memory Extrinsic Scratch memory Extrinsic signals Alpha The TCP2 can enable or disable the max star function by modifying the E_MAX_STAR bit in the TCPIC3 register. • E_MAX_STAR = 0 = Enable max star • E_MAX_STAR = 1 = Disable max star Log-map algorithm is implemented in a highly paralleled manner using the sliding window principle.
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Architecture www.ti.com Figure 96. Sliding Windows and Sub-blocks Segmentation (Example with 5 Sub-blocks, frame length ≤20730) Frame or subframe (length < 5114) First subblock Prolog Middle subblock Middle subblock Only used in SP mode. in SA mode, start from known state 0 Middle subblock Last subblock Prolog Subblock : 1, 2 or 4 sliding windows Sliding Window Only used in SP mode subframes (not last).
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Architecture www.ti.com Figure 97. Shared Processing Subframe Segmentation (Example with 5 Subframes) Shared-processing frame (length > 20730) First subframe Prolog Middle subframe Middle subframe Must point to valid address Middle subframe Last subframe Subframe (length ≤ 20480) 8.
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Architecture www.ti.com Figure 98. Example R Formula R MAX + 128 if(N v 128) NSW + 1, R + N ELSE NSW + 2 IFǒ N SW + 2 Ǔ { whileǒǒ N SB R NSW * N Ǔ w (R * 48)Ǔ { WIN_SIZE + CEIL ƪNńN SWƫ N SB + CEIL R + IFǒ R ƪWIN_SIZE ƫ R MAX WIN_SIZE NSB N SB t WIN_SIZE ǓR ) ) R MAX + RMAX * 1 } N SW + NSW * 1 This computation should be done by the DSP CPU. It should be noted that a 1 must be subtracted from the calculated R value prior to writing to TCPIC1. Note: 8.4 8.4.
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Programming 8.4.2 www.ti.com Input Sign The TCP assumes that the encoded bits are converted into signed binary symbols using the following mapping: 0 → -1, 1 → +1 and scaled by -2*a/Σ2 where a is the fading factor and Σ is the noise variance. Many receivers may perform this scaling without applying the -1 factor. With TCP, this requires the DSP to perform the -1 multiplication as the TCP expects this scaling.
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Programming www.ti.com Note that several user channels can be programmed prior to starting the TCP2. Table 42.
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Programming 9.2 www.ti.com Programming Standalone (SA) Mode Table 42 highlights the required EDMA3 resources to perform a standalone (SA) mode decoding. Each set of EDMA3 parameters uses the EDMA3 linking capabilities. Section 9.2.1 details the EDMA3 transfers programming and Section 9.2.2 details the input parameters programming. Any notification mechanism to flag that a user-channel has just been decoded is left to you.
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Programming www.ti.com – TCINTEN = 0 (Transfer complete interrupt is disabled) – TCC = 1 to 63 (Transfer Complete Code) – TCCMODE = 0 (Normal Completion) – FWID = Don't care – STAT = 0 (Entry is updated as normal) – SYNCDIM = 0 (AB-Sync, Each event triggers the transfer of BCNT arrays of ACNT elements.) – DAM = 0 (Dst addressing within an array increments. Dst is not a FIFO.) – SAM = 0 (Src addressing within an array increments. Source is not a FIFO.
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Programming • • • • • • • www.ti.com SRCBIDX = 0 (Source 2nd Dimension Index) DSTBIDX = 0 (Destination 2nd Dimension Index SRCCIDX = 0 (Source 3rd Dimension Index) DSTCIDX = 0 (Destination 3rd Dimension Index) CCNT = 1 (No of frames in a block) BCNTRLD: Don't care LINK ADDRESS: See cases 1 and 2 below Upon completion, this EDMA3 transfer is linked to one of the following: 1. The EDMA3 input configuration parameters transfer parameters of the next user-channel, if there is one ready to be decoded 2.
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Programming www.ti.com 3. Null EDMA3 transfer parameters (with all zeros), if there are no more user channels ready to be decoded and the OUTF bit is cleared. 9.2.1.5 Output Parameters Transfer This EDMA3 transfer is optional and depends on the OUTF bit in the TCP2 input configuration register 0 (TCPIC0). This EDMA3 transfer is a TCPREVT frame-synchronized transfer.
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Programming www.ti.com The minimum number of iterations (MINIT bits in TCPIC3) should be selected as a function of the overall system performance (minimum iterations 1 to 31) when SNR stopping criteria is used. The INPUTSIGN bit can be enabled or disabled in TCPIC3 (0 = Use channel input data as is, 1 = multiply channel input data by -1). The OUTORDER bit can be enabled or disabled in TCPIC3 (0 = output bit ordering from 0 to 31, 1 = output bit ordering from 31 to 0).
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Programming www.ti.com 9.3.1 EDMA3 Programming 9.3.1.1 Input Configuration Parameters Transfer This EDMA3 transfer to the input configuration parameters is a 16-word TCPXEVT frame-synchronized transfer.
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Programming • • • • • • • • • • www.ti.
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Programming www.ti.com 1. The EDMA3 input configuration parameters transfer parameters of the next user-channel MAP, if there is one ready to be decoded. 2. Dummy EDMA3 transfer parameters, if there are no more user channels LOG-MAP ready to be decoded. 9.3.1.4 Extrinsics Transfer This EDMA3 transfer to the extrinsics buffer is a TCPREVT frame-synchronized transfer.
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Output Parameters • • • • www.ti.com The EMAXSTR bit can be enabled or disabled in TCPIC3, 0 = max star disabled (enable Max Log-MAP, 1 = max star enabled (enable log MAP)). The minimum number of iterations (MINIT bits in TCPIC3) should be selected as a function of the overall system performance (minimum iterations 1 to 31). The INPUTSIGN bit can be enabled or disabled in TCPIC3 (0 = Use channel input data as is, 1 = multiply channel input data by -1).
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Debug Mode: Pause After Each Map www.ti.com Figure 101.
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Errors and Status 13.1.2 www.ti.com Unexpected Frame Length: F The F bit is set to 1 if the programmed frame length is strictly smaller than 40 or is strictly greater than 20730 for standalone mode. The F bit is set to 1 if the programmed frame length has the following values for shared processing mode: 1. Frame length < 256 or frame length > 20480 or (frame length)%256 != 0 if opmode = 1 or 2. 2. Frame length < 128 or frame length > 20480 if opmode = 3. 13.1.
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Errors and Status www.ti.com 13.1.10 Unexpected Max and Min Iterations: MAXMINITER The MAXMINITER bit is set to 1 if the minimum iterations are greater than the maximum iterations. 13.2 Status The TCP2 status register (TCPSTAT) reflects the state of the TCP2. 13.2.1 TCP2 Decoder Status: dec_busy The dec_busy is set to 0 if the MAP decoder is in state 0. The dec_busy is set to 1 if the MAP decoder is in states 1 to 8. 13.2.
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Errors and Status www.ti.com 13.2.12 TCP2 Active State Status: Active_state The Active_state indicates active MAP decoder state. 13.2.13 TCP2 Active Iteration Status: Active_iter The Active_iter indicates active TCP2 iteration. 13.2.14 TCP2 SNR Status: snr_exceed The snr_exceed indicates failed or passed MAPs with respect to SNR. 13.2.15 TCP2 CRC Status: Crc_pass The Crc_pass bit is set to 1 when the CRC has passed. 13.2.
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