User's Manual

Functional Description

SLES140A—March 2007 TVP5147M1PFP

2.11.81 FIFO Read Data Register

Subaddress E2h

Read only

7 6 5 4 3 2 1 0

FIFO read data [7:0]

FIFO read data [7:0]: This register is provided to access VBI FIFO data through the I

C interface. All forms

of teletext data come directly from the FIFO, while all other forms of VBI data can be programmed to come

from registers or from the FIFO. If the host port is to be used to read data from the FIFO, then bit 0 (host access

enable) in the VDP FIFO output control register at subaddress C0h must be set to 1 (see Section 2.11.71).

2.11.82 VBUS Address Access Register

Subaddress E8h E9h EAh

Default 00h 00h 00h

Subaddress 7 6 5 4 3 2 1 0

E8h VBUS address [7:0]

E9h VBUS address [15:8]

EAh VBUS address [23:16]

VBUS address [23:0]: VBUS is a 24-bit wide internal bus. The user needs to program in these registers the

24-bit address of the internal register to be accessed via host port indirect access mode.

2.11.83 Interrupt Raw Status 0 Register

Subaddress F0h

Read only

7 6 5 4 3 2 1 0

FIFO THRS TTX WSS VPS VITC CC F2 CC F1 Line

FIFO THRS: FIFO threshold passed, unmasked

0 = Not passed

1 = Passed

TTX: Teletext data available unmasked

0 = Not available

1 = Available

WSS: WSS data available unmasked

0 = Not available

1 = Available

VPS: VPS data available unmasked

0 = Not available

1 = Available

VITC: VITC data available unmasked

0 = Not available

1 = Available

CC F2: CC field 2 data available unmasked

0 = Not available

1 = Available