Specifications

Table Of Contents

Cinterion

EHS6-A Hardware Interface Overview

2.1 Application Interface

 EHS6-A_HIO_v04.000 2019-03-05

Confidential / Preliminary

Page 17 of 40

2.1.8 I

C Interface

C is a serial, 8-bit oriented data transfer bus for bit rates up to 400kbps in Fast mode. It con-

sists of two lines, the serial data line I2CDAT and the serial clock line I2CCLK. The module acts

as a single master device, e.g. the clock I2CCLK is driven by the module. I2CDAT is a bi-direc-

tional line. Each device connected to the bus is software addressable by a unique 7-bit ad-

dress, and simple master/slave relationships exist at all times. The module operates as master-

transmitter or as master-receiver. The customer application transmits or receives data only on

request of the module.

The I

C interface can be powered via the V180 line of EHS6-A. If connected to the V180 line,

the I

C interface will properly shut down when the module enters the Power Down mode.

Note: Good care should be taken when creating the PCB layout of the host application: The

traces of I2CCLK and I2CDAT should be equal in length and as short as possible.

2.1.9 SPI Interface

Four EHS6-A GPIO interface lines can be configured as Serial Peripheral Interface (SPI). The

SPI is a synchronous serial interface for control and data transfer between EHS6-A and the ex-

ternal application. Only one application can be connected to the SPI and the interface supports

only master mode. The transmission rates are up to 6.5Mbit/s. The SPI interface comprises the

two data lines MOSI and MISO, the clock line SPI_CLK a well as the chip select line SPI_CS.

2.1.10 HSIC Interface

The (USB) High Speed Inter Chip Interface can be used between the module and an external

application processor and is compliant to the High Speed USB 2.0 interface with 480Mbit/s.

The maximum distance between module processor and external application processor should

not exceed 100mm.

The HSIC interface comprises 6 lines:

• Two signal lines (strobe - HSIC_STRB - and data - HSIC_DATA) are used in a source syn-

chronous serial interface with a 240MHz clock to provide a 480Mbps USB interface.

The HSIC_STRB and HSIC_DATA lines are high-speed signals and should be routed as

50 impedance traces. The trace length of these signals should be balanced to minimize

timing skew and no longer as 100mm.

• Four signal lines for Link Power Management (LPM). For further power reduction, the USB

HSIC interface supports LPM according to the USB 2.0 standard. The LPM defines power

management states and mechanisms to affect state changes that are used by the

AP_WAKEUP and CP_WAKEUP signal lines to efficiently manage bus and system power.

To take advantage of the LPM feature, two further signals are needed to support power

management state transitions - the SUSPEND and HOST_ACTIVE signals.