Product Card
Table Of Contents
- Contents
- Tables
- Figures
- 0 Document History
- 1 Introduction
- 2 Product Concept
- 3 Application Connector Interface
- 3.1 Pin Assignments and Electrical Description
- 3.2 Characteristics
- 3.2.1 Power Supply and Ground
- 3.2.2 Control Signals
- 3.2.3 Tunable Antenna Interface
- 3.2.4 WWAN/WiFi Coexistence Control
- 3.2.5 Dynamic Power Reduction
- 3.2.6 USB Interface
- 3.2.7 PCI Express® Interface
- 3.2.8 SIM/UICC Interface
- 3.2.9 eUICC Interface
- 3.2.10 GPIO Interface
- 3.2.11 Status
- 3.2.12 Add-in Card Configuration Pins
- 4 Antenna Interface
- 5 Operation
- 6 Appendix
Cinterion
®
MV31-W Hardware Interface Description
5.5 Timing Sequence Requirement
75
t MV31-W_HID_v01.009a 2022-04-27
Public / Preliminary
Page 61 of 76
Figure 33: Modern Standby D3cold
• The Host enabled PCIe
®
reference clock and deasserts PERST# (drive high).
Host Device
De‐assert PERST# (drive high)
D0 / L0
Host wakeup condition
Enable PCIe ref
clock
Enable PCIe RC
hardware blocks
Wake up from
sleep mode
(if applicable)
In itialize th e PCIe
RC hardware
blocks
Vote not OK to
sleep
Enable LTSSM
Request IPA
resources (IPA
power mgmt)
Enable PCIe EP
hardware blocks
Init ialize t he PC I e
EP hardware
blocks
Restore MHI
MMIO registers
values
Link training
PCIe enumeration and configuration
Pre ‐requisites:
M‐State = M3
D‐ State = D3cold
L‐State = L3
DEVICE_WAKE mechanism = Disabled
Enable LTSSM