User Manual

Table Of Contents
Connector specifications
5-12 Confidential - For internal use 99-137719-D
5.5.4 Debug connector (FOR INTERNAL USE)
The pin numbers listed in the table below are defined by the figure below. Electrical
characteristics for the signal types are listed in Table 5-10 on page 5-15.
Figure 5-8: Pin allocation of debug connector
RM bottom view
Ref
CLK
Tx
Rx2 (IF)
Rx1
1B 1A
30B 30A
90
60
B2B
Connector
1B
1A
20B20A
Debug
Connector
Signal Description I/O Electrical Pin #
FPGA Debug
Debug_[1..20] FPGA Debug I/O 1.8V LVCMOS [20B..1B]
Debug_0 FPGA Debug I/O 1.8V LVCMOS 20A
UART for debug (modem)
Debug_UART1_RxD Received Serial Data In 3.3V TTL 5A
Debug_UART1_TxD Transmitted Serial Data Out 3.3V TTL 6A
Power Interface
3V3D 3.3V digital voltage for
reference use
Out 3.3 VDC 3A, 8A
GND Ground reference PWR GND 4A, 7A
NC for future use
NC[1-13] Not Connected N/A N/A 1A,2A, 9A..19A
Table 5-6: Debug connector — pin allocation
Note
The debug connector is intended for development purposes only and is not
mounted per default.