Data Sheet

Thundercomm TurboX C40x SOM Datasheet
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Figure 2-3. Power on Signal
Table 2-18. Power on interface definition
Pin Name PIN Location Voltage Type Description Notes
KPDPWR_N C6 V_INT DI Power-on trigger, level trigger (active low)
PON_1 C1 1.17V - 4.2V DI Level-high triggered power-on input (keep high)
2.3.13. Reset interface
Three stages are available for resetting.
 Stage 1 reset – software-configurable bark
PMIC generates interrupt, giving the QCS device the opportunity to fix the problem or gracefully reset the
system. Example events can cause a bark: over temperature indicates system is getting too hot. PMIC
watchdog indicates that it has not kicked.
 Stage 2 – software-configurable bite
If reset is ignored, PMIC will force a reset event (selectable by software).
 Stage 3 – hardware mandatory bite
The user can generate a mandatory reset by a long key press of KYPD_PWR.
Table 2-19. Reset interface definition
Pin Name PIN Location Voltage Type Description Notes
PM_RESIN_N C5 1.8V DI Power management reset in (active low)
KPDPWR_N C6 V_INT DI Long press to reset PMIC (active low)
These reset triggers each have individual debounce and delay timers. Their default values are 10.256 seconds
for stage 1 and 2 seconds for stage 2, respectively, and they share the stage 3 reset timer. Stage 1 and stage 2
timers run in series, and stage 3 timer runs independently (parallel) of stage 1 and stage 2 timers. If the stage
3 timer is set to a lower value than that of stage 1 and stage 2 combined, then the stage 3 reset happens first.
The stage 3 default value is 128 seconds.
nicholas.wang_thundercomm.com
2022-07-21 2:34:47 AM CST