Data Sheet

Thundercomm TurboX C40x SOM Datasheet
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3.10. SPI
The following are the SPI features and comparisons:
 Supports 4-bit (MISO, MOSI, CS, CLK) synchronous serial data link.
 Support for master-only mode, up to 50 MHz on all SPI interfaces.
 Master device initiates data transfers; Multiple slave devices are supported by using chip-selects.
 No explicit communication framing, error-checking, or defined data word lengths; The transfers are strictly
at the raw bit level.
 As an SPI master, the core supports several SPI system configurations (as defined by the SPI protocol).
Figure 3-5. SPI Master Timing Diagram
Table 3-17. SPI master timing characteristics
Parameter Description Min Typical Max Units
T SPI clock period: 50 MHz maximum 20 - - ns
t(ch) Clock high 9.0 - - ns
t(cl) Clock low 9.0 - - ns
t(mov) Master output valid -5.0 - 5.0 ns
t(mis) Master input setup 5.0 - - ns
t(mih) Master input hold 1.0 - - ns
T SPI clock period: 26 MHz maximum 38 - - ns
t(ch) Clock high 17 - - ns
t(cl) Clock low 17 - - ns
t(mov) Master output valid -5.0 - 5.0 ns
t(mis) Master input setup 5.0 - - ns
t(mih) Master input hold 1.0 - - ns
nicholas.wang_thundercomm.com
2022-07-21 2:34:47 AM CST