Data Sheet

THUNDERCOMM TurboX™ C40x SoM Datasheet
43
4.9 I2C
THE SoM I2C standards and exceptions:
Applicable standard
Feature exceptions
I²C Specification , version 5.0, October 2012
None
Table 4-10 I2C
4.10 SPI
The following are the SPI features and comparisons:
■ Supports 4‐bit (MISO, MOSI, CS, CLK) synchronous serial data link.
■ Support for master-only mode, up to 50 MHz on all SPI interfaces.
■ Master device initiates data transfers; Multiple slave devices are supported by using chip-selects.
■ No explicit communication framing, error-checking, or defined data word lengths; The transfers are strictly at the
raw bit level.
■ As an SPI master, the core supports several SPI system configurations (as defined by the SPI protocol).
SPI master timing diagram
SPI master timing characteristics at 50 MHz
Parameter
Description
Min
Typica
l
Max
Units
T
SPI clock period: 50 MHz maximum
20
-
-
ns
t(ch)
Clock high
9.0
-
-
ns
t(cl)
Clock low
9.0
-
-
ns
t(mov)
Master output valid
-5.0
-
5.0
ns
t(mis)
Master input setup
5.0
-
-
ns
t(mih)
Master input hold
1.0
-
-
ns
T
SPI clock period: 26 MHz maximum
38
-
-
ns
t(ch)
Clock high
17
-
-
ns