Users Manual

Table Of Contents

Thundercomm TurboX D845 System on Module

Data outputs are launched on the falling edge of the clock, and inputs data are captured on the rising edge

of the clock by the receiver.

I2S samples are 2’s complement values, and the MSB is transmitted first allowing the transmitter and

receiver to support different number of bits per sample.

The left channel is transmitted when the word select is low, and the right channel is transmitted when the

word select is high

Parameter

Comments

Min Typ Max Unit

Using internal SCK

Frequency –

– – 24.576 MHz

T Clock period –

40.69 – – ns

t(HC) Clock high –

0.45 × T – 0.55 × T ns

t(LC) Clock low –

0.45 × T – 0.55 × T ns

t(sr) SD and WS input setup time –

8.14 – – ns

t(hr) SD and WS input hold time –

0 – – ns

t(dtr) SD and WS output delay –

– – 6.10 ns

Using external SCK

Frequency – – – 24.576 MHz

T Clock period – 40.69 – – ns

t(HC) Clock high – 0.45 × T – 0.55 × T ns

t(LC) Clock low – 0.45 × T – 0.55 × T ns

t(sr) SD and WS input setup time – 8.14 – – ns

t(hr) SD and WS input hold time – 0 – – ns

t(dtr) SD and WS output delay – – – 6.10 ns

Table 5.11- 2 I2S Timing

5.11 I2C

The SOM I2C standards and exceptions:

Applicable standard Feature exceptions

I2C Specification, version 3.0

HS mode, slave mode, multi-master

mode, and 10-bit addressing are not

supported.

Table 5.12- 1 I2C

5.12 SPI

The SOM supports SPI standards as a master only.