User's Guide

LE920A4 HW User Guide Module Connections Doc#: 1VV0301261 LE920A4 LGA Pads Layout Rev. 4.7.1 Page 40 of 124 2019-11-21
LE920A4 LGA Pads Layout
Figure 2: LGA Pads Layout
zz A B C D E F G H J K L M N P R S T U V W X Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AS AT AU AV
0
GND
RESERV
ED
RESERV
ED
RESERV
ED
RESERV
ED
RFU GND GND GND GND GND GND GND GND GND GND GND GND GND RFU GND
1
GND
MIC2
_MT-
EAR2
_MT-
GND
TGPIO
_21
TGPI O
_22
GND GND
ANT
_GPS
GND GND GND GND ANT 1 GND GND GND ANT 2
RESERV
ED
ON
_OFF*
GND
2
MIC1
_MT-
MIC2
_MT+
EAR2
_MT+
RESERV
ED
RESERV
ED
RESERV
ED
GND GND GND
GPS_
LNA
_EN
GND GND GND GND GND GND GND GND GND
WCI_RX
D
RFU
3
RESERV
ED
MIC1
_MT+
GND
RESERV
ED
RESERV
ED
RESERV
ED
JTAG_T
ORIGIN
GND
RESERV
ED
RESERV
ED
GPS_PP
S
WiFi
_SDRST
_TGPIO
WiFi_SD
CMD_TG
PIO14
WiFi_SD
0_TGPI
O15
WiFi_SD
1_TGPI
O16
WiFi_SD
2_TGPI
O17
WiFi_SD
3_TGPI
O18
WiFi_SD
CLK_TG
PIO19
GND
WCI_TX
D
STAT
_LED
4
EAR1
_MT-
GND
RESERV
ED
RESERV
ED
RESERV
ED
RFU RFU RFU RFU RFU
RFCLK2
_QCA
WLAN_S
LEEP_C
LK
I2C_SDA
_AUX
I2C_SCL
_AUX
RESERV
ED
RESERV
ED
RESERV
ED
TGPIO
_20
GND GND RFU
5
RESERV
ED
EAR1
_MT+
ADC
_IN1
RESERV
ED
RESERV
ED
GND GND GND
6
GND GND
ADC
_IN2
MIC_BIA
S
LED_DR
V
GND GND RFU
7
RESERV
ED
SIMIN1 GND
ADC
_IN3
RFU GND GND GND
8
SIMVCC1 DVI_RX
eSIM
RST
ETH_RS
T_N
GND GND GND GND
RESET_
N
GND GND GND
9
RESERV
ED
SIMIO1
DVI
_TX
TGPIO
_01
GND GND GND
RESERV
ED
GND GND
ANT
_DIV 1
10
SIMCLK1
DVI
_CLK
TGPIO
_02
ETH_IN_
N
GND GND GND GND
SW_
RDY
GND GND GND
11
SGMII_R
X_P
SIM
RST1
DVI
_WAO
TGPIO
_03
GND GND GND
RESERV
ED
GND GND GND
12
GND
REF
_CLK
TGPIO
_04
MAC_
MDIO
GND GND GND GND SHDN GND GND GND
13
SGMII_R
X_M
GND
I2C
SDA
TGPIO
_05
RESERV
ED
GND GND
ANT
_DIV 2
14
HSIC_D
ATA
I2C
_SCL
TGPIO
_06
MAC_
MDC
JTAG_P
S_HOLD
GND GND GND
15
SGMII_T
X_P
GND SIMVCC2
HW_KE
Y
RESERV
ED
GND GND GND
16
HSIC_S
TB
SIMCLK2 SIMIO2
RESERV
ED
RESERV
ED
RESERV
ED
RESERV
ED
RESERV
ED
RESERV
ED
RESERV
ED
RESERV
ED
RESERV
ED
RESERV
ED
RESERV
ED
RESERV
ED
RESERV
ED
RESERV
ED
GND GND GND GND
17
SGMII_T
X_M
GND
SIM
RST2
VRTC
RESERV
ED
RESERV
ED
LED_DR
V_EN
VAUX/
PWR
MON
VMMC
MMC
_CD
MMC
_DAT3
MMC
_DAT0
MMC
_DAT2
MMC
_CLK
MMC
_DAT1
MMC
_CMD
GND GND VBATT
VBATT
_PA
VBATT
_PA
18
USB
_VBUS
SIMIN2 GND GND
TGPIO_
12
TGPIO_
11
SPI
_CS*
TGPIO
_07
GND GND GND
C105/
RTS*
C108/
DTR*
C109/
DCD
C107/
DSR*
C125/
RING*
GND GND VBATT
VBATT
_PA
GND
19
GND USB_ID
USB
_D+
USB
_D-
GND
SPI
_MOSI
SPI
_MISO
SPI
_CLK
TGPIO
_08
TGPIO
_09
TGPIO
_10
GND
TX
_AUX
RX
_AUX
C104/
RXD
C103/
TXD
C106/
CTS*
GND VBATT
VBATT
_PA
VBATT
_PA
20
GND
RESERV
ED
RESERV
ED
RESERV
ED
RESERV
ED
GND GND
RESERV
ED
RESERV
ED
RESERV
ED
RESERV
ED
RESERV
ED
RESERV
ED
RESERV
ED
RESERV
ED
RESERV
ED
RFU RFU VBATT
VBATT
_PA
GND
New xE920 (34 mm X 40 mm) Form Factor Pin MAP