User's Guide

LE920A4 HW User Guide Electrical Specifications
Doc#: 1VV0301261 Logic Level Specifications
Rev. 4.7.1 Page 42 of 124 2019-11-21
Logic Level Specifications
Unless otherwise specified, all the interface circuits of the module are 1.8V CMOS logic.
Only few specific interfaces (such as USIM and SD Card) are capable of dual voltage I/O.
The following tables show the logic level specifications used in the module’s interface
circuits. The data specified in the tables below is valid throughout all drive strengths and
the entire temperature ranges.
NOTE:
Do not connect the module’s digital logic signals directly to the OEM’s digital
logic signals with a level higher than 2.7V for 1.8V CMOS signals.
4.3.1. 1.8V Pads - Absolute Maximum Ratings
Table 11: Absolute Maximum Ratings - Not Functional
Parameter Min Max
Input level on any digital pin when on -0.3V +2.16V
Input voltage on analog pins when on -0.3V +2.16 V
4.3.2. 1.8V Standard GPIOs
Table 12: Operating Range – Interface Levels (1.8V CMOS)
Pad Parameter Min Max Unit Comment
VIH Input high level 1.25V -- [V]
VIL Input low level -- 0.6V [V]
VOH Output high level 1.4V -- [V]
VOL Output low level -- 0.45V [V]
IIL Low-level input leakage
current
-1 -- [uA] No pull-up
IIH
High-level input leakage
current
-- +1 [uA] No pull-down
RPU Pull-up resistance 30 390 [kΩ] See Note
RPD Pull-down resistance 30 390 [kΩ] See Note
Ci Input capacitance -- 5 [pF]
NOTE:
Pull-up and Pull-down resistance of GPIO5 is different from those mentioned
above.
GPIO5 pull resistance is specified as 10KΩ to 50KΩ.