Data Sheet

16
K019-CW43-DW datasheet_V1.6_15042020.doc | Shawn Xiao
Copyright © 2008-2020 | www.kertong.com.cn | rights reserved
7. Interface Timing Diagram
7.1
Power-up Sequence Timing Diagram
The module has signals that allow the host to control power consumption by enabling
or
disabling the Bluetooth, WLAN and internal regulator blocks. These signals are described
below.Additionally, diagrams are provided to indicate proper sequencing of the signals for
carious
operating states. The timing value indicated are minimum required values: longer
delays are
also acceptable.
※ WL_REG_ON: Used by the PMU to power up the WLAN section. When this pin is
high, the regulators are enabled and the WLAN section is out of reset. When this
pin is low the WLAN section is in reset.
※ BT_RST_N: Low asserting reset for Bluetooth only. This pin has no effect
on WLAN and does not control any PMU functions. This pin must be driven high or
low (not left floating).
WLAN=ON, Bluetooth=ON










