TOSHIBA Original CMOS 32-Bit Microcontroller TLCS-900/H1 Series TMP92CM22FG Semiconductor Company
Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”.
TMP92CM22 CMOS 32-Bit Microcontrollers TMP92CM22FG 1. Outline and Device Characteristics TMP92CM22 is high-speed advanced 32-bit microcontroller developed for controlling equipment, which processes mass data. TMP92CM22FG is a microcontroller, which has a high-performance CPU (900/H1 CPU) and various built-in I/Os. TMP92CM22F is housed in a 100-pin flat package.
TMP92CM22 (4) External memory expansion • Expandable up to 16 Mbytes (Shared program/data area) • Can simultaneously support 8-/16-bit width external data bus ･･･Dynamic data bus sizing • Separate bus system (5) Memory controller • Chip select output: 4 channels (6) 8-bit timers: 4 channels (7) 16-bit timers: 2 channels (8) General-purpose serial interface: 2 channels • UART/synchronous mode • IrDA (9) Serial bus interface: 1 channel • I2C bus mode • Clock synchronous mode (10) 10-bit AD co
TMP92CM22 PG0 to PG7 (AN0 to AN7) PG3 ( ADTRG ) AVCC AVSS VREFH VREFL PF0 (TXD0) PF1 (RXD0) PF2 (SCLK0/ CTS0 ) PF3 (TXD1) PF4 (RXD1) PF5 (SCLK1/ CTS1 ) PF6 to PF7 900/H1 CPU 10-bit 8-ch AD converter Serial I/O SIO0 Serial I/O SIO1 Port F DVCC [3] DVSS [4] PLL XWA W A H-OSC XBC B C Clock gear XDE D E XHL H L XIX IX XIY IY XIZ IZ XSP SP 32 bits P90 (SCK) P91 (SO/SDA) P92 (SI/SCL) Serial bus I/F SBI0 SR F PC X2 Mode controller 8-bit timer (Timer A0) PC1 (TA1OUT/INT1) 8-bi
TMP92CM22 2. Pin Assignment and Functions The assignment of input/output pins for the TMP92CM22FG, their names and functions are as follows. 2.1 Pin Assignment VREFL P70/RD P67/A23 P72/WRLU P71/WRLL P73 P74/CLKOUT 80 P76/WAIT P75/R/W P80/CS0 DVSS4 P81/CS1 85 P83/CS3 P82/CS2 P90/SCK P91/SO/SDA P92/SI/SCL 90 PD0/TB1IN0/INT4 PD1/TB1IN1/INT5 PD2/TB1OUT0 95 PD3/TB1OUT1 PA0 PA1 AVSS PA2 100 AVCC Figure 2.1.1 shows the pin assignment of the TMP92CM22FG.
TMP92CM22 2.2 Pin Names and Functions The following tables show the names and functions of the input/output pins. Table 2.2.1 Pin Names and Functions (1/2) Pin Names D0 to D7 Number of Pins 8 P10 to P17 I/O Functions I/O Data (Lower): Data bus D0 to D7. I/O Port 1: I/O port that allows I/O to be selected at the bit level. 8 (when used to the external 8-bit bus.) D8 to D15 I/O Data: Data bus D8 to D15. P40 to P47 I/O Port 4: I/O port.
TMP92CM22 Table 2.2.2 Pin Names and Functions (2/2) Pin Names PC0 TA0IN Number of Pins 1 PC1 INT1 INT0 1 1 1 I/O 1 TB0OUT0 I/O 1 TB1IN0 PD1 TB1OUT0 PD3 TB1OUT1 PF0 TXD0 PF1 RXD0 1 1 1 1 PF2 SCLK0 1 PF3 TXD1 PF4 RXD1 1 1 PF5 SCLK1 1 PF6 to PF7 2 AN0 to AN7 8 ADTRG NMI 1 Interrupt request pin 1: Interrupt request pin with programmable level/rising edge/falling edge. Timer output: 8-bit timer A0 or timer A1 output. Port C3: I/O port.
TMP92CM22 3. Operation This section describes the basic components, functions and operation of the TMP92CM22. 3.1 CPU The TMP92CM22 incorporates a high-performance 32-bit CPU (The TLCS-900/H1 CPU). For a description of this CPU’s operation, please refer to the section of this data book which describes the TLCS-900/H1 CPU. The following sub-sections describe functions peculiar to the CPU used in the TMP92CM22; these functions are not covered in the section devoted to the TLCS-900/H1 CPU. 3.1.
TMP92CM22 3.1.2 Reset Operation When resetting the TMP92CM22 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low for at least 20 system clocks (16 μs at fc = 40 MHz).
TMP92CM22 VCC 3.3 V RESET 0 [s] (Min) Oscillator operation time + 20 system clocks Figure 3.1.1 Reset Timing Example 3.1.3 Outline of Operation Mode Set AM1 and AM0 pins to “10” to use 8-bit external bus, or set it to “01” to use 16-bit external bus. Table 3.1.
TMP92CM22 3.2 Memory Map Figure 3.2.1 shows memory map of TMP92CM22. 000000H Internal I/O (8 Kbytes) Direct area(n) 000100H 001FE0H 002000H 00A000H 64-Kbyte area (nn) Internal RAM (32 Kbytes) 010000H External memory F00000H F10000H Provisinal emulator control area (64 Kbytes) External memory 16-Mbyte area (R) ( − R) (R + ) (R + R8/16) (R + d8/16) (nnn) FFFF00H Vector table (256 bytes) FFFFFFH = Internal area) ( Figure 3.2.
TMP92CM22 3.3 Clock Function and Standby Function TMP92CM22 contains (1) Clock gear, (2) Standby controller and (3) Noise-reducing circuit. It is used for low-power, low-noise systems. This chapter is organized as follows: 3.3.1 Block Diagram of System Clock 3.3.2 SFRs 3.3.3 System Clock Controller 3.3.4 Clock Doubler (PLL) 3.3.5 Noise Reduction Circuits 3.3.
TMP92CM22 The clock operating modes are as follows: (a) Single clock mode (X1 and X2 pins only), (b) Dual clock mode (X1, X2 pins and PLL). Figure 3.3.1 shows a transition figure.
TMP92CM22 3.3.
TMP92CM22 3.3.2 SFRs 7 SYSCR0 (10E0H) 5 4 3 2 − − Read/Write R/W R/W After reset 1 Function SYSCR1 (10E1H) 6 Bit symbol 1 0 GEAR1 GEAR0 0 0 0 Always write “1”. Always write “0”. − Bit symbol GEAR2 Read/Write R/W After reset 0 Function 1 Always write “0”.
TMP92CM22 7 PLLCR (10E8H) Bit symbol PLLON Read/Write After reset Function 6 5 FCSEL LWUPFG R/W 0 0: PLL stop 1: PLL run 4 3 2 1 0 2 1 0 EXTIN DRVOSCH − R 0 0: fc = OSCH 1: fc = PLL (× 4) 0 PLL warm-up flag 0: Don’t end up or stop 1: End up Note: Logic of PLLCR is different DFM of 900/L1. Figure 3.3.
TMP92CM22 3.3.3 System Clock Controller The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O. It is used as input that fc outputted from high-frequency oscillation circuit and PLL (Clock doubler) SYSCR1, SYSCR1 sets the high-frequency clock gear to either 1, 2, 4, 8, or 16 (fc, fc/2, fc/4, fc/8, or fc/16). These functions can reduce the power consumption of the equipment in which the device is installed.
TMP92CM22 3.3.4 Clock Doubler (PLL) PLL outputs the fPLL clock signal, which is four times as fast as fOSCH. A reset initializes PLL to stop status, setting to PLLCR register is needed before use. Like an oscillator, this circuit requires time to stabilize. This is called the lockup time. Note 1: Input frequency limitation for PLL The limitation of input frequency (High-frequency oscillation) for PLL is the following. fOSCH = 4 to 10 MHz (Vcc = 3.0 V to 3.
TMP92CM22 Example 2: PLL stopping PLLCR EQU 10E8H LD (PLLCR), 10XXXXXXB ; Changes fc from 40 MHz to10 MHz. LD (PLLCR), 00XXXXXXB ; Stop PLL. X: Don’t care PLL output: fPLL System clock fSYS Changes from 40 MHz to 10 MHz. Stops PLL operation. Limitation point on the use of PLL 1. When PLL is started, don’t set fc from fOSCH to fPLL at same time. Don’t setting: LD (PLLCR), 00H LD (PLLCR), C0H 2. When PLL is started, don’t set fc from fOSCH to fPLL at same time.
TMP92CM22 3.3.5 Noise Reduction Circuits Noise reduction circuits are built in for reduction EMI (Unnecessary radius noise) and reinforcement EMS (Measure of endure noise), allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator (2) Single drive for high-frequency oscillator (3) SFR protection of register contents These functions need setting by EMCCR0 to EMCCR2.
TMP92CM22 (2) Single drive for high-frequency oscillator (Purpose) Not need twin-drive and protect mistake operation by inputted noise to X2 pin when the external oscillator is used. (Block diagram) fOSCH X1 pin Oscillation enable ( STOP + EMCCR0 < EXTIN > ) EMCCR0 X2 pin (Setting method) The oscillator is disabled and starts operation as buffer by writing “1” to EMCCR0 register. X2 pin is always outputted “1”. By reset, is initialized to “0”.
TMP92CM22 (3) Runaway provision with SFR protection register (Purpose) Provision in runaway of program by noise mixing. Write operation to specified SFR is prohibited so that provision program in runaway prevents that is in the state which is fetch impossibility by stopping of clock, memory control register (Memory controller) is changed. And error handling in runaway becomes easy by INTP0 interruption. Specified SFR list 1.
TMP92CM22 3.3.6 Standby Controller (1) HALT modes When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1, or STOP mode, depending on the contents of the SYSCR2 register. The subsequent actions performed in each mode are as follows: a. IDLE2: Only the CPU halts. The internal I/O is available to select operation during IDLE2 mode by setting the following register. Table 3.3.1 shows the registers of setting operation during IDLE2 mode. Table 3.3.
TMP92CM22 (2) How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination between the states of interrupt mask register and the HALT modes. The details for release the halt status are shown in Table 3.3.3. • Released by requesting an interrupt The operating released from the HALT mode depends on the interrupt enabled status.
TMP92CM22 Table 3.3.
TMP92CM22 (3) Operation a. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.3.6 illustrates an example of the timing for clearance of the IDLE2 mode halt state by an interrupt. X1 A0 to A23 D0 to D15 Data Data RD WR Interrupt of releasing halt IDLE2 mode Figure 3.3.6 Timing Chart for IDLE2 Mode Halt State Released by Interrupt b.
TMP92CM22 c. STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator pin status in STOP mode depends on the settings in the SYSCR2 register. Table 3.3.5, Table 3.3.6 shows the state of these pins in STOP mode. After STOP mode has been released system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize. Warm-up time set by SYSCR2 register. See the sample warm-up times in Table 3.3.4. Figure 3.3.
TMP92CM22 Table 3.3.
TMP92CM22 Table 3.3.
TMP92CM22 3.4 Interrupt Interrupts of TLCS-900/H1 are controlled by the CPU interrupt mask flip-flop (IFF2:0) and by the built-in interrupt controller.
TMP92CM22 Interrupt processing Interrupt specified by micro DMA start vector? Micro DMA soft start request Yes Clear interrupt request flag No Interrupt vector “V” read Interrupt request F/F clear Data transfer by micro DMA Micro DMA processing General-purpose interrupt processing PUSH PC PUSH SR SR ← Level of accepted interrupt + 1 INTNEST ← INTNEST + 1 COUNT ← COUNT − 1 COUNT = 0 No Yes Generating INTTC interrupt clear micro DMA start vector PC←(FFFF00H) + V) Interrupt process progra
TMP92CM22 3.4.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. That is also the same as TLCS-900/L, TLCS-900/H, and TLCS-900/L1. (1) The CPU reads the interrupt vector from the interrupt controller. If the same level interrupts occur simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt request.
TMP92CM22 Table 3.4.
TMP92CM22 Default Priority Type Interrupt Source Vector Value Address Refer to Vector Micro DMA Start Vector 52 INTAD: AD conversion end 00CCH FFFFCCH 33H 53 INTTC0: Micro DMA end (Channel 0) 00D0H FFFFD0H 34H 54 INTTC1: Micro DMA end (Channel 1) 00D4H FFFFD4H 35H 55 INTTC2: Micro DMA end (Channel 2) 00D8H FFFFD8H 36H 56 INTTC3: Micro DMA end (Channel 3) 00DCH FFFFDCH 37H INTTC4: Micro DMA end (Channel 4) 00E0H FFFFE0H 38H 58 INTTC5: Micro DMA end (Channel 5) 00E4H FFF
TMP92CM22 3.4.2 Micro DMA In addition to general-purpose interrupt processing, the TMP92CM22 also includes a micro DMA function. Micro DMA processing for interrupt requests set by micro DMA is performed at the highest priority level for maskable interrupts (Level 6), regardless of the priority level of the interrupt source.
TMP92CM22 Although the control registers used for setting the transfer source and transfer destination addresses are 32 bits wide, this type of register can only output 24-bit addresses. Accordingly, micro DMA can only access 16 Mbytes (the upper eight bits of a 32-bit address are not valid). Three micro DMA transfer modes are supported: one-byte transfers, two-byte (one-word) transfer and four-byte transfer.
TMP92CM22 (2) Soft start function In addition to starting the micro DMA function by interrupts, TMP92CM22 includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register. Writing “1” to each bit of DMAR register causes micro DMA once (If write “0” to each bit, micro DMA doesn’t operate). At the end of transfer, the corresponding bit of the DMAR register is automatically cleared to “0”. Only one channel can be set for DMA request at once.
TMP92CM22 (4) Detailed description of the transfer mode register 0 0 0 Mode DMAM0 to DMAM7 DMAM [4:0] 000 zz 001 zz 010 zz 011 zz 100 zz 101 zz 110 zz 111 00 ZZ Operation Destination address INC mode (DMADn +) ← (DMASn) DMACn ← DMACn − 1 If DMACn = 0 then INTTC Source address DEC mode (DMADn −) ← (DMASn) DMACn ← DMACn − 1 If DMACn = 0 then INTTC Source address INC mode (DMADn) ← (DMASn +) DMACn ← DMACn − 1 If DMACn = 0 then INTTC Source address DEC mode (DMADn) ← (DMASn −) DMACn ← DMACn − 1 If
TMP92CM22 3.4.3 Interrupt Controller Operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 33 interrupts channels there is an interrupt request flag (Consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register.
92CM22-39 Micro DMA counter 0 interrupt INTTC0 INTTC1 INTTC2 INTTC3 INTTC4 INTTC5 INTTC6 INTTC7 (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) INT1 INT2 INT3 INT0 INTWD (Reserved) R R Q CLR D Reset D5 D4 D3 D2 D1 D0 Dn + 3 V = 20H V = 24H Decoder Y1 A Y2 Y3 B Y4 Y5 C Y6 6 INTTC0 6 34 Selector S 1 DMA0V DMA1V DMA2V DMA3V Soft start V = D0H V = D4H V = D8H V = DCH V = E0H V = E4H V = E8H V = ECH Interrupt request F/F read Interrupt vector read Micro DMA acknowlege V
TMP92CM22 (1) Interrupt priority setting registers Symbol Name Address 7 6 I2C I2M2 5 4 3 2 I2M1 I2M0 I1C I1M2 INT2 INTE12 INT1&INT2 enable D0H R 0 − − R INTE3 D1H 0 0 0 0 − − I3C I3M2 − − R INTETA01 D4H INTTA2& INTTA3 ITA1M1 R 0 INTETA23 ITA1M2 0 enable ITA3C R/W 0 0 ITA3M2 ITA3M1 R 0 ITA0C ITA0M2 INTTB00& INTTB01 enable D8H ITB01C 0 0 0 ITB01M1 R 0 0 ITA3M0 ITA2C 0 0 INTTBO0 (Overflow) enable DAH − ITB01M0 0 ITA2M2 DBH − 0 − − R/W
TMP92CM22 Symbol Name Address 7 6 IADC IADM2 5 4 3 2 IADM1 IADM0 I0C I0M2 INTAD INTE0AD INT0&INTAD enable F0H R 0 ITC1C ITC1M2 INTETC01 F1H 0 ITC1M1 R 0 0 0 ITC1M0 ITC0C ITC0M2 0 ITC3C ITC3M2 INTETC23 F2H ITC3M1 R 0 0 INTTC4& INTTC5 enable F3H ITC5C ITC5M2 0 0 0 ITC3M0 ITC2C ITC2M2 0 0 INTTC6& INTTC7 enable F4H ITC7C ITC7M2 0 0 0 ITC5M0 ITC4C ITC4M2 0 INTWD enable − F7H − 0 0 0 0 INTTC6 (DMA6) ITC7M0 ITC6C ITC6M2 ITC6M1 R 0 0 ITC6M0
TMP92CM22 (2) External interrupt control Symbol Name Address 7 6 5 4 I3EDGE I2EDGE 3 2 1 I1EDGE I0EDGE I0LE W 0 IIMC Interrupt input mode control IIMC2 Interrupt input mode control2 00F6H (Prohibit RMW) 0 0 NMIREE R/W 0 0 0 INT3EDGE INT2EDGE INT1EDGE INT0EDGE INT0 0: Rising/ 0: Rising/ 0: Rising/ 0: Rising/ 0: Edge high high high high 1: Level 1: Falling/ 1: Falling/ 1: Falling/ 1: Falling/ low low low low I3LE I2LE 0 NMI 0: Falling edge 1: Falling and rising edges I1LE W 00FA
TMP92CM22 Table 3.4.
TMP92CM22 (3) SIO receive interrupt control Symbol Name Address 7 6 5 4 3 2 1 0 IR1LE SIO SIMC Interrupt mode IR0LE W F5H 1 (Prohibit RMW) 0: INTRX1 edge mode control 1: INTRX1 level mode 1 0: INTRX0 edge mode 1: INTRX0 level mode *INTRX1 level enables 0 Detect edge INTRX1 1 “H” level INTRX1 *INTRX0 rising edge enable 0 Detect edge INTRX0 1 “H” Level INTRX0 92CM22-44 2007-02-16
TMP92CM22 (4) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 3.4.1, to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction.
TMP92CM22 Symbol Name Address DMA0 DMA0V start 100H vector 7 6 5 4 3 DMA0V5 DMA0V4 DMA0V3 2 1 0 DMA0V2 DMA0V1 DMA0V0 0 0 DMA1V1 DMA1V0 0 0 DMA2V1 DMA2V0 0 0 DMA3V1 DMA3V0 0 0 DMA4V1 DMA4V0 0 0 DMA5V1 DMA5V0 0 0 DMA6V1 DMA6V0 0 0 DMA7V1 DMA7V0 0 0 R/W 0 0 0 0 DMA0 start vector DMA1V5 DMA1 DMA1V start 101H vector DMA1V4 DMA1V3 DMA1V2 R/W 0 0 0 0 DMA1 start vector DMA2V5 DMA2 DMA2V start 102H vector DMA2V4 DMA2V3 DMA2V2 R/W 0 0 0 0
TMP92CM22 (6) Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer, once started, to continue until the value in the transfer counter register reaches 0. Setting any of the bits in the register DMAB which correspond to a micro DMA channel (as shown below) to 1 specifies that any micro DMA transfer on that channel will be a burst transfer.
TMP92CM22 (7) Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore if, immediately before an interrupt is generated, the CPU fetches an instruction which clears the corresponding interrupt request flag (Note), the CPU may execute this instruction in between accepting the interrupt and reading the interrupt vector. In this case, the CPU will read the default vector 0004H and jump to interrupt vector address FFFF04H.
TMP92CM22 3.5 Port Function The TMP92CM22 features 50-bit settings which relate to the various I/O ports. As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in CPU and internal I/Os. Table 3.5.1 lists the functions of each port pin. Table 3.5.2 and Table 3.5.3 lists I/O registers and their specifications. Table 3.5.
TMP92CM22 Table 3.5.
TMP92CM22 Table 3.5.
TMP92CM22 Port 1 (P10 to P17) Port1 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P1CR and function register P1FC. In addition to functioning as a general-purpose I/O port, port1 can also function as a data bus (D8 to D15). After released reset, device set port1 to pins of follow function by combination of AM1 and AM0 pins.
TMP92CM22 Port 1 Register P1 (0004H) Bit symbol 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 Read/Write R/W After reset Data from external port (Output latch register is clear to “0”.
TMP92CM22 3.5.2 Port 4 (P40 to P47) Port 4 is an 8-bit general-purpose I/O port*. Bits can be individually set as either inputs or outputs by control register P4CR and function register P4FC*. In addition to functioning as a general-purpose I/O port, port 4 can also function as a address bus (A0 to A7). After released reset, device set Port 4 to pins of follow function by combination of AM1 and AM0 pins.
TMP92CM22 P4 (0010H) P4CR (0012H) Bit symbol Port 4 Register 4 7 6 5 P47 P46 P45 P44 2 1 0 P42 P41 P40 Read/Write R/W After reset Data from external port (Output latch register is cleared to “0”.
TMP92CM22 3.5.3 Port 5 (P50 to P57) Port 5 is an 8-bit general-purpose I/O port*. Bits can be individually set as either inputs or outputs by control register P5CR and function register P5FC*. In addition to functioning as a general-purpose I/O port, port 5 can also function as an address bus (A8 to A15). After released reset, device set port 5 to pins of follow function by combination of AM1 and AM0 pins.
TMP92CM22 P5 (0014H) P5CR (0016H) Bit symbol Port 5 Register 4 7 6 5 P57 P56 P55 P54 2 1 0 P52 P51 P50 Read/Write R/W After reset Data from external port (Output latch register is cleared to “0”.
TMP92CM22 3.5.4 Port 6 (P60 to P67) Port 6 is an 8-bit general-purpose I/O port*. Bits can be individually set as either inputs or outputs by control register P6CR and function register P6FC*. In addition to functioning as a general-purpose I/O port, port 6 can also function as an address bus (A16 to A23). After released reset, device set port 6 to pins of follow function by combination of AM1 and AM0 pins.
TMP92CM22 Port 6 Register P6 (0018H) Bit symbol 7 6 5 4 3 2 1 0 P67 P66 P65 P64 P63 P62 P61 P60 Read/Write R/W After reset Data from external port (Output latch register is cleared to “0”.
TMP92CM22 Port 7 (P70 to P76) Port 7 is a 7-bit general-purpose I/O port (P70 to P75 are used for output only). Bits can be individually set as either inputs or outputs by control register P7CR and function register P7FC. In addition to functioning as a general-purpose I/O port, P70 to P73 pins can also function as output pin of read/write strobe signals to connect with an external memory. P74 pin can also function as CLKOUT output pin when outputted internal clock. P76 pin can also function as wait input.
TMP92CM22 Reset Direction control (on bit basis) P7CR write Internal data bus Function control (on bit basis) P7FC write S Output latch Output buffer Port P7 P76 ( WAIT ) P7 write P7 read Internal WAIT signal Figure 3.5.10 Port 7 (P76) Port 7 Register 7 P7 (001CH) Bit symbol 6 5 4 3 2 1 0 P76 P75 P74 P73 P72 P71 P70 Data from external port (Note) 1 1 1 1 1 2 1 0 Read/Write R/W After reset 1 Note: Output latch register is cleared to 0.
TMP92CM22 3.5.6 Port 8 (P80 to P83) Port 8 is 4-bit output port. Resetting sets output latch of P82 to “0” and set output latches of P80, P81, and P83 to “1”. In addition to functioning as a output port, port 8 can also function as a output chip select signal ( CS0 to CS3 ). These settings operate by programming “1” to the corresponding bit of P8FC. Resetting set all bits of P8FC to “0”, these pits set output mode.
TMP92CM22 Port 9 (P90 to P92) Port 9 is 3-bit general-purpose I/O port. Each bit can be set individually for input or output. In addition to functioning as a general-purpose I/O port, port 9 can also function as a serial bus interface input (SCK (Clock signal in SIO mode), SO (Data output signal in SIO mode), SDA (Data signal in I2C bus mode), SI (Data input signal in SIO mode) and SCL (Clock signal in I2C bus mode)). These settings operate by programming to the corresponding bit of P9FC.
TMP92CM22 Port 9 Register 7 P9 (0024H) 6 5 4 3 Bit symbol 2 1 0 P92 P91 P90 Read/Write R/W After reset Data from external port (Output latch register is set to 1) Port 9 Control Register 7 P9CR (0026H) 6 5 4 3 Bit symbol 2 1 0 P92C P91C P90C Read/Write W After reset 0 0 Function 0: Input 0 1: Output Port 9 Function Register 7 P9FC (0027H) 6 5 4 3 Bit symbol 2 1 0 P92F P91F P90F Read/Write W After reset 0 Function 0 0 0: Port, SI 0: Port 0: Port, 1:
TMP92CM22 3.5.8 Port A (PA0 to PA2, PA7) Port A is 4-bit general-purpose input port with pull-up resistor. Internal data bus Pull-up resistor PA0, PA1, PA2, PA7 PA read Figure 3.5.16 Port A Port A Register 7 PA (0028H) 6 5 4 3 2 1 0 PA2 PA1 PA0 Bit symbol PA7 Read/Write R R After reset Data from external port Data from external port Figure 3.5.
TMP92CM22 Port C (PC0, PC1, PC3, PC5, and PC6) Port C is 5-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets port C to input port. In addition to functioning as a general-purpose I/O port, port C can also function as a input/output pin (TA0IN, TA1OUT, TA3OUT, and TB0OUT0) and external interrupt pin (INT0 to INT3). These settings operate by programming “1” to the corresponding bit of PCCR and PCFC.
TMP92CM22 (2) PC1 (INT1, TA1OUT), PC5 (INT2, TA3OUT), PC6 (INT3, TB0OUT0) In addition to function as I/O port, port PC1, PC5, and PC6 can also function as external interrupt input pin INT1 to INT3 and output pin of timer channel TA1OUT, TA3OUT, and TB0OUT0.
TMP92CM22 (3) PC3 (INT0) In addition to function as I/O port, port PC3 can also function as external interrupt pin INT0. Reset Direction control (on bit basis) Internal data bus PCCR write Function control (on bit basis) PCFC write S PC3 (INT0) Output latch PC read S B Selector PC read INT0 A Select level/edge and Select rising/falling IIMC Figure 3.5.
TMP92CM22 Port C Register 7 PC (0030H) Bit symbol 6 5 PC6 PC5 4 3 2 PC3 1 0 PC1 PC0 Read/Write R/W R/W R/W After reset Data from external port (Note) Data from external port (Note) Data from external port (Note) Note: Output latch register is set to 1.
TMP92CM22 Port D (PD0 to PD3) Port D is 4-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets port D to input port. In addition to functioning as a general-purpose I/O port, port D can also function as an input pin (INT4 and INT5)/output pin (TB0IN, TB1OUT, TB3OUT, and TB1OUT1). These settings operate by programming “1” to the corresponding bit of PDCR and PDFC. Resetting resets the PDCR and PDFC to “0”, and sets all bits to input port.
TMP92CM22 (2) PD2 (TB1OUT0) and PD3 (TB1OUT1) In addition to function as I/O port, port PD0 and PD1 can also function as timer channel output pins TB1OUT0 and TB1OUT1. Reset Direction control (on bit basis) Internal data bus PDCR write Function control (on bit basis) PDFC write S Output latch PD write TB1OUT0 TB1OUT1 S A Selector B PD2 (TB1OUT0) PD3 (TB1OUT1) S B Selector A PF read Figure 3.5.
TMP92CM22 Port D Register 7 PD (0034H) 6 5 4 Bit symbol 3 2 1 0 PD3 PD2 PD1 PD0 Read/Write R/W After reset Data from external port (Output latch register is set to 1) Port D Control Register 7 PDCR (0036H) 6 5 4 Bit symbol 3 2 PD3C PD2C Read/Write 1 0 PD1C PD0C W After reset 0 Function 0: Input 1: Output 0 0 0: Input 1: Output 0 0: Input 1: Output 0: Input 1: Output Port D I/O setting 7 PDFC (0037H) 6 Port D Function Register 5 4 3 Bit symbol PD3F 2 PD2F Rea
TMP92CM22 Port F (PF0 to PF7) Port F is 8-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting resets the PFCR and PFFC to “0”, and sets all bits to input port. And all bits of output latch register to “1”. In addition to functioning as a general-purpose I/O port, port F can also function as I/O function of serial channel 0 and 1. These settings operate by writing “1” to the corresponding bit of PFFC.
TMP92CM22 (2) Ports PF1 and PF4 (RXD0 and XD1) In addition to function as I/O port, port PF1 and PF4 can also function as RXD input pin of serial channel. Reset Direction control (on bit basis) Internal data bus PFCR write S PF1 (RXD0) PF4 (RXD1) Output latch PF write PF read S B Selector A RXD0, RXD1 Figure 3.5.
TMP92CM22 (3) Port PF2 ( CTS0 , SCLK0) and port PF5 ( CTS1 , SCLK1) In addition to function as I/O port, port PF2 and PF5 can also function as CTS input pin of serial channel or SCLK I/O pin. Reset Direction control (on bit basis) Internal data bus PFCR write Function control (on bit basis) PFFC write S Output latch SCLK0, SCLK1 output PF write S A Selector B PF2 (SCLK0, CTS0 ) PF5 (SCLK1, CTS1 ) S B Selector A PF read CTS0 , CTS1 SCLK0, SCLK1 input Figure 3.5.
TMP92CM22 Port F Register PF (003CH) Bit symbol 7 6 5 4 3 2 1 0 PF7 PF6 PF5 PF4 PF PF2 PF1 PF0 Read/Write R/W After reset Data from external port (Output latch register is set to 1) Port F Control Register PFCR (003EH) Bit symbol 7 6 5 4 PF7C PF6C PF5C PF4C Read/Write 3 2 1 0 PF3C PF2C PF1C PF0C 0 0 0 0 2 1 0 W After reset 0 0 0 0 Function 0: Input 1: Output Port F Function Register 7 PFFC (003FH) − Bit symbol Read/Write 5 4 − PF5F 3 PF3F W
TMP92CM22 3.5.12 Port G (PG0 to PG7) Internal data bus Port G is 8-bit input port and can also be used as the analog input pins for the internal AD converter. PG3 can also be used as ADTRG pin for the AD converter. Port G PG0 to PG7 (AN0 to AN7) PG read Convertion result register AD read AD converter Channel selector ADTRG (only PG3) Figure 3.5.
TMP92CM22 3.6 Memory Controller 3.6.1 Function TMP92CM22 has a memory controller with a variable 4-block address area that controls as follows. (1) 4-block address area support Specifies a start address and a block size for 4-block address area. (2) Connecting memory specifications Specifies SRAM and ROM as memories to connect with the selected address areas. (3) Data bus size selection Whether 8-bit or 16-bit is selected as the data bus size of the respective block address areas.
TMP92CM22 3.6.2 Control Register and Operation after Reset Release This section describes the registers to control the memory controller, the state after reset release and necessary settings. (1) Control register The control registers of the memory controller are as follows. • Control register: BnCSH/BnCSL (n = 0 to 3, EX) Sets the basic functions of the memory controller, that is the connecting memory type, the number of waits to be read and written.
TMP92CM22 3.6.3 Basic Functions and Register Setting In this section, setting of the block address area, the connecting memory and the number of waits out of the memory controller’s functions are described. (1) Block address area specification The block address area is specified by two registers. The memory start address register (MSAR) sets the start address of the block address areas. The memory controller compares between the register value and the address every bus cycles.
TMP92CM22 (iii) Example of register setting To set the block address area 1 to 512 bytes from address 110000H, set the register as follows. MSAR1 Register Bit symbol Setting value 7 6 5 4 3 2 1 0 M1S23 M1S22 M1S21 M1S20 M1S19 M1S18 M1S17 M1S16 0 0 0 1 0 0 0 1 M1S23 to M1S16 bits of the memory start address register MSAR1 correspond with address A23 to A16. A15 to A0 are cleared to “0”.
TMP92CM22 (2) Connection memory specification Setting the BnOM1 to BnOM0 bit of the control register (BnCSH) specifies the memory type to be connected with the block address areas. The interface signal is output according to the set memory as follows. TMP92CM22 prohibit changing default (SRAM/ROM).
TMP92CM22 CPU Data Data Size (Bit) Start Address Data Width in Memory Side (Bit) CPU Address D15 to D8 D7 to D0 8 4n + 0 8/16 4n + 0 xxxxx b7 to b0 b7 to b0 4n + 1 4n + 2 4n + 3 16 4n + 0 4n + 1 4n + 2 4n + 3 32 4n + 0 8 4n + 1 xxxxx 16 4n + 1 b7 to b0 xxxxx 8/16 4n + 2 xxxxx b7 to b0 b7 to b0 8 4n + 3 xxxxx 16 4n +3 b7 to b0 xxxxx 8 (1) 4n + 0 xxxxx b7 to b0 (2) 4n + 1 xxxxx b15 to b8 16 4n + 0 b15 to b8 b7 to b0 8 (1) 4n + 1 xxxxx b7 to b0 (2) 4n + 2
TMP92CM22 (4) Wait control The external bus cycle completes a wait of two states at least (100 ns at fSYS = 20 MHz). Setting the and of BnCSL specifies the number of waits in the read cycle and the write cycle. BnWW is set with the same method as BnWR.
TMP92CM22 • When not inserting a dummy (0 waits) CLKOUT Address CSm CSn RD • When inserting a dummy cycle (0 waits) Dummy CLKOUT Address CSm CSn RD 92CM22-85 2007-02-16
TMP92CM22 (5) Bus access timing • External read/write bus cycle (0 waits) CLKOUT (20 MHz) T1 T2 CS Address RD Read D7 to D0 input WR Write output D7 to D0 • External read/write bus cycle (1 wait) CLKOUT (20 MHz) T1 TW T2 CS Address RD Read Input D7 to D0 WR D7 to D0 Write Output 92CM22-86 2007-02-16
TMP92CM22 • External read/write bus cycle (0 waits at WAIT pin input mode) CLKOUT (20 MHz) T1 T2 CS Address RD Read D7 to D0 Input WR Write D7 to D0 Output WAIT Sampling • External read/write bus cycle (n waits at WAIT pin input mode) CLKOUT (20 MHz) T1 T2 TW CS Address RD Read D7 to D0 Input WR Write D7 to D0 Output WAIT Sampling Sampling 92CM22-87 2007-02-16
TMP92CM22 Example of WAIT input cycle (5 waits) FF0 D Q CK FF1 D Q CK FF2 D CK RES RES 2 3 RES Q FF3 D CK RES Q FF4 D Q WAIT CK RES CLKOUT CSn RD WRLL WRLU CLKOUT (20 MHz) 1 4 5 6 7 CSn RD FF_RES FF0_D FF0_Q FF1_Q FF2_Q FF3_Q WAIT 92CM22-88 2007-02-16
TMP92CM22 (6) Connecting external memory Figure 3.6.1 shows an example of how to connect external memory to the TMP92CM22. This example connects ROM and SRAM in 16-bit width. TMP92CM22 16-bit SRAM RD OE WRLL LB WRLU UB R/ W R/W CS0 CE D [15:0] A0 I/O [16:1] Not connetion A1 A0 A2 A1 A3 A2 ･ ･ ･ ･ ･ ･ ･ ･ ･ ･ ･ ･ ･ ･ ･ ･ ･ ･ 16-bit ROM OE CS2 CE DQ [15:0] A0 A1 A2 ･ ･ ･ ･ ･ ･ Figure 3.6.1 Example of External Memory By resetting, TMP92CM22 function as output port.
TMP92CM22 3.6.4 ROM Control (Page mode) This section describes ROM page mode accessing and how to set registers. ROM page mode is set by the page ROM control register. (1) Operation and how to set the registers The TMP92CM22 supports ROM access of the page mode. ROM access of the page mode is specified only in block address area 2. ROM page mode is set by the page ROM control register (PMEMCR).
TMP92CM22 3.6.5 List of Registers The memory control registers and the settings are described as follows. For the addresses of the registers, see list of special function registers in section 5. (1) Control registers The control register is a pair of BnCSL and BnCSH. (“n” is a number of the block address area.) BnCSL has the same configuration regardless of the block address areas. In BnCSH, only B2CSH which is corresponded to the block address area 2 has a different configuration from the others.
TMP92CM22 B2REC Sets the dummy cycle for data output recovery time. 0 = Not insert a dummy cycle (Default) 1 = Insert a dummy cycle B2OM[1:0] 00 = SRAM or ROM (Default) Others = (Reserved) B2BUS[1:0] Sets the data bus width. 00 = 8 bits (Default) 01 = 16 bits 10 = (Reserved) 11 = (Reserved) Note: The value of B2BUS bit is set according to the state of AM[1:0] pin after reset release.
TMP92CM22 BEXCSL 7 Bit symbol 6 5 4 BEXWW2 BEXWW1 BEXWW0 Read/Write 3 2 1 0 BEXWR2 BEXWR1 BEXWR0 W After reset 0 W 1 0 0 1 0 1 0 BEXBUS1 BEXBUS0 0 0 BEXWW[2:0] Specifies the number of write waits. 001 = 2 states (0 waits) access 010 = 3 states (1 wait) access 101 = 4 states (2 waits) access 110 = 5 states (3 waits) access 111 = 6 states (4 waits) access 011 = WAIT pin input mode Others = (Reserved) BEXWR[2:0] Specifies the number of read waits.
TMP92CM22 (1) Block address area specification register A start address and range in the block address are specified by the memory start address register (MSARn) and the memory address mask register (MAMRn). The memory start address register sets all start address similarly regardless of the block address areas. The bit to be set by the memory address mask register is depended on the block address area.
TMP92CM22 (2) Page ROM control register (PMEMCR) The page ROM control register sets page ROM accessing. ROM page accessing is executed only in block address area 2. PMEMCR 7 6 5 Bit symbol 4 3 2 1 0 OPGE OPWR1 OPWR0 PR1 PR0 1 0 Read/Write R/W After reset 0 0 0 OPGE Enable bit. 0 = No ROM page mode accessing (Default) 1 = ROM page mode accessing OPWR [1:0] Specifies the number of waits.
TMP92CM22 Table 3.6.
TMP92CM22 3.6.6 Caution If the parasitic capacitance of the read signal (Output enable signal) is greater than that of the chip select signal, it is possible that an unintended read cycle occurs due to a delay in the read signal. Such an unintended read cycle may cause a trouble as in the case of (a) in Figure 3.6.3 CLKOUT (20 MHz) Address Memory 1 chip select Memory 2 chip select RD (a) Figure 3.6.
TMP92CM22 (2) The cautions at the time of the functional change of a CSn . A chip select signal output has the case of a combination terminal with a general-purpose port function. In this case, an output latch register and a function control register are initialized by the reset action, and an object terminal is initialized by the port output (“1” or “0”) by it.
TMP92CM22 3.7 8-Bit Timers (TMRA) The TMP92CM22 features 4 built-in 8-bit timers. These timers are paired into four modules: TMRA01 and TMRA23. Each module consists of two channels and can operate in any of the following four operating modes.
External input clock: TA0IN Prescaler clock: φT0 φT4 8 Selector 4 92CM22-100 TA01RUN φT256 n overflow 2 Internal data bus Register buffer 0 8-bit timer register TA0REG 8-bit comparator (CP0) Match detect 8-bit timer register TA1REG 8-bit comparator (CP1) 8-bit up counter (UC1) TA01RUN Internal data bus TMRA0 match output: TA0TRG TA01MOD TA0TRG Selector TA01MOD φT1 φT16 φT256 TA01RUN TMRA0 interrupt output: INTTA0 Run/clear TA01
Prescaler clock: φT0 φT4 8 Selector 4 92CM22-101 TA23RUN φT256 n 2 overflow Run/clear Internal data bus Register buffer 2 8-bit timer register TA2REG 8-bit comparator (CP2) Match detect TA23MOD TA2TRG Selector 8-bit timer register TA3REG 8-bit comparator register (CP3) (UC3) 8-bit up counter TA23RUN Internal data bus TMRA2 match output: TA2TRG TA23MOD φT1 φT16 φT256 TA23RUN TMRA2 interrupt output: INTTA2 TA23MOD 8-bit
TMP92CM22 3.7.2 Operation of Each Circuit (1) Prescaler A 9-bit prescaler generates the input clock to TMRA01. The prescaler’s operation can be controlled using TA01RUN in the timer control register. Setting to “1” starts the count; setting to “0” clears the prescaler to “0” and stops operation. Table 3.7.2 shows the various prescaler output clock resolutions. Table 3.7.
TMP92CM22 (3) Timer registers (TA0REG and TA1REG) These are 8-bit registers, which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up counter, the comparator match detect signal goes Active. If the value set in the timer register is 00H, the signal goes active when the up counter overflows. The TA0REG are double buffer structure, each of which makes a pair with register buffer.
TMP92CM22 (4) Comparator (CP0) The comparator compares the value in an up counter with the value set in a timer register. If they match, the up counter is cleared to 0 and an interrupt signal (INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time. (5) Timer flip-flop (TA1FF) The timer flip-flop (TA1FF) is a flip-flop inverted by the match detects signal (8-bit comparator output) of each interval timer.
TMP92CM22 3.7.3 SFRs TMRA01 Run Register 7 TA01RUN Bit symbol (1100H) Read/Write 5 4 TA0RDE 3 2 I2TA01 TA01PRUN R/W After reset Function 6 1 0 TA1RUN TA0RUN 0 0 R/W 0 0 Double buffer 0: Disable 1: Enable IDLE2 0: Stop 1: Operate 0 TMRA01 prescaler UP counter (UC0) UP counter (UC1) 0: Stop and clear 1: Run (Count up) TA0REG double buffer control Count operation 0 Disable 0 Stop and clear 1 Enable 1 Count Note: The values of bits 4 to 6 of TA01RUN are undefined when read.
TMP92CM22 TMRA01 Mode Register TA01MOD Bit symbol (1104H) Read/Write After reset Function 7 6 5 4 TA01M1 TA01M0 PWM01 PWM00 3 2 1 TA1CLK1 TA1CLK0 TA0CLK1 0 0 0 TA0CLK0 R/W 0 0 Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode 0 0 0 PWM cycle 00: Reserved 6 01: 2 7 10: 2 8 11: 2 TMRA1 source clock 00: TA0TRG 01: φT1 10: φT16 11: φT256 0 TMRA0 source clock 00: TA0IN pin input (Note) 01: φT1 10: φT4 11: φT16 TMRA0 input clock 00 TA0IN
TMP92CM22 TMRA23 Mode Register TA23MOD (110CH) Bit symbol 7 6 5 4 TA23M1 TA23M0 PWM21 PWM20 Read/Write After reset Function 3 2 1 TA3CLK1 TA3CLK0 TA2CLK1 0 0 0 TA2CLK0 R/W 0 0 Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode 0 0 0 PWM cycle 00: Reserved 6 01: 2 7 10: 2 8 11: 2 TMRA3 source clock 00: TA2TRG 01: φT1 10: φT16 11: φT256 0 TMRA2 source clock 00: Reserved 01: φT1 10: φT4 11: φT16 TMRA2 input clock 00 Don’t set 01 φT1
TMP92CM22 TMRA1 Flip Flop Control Register 7 TA1FFCR (1105H) 6 5 4 Bit symbol 3 2 TA1FFC1 TA1FFC0 Read/Write 1 0 TA1FFCIE TA1FFCIS R/W After reset 1 Read-modify Function -write instruction is prohibited.
TMP92CM22 TMRA3 Flip-Flop Control Register 7 TA3FFCR (110DH) 6 5 4 Bit symbol 2 TA3FFC1 TA3FFC0 Read/Write 1 0 TA3FFCIE TA3FFCIS R/W After reset Read-modify -write instruction is prohibited.
TMP92CM22 Timer Register (TA0REG to TA3REG) Symbol Address TA0REG 1102H 7 6 5 4 3 2 1 0 − W Undefined − TA1REG 1103H W Undefined − TA2REG 110AH W Undefined − TA3REG 110BH W Undefined Note: Read-modify-write instruction is prohibited for above registers. Figure 3.7.
TMP92CM22 3.7.4 Operation in Each Mode (1) 8-bit timer mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. When set function and count data, TMRA0 and TMRA1 should be stopped. 1. Generating interrupts at a fixed interval (using TMRA1) To generate interrupts at constant intervals using TMRA1 (INTTA1), first stop TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and TA1REG register, respectively. Then, enable the interrupt INTTA1 and start TMRA1 counting.
TMP92CM22 2. Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF1) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). To output a 2.4 μs square wave pulse from the TA1OUT pin at fC = 40 MHz, use the following procedure to make the appropriate register settings. This example uses TMRA1; however, either TMRA0 or TMRA1 may be used.
TMP92CM22 3. Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparator (Match output forTMRA0) TMRA0 up counter (when TA0REG = 5) TMRA1 up counter (when TA1REG = 2) 1 2 3 4 5 1 2 1 3 4 2 5 1 2 3 1 Match output for TMRA1 Figure 3.7.
TMP92CM22 The comparator match signal is output from TMRA0 each time the up counter UC0 matches TA0REG, though the up-counter UC0 is not cleared. In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse on which the values in the up counter UC1 and TA1REG match. When the match detect signal is output simultaneously from both the comparator TMRA0 and TMRA1, the up counters UC0 and UC1 are cleared to 0 and the interrupt INTTA1 is generated.
TMP92CM22 In this mode, a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be smaller than the value set in TA1REG. Although the up counter for TMRA1 (UC1) is not used in this mode, TA01RUN should be set to “1”, so that UC1 is set for counting. Figure 3.7.14 shows a block diagram representing this mode.
TMP92CM22 Example: To generate 1/4 duty 62.5 kHz pulses (at fC= 40 MHz): 16 μs Calculate the value that should be set in the timer register. To obtain a frequency of 62.5 kHz, the pulse cycle t should be: t = 1/62.
TMP92CM22 (4) 8-bit PWM (Pulse width modulation) output mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output on the TA1OUT pin (which is also used as PC1). TMRA1 can also be used as an 8-bit timer. The timer output is inverted when the up counter (UC0) matches the value set in the timer register TA0REG or when 2n counter overflow occurs (n = 6, 7, or 8 as specified by TA01MOD).
TMP92CM22 In this mode, the value of the register buffer will be shifted into TA0REG if 2n overflow is detected when the TA0REG double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Match with TA0REG Up counter = Q1 2 n Up counter = Q2 overflow Shift from TA0REG (Register buffer) TA0REG (Value of compare) Q1 Q2 Q2 Register buffer Q3 Write to TA0REG Figure 3.7.
TMP92CM22 Table 3.7.
TMP92CM22 3.8 16-Bit Timer/Event Counters (TMRB) The TMP92CM22 contains 2 channels 16-bit timer/event counter (TMRB) which have the following operation modes: • 16-bit interval timer mode • 16-bit event counter mode • 16-bit programmable square wave pulse generation output mode (PPG: Variable duty cycle with variable period) Can be used following operation modes by capture function: • Frequency measurement mode • Pulse width measurement mode • Time differential measurement mode Figure 3.8.
(from TMRA01) TA1OUT 4 φT4 8 92CM22-121 TB0RUN TB0MOD control Selector Count clock Internal data bus Register buffer 10 16-bit timer register TB0REG0H/L 16-bit comparator (CP10) TB0MOD φT1 φT4 φT16 Match detection Intenal data bus 16-bit timer register TB0RG1H/L TB0FF0 Match detection Timer flip-flop control Timer flip-flop Register 1 INTTB01 Interrupt output Register 0 INTTB00 16-bit comparator (CP11) TB0RUN TB0MOD Caputure register 1
TB1IN0 TB1IN1 INT4 INT5 (from TMRA23) TA1OUT External interrupt input Prescaler clock: φT0 4 φT4 8 92CM22-122 TB1RUN TB1MOD control Count clock Internal data bus Register buffer 12 16-bit timer register TB1REG0H/L 16-bit comparator (CP12) TB1MOD φT1 φT4 φT16 Selector Match detection Intenal data bus 16-bit timer register TB1RG1H/L TB0FF1 TB0FF0 Match detection Timer flip-flop control Timer flip-flop Register 1 INTTB01 Interrupt output Register 0 INT
TMP92CM22 3.8.2 Operation (1) Prescaler The 5-bit prescaler generates the source clock for TMRB0. The prescaler clock (φT0) is a divided clock (Divided by 8) from selected clock by the register SYSCR1 of clock gear. This prescaler can be started or stopped using TB0RUN. Counting starts when is set to 1; the prescaler is cleared to zero and stops operation when is cleared to 0. Table 3.8.2 show prescaler output clock resolution. Table 3.8.
TMP92CM22 (3) Timer registers (TB0RG0H/L and TB0RG1H/L) These two 16-bit registers are used to set the interval time. When the value in the up counter UC10 matches the value set in this timer register, the comparator match detect signal will go active. Setting data for both upper and lower timer registers TB0RG0H/L and TB0RG1H/L is always needed. For example, either using 2-byte data transfer instruction or using 1-byte data transfer instruction twice for lower 8 bits and upper 8 bits in order.
TMP92CM22 (4) Capture registers (TB0CP0H/L, TB0CP1H/L, TB1CP0H/L and TB1CP1H/L) These 16-bit registers are used to latch the values in the up counters UC10. Data in the capture registers should be read both upper and lower all 16 bits. For example, using 2-byte data transfer instruction or using 1-byte data transfer instruction twice for lower 8 bits and upper 8 bits in order.
TMP92CM22 (6) Comparators (CP10 and CP11) CP10 and CP11 are 16-bit comparators which compare the value in the up counter UC10 with the value set in TB0RG0H/L or TB0RG1H/L respectively, in order to detect a match. If a match is detected, the comparator generates an interrupt (INTTB00 or INTTB01 respectively). (7) Timer flip-flop (TB0FF0 and TB0FF1) These flip-flops (TB0FF0 and TB0FF1) are inverted by the match detect signals from the comparators and the latch signals to the capture registers.
TMP92CM22 3.8.3 SFRs TMRB0 Run Register 7 TB0RUN (1180H) Bit symbol Function 5 4 − TB0RDE Read/Write After reset 6 3 I2TB0 R/W 0 Double buffer 2 1 0 TB0PRUN TB0RUN R/W 0 0 Always write “0”. 0: Disable R/W 0 0 IDLE2 TMRB0 0: Stop Prescaler 1: Operate 0: Stop and clear 1: Enable Up counter UC10 1: Run (Count) Count operation 0 Stop and clear 1 Count Note: The values of bits 1, 4, and 5 of TB0RUN are undefined when read.
TMP92CM22 TMRB0 Mode Register 7 TB0MOD (1182H) Bit symbol After reset Read-modify -write instruction is prohibited − Read/Write Function 6 5 4 3 2 1 0 − TB0CP0I TB0CPM1 TB0CPM0 TB0CLE TB0CLK1 TB0CLK0 0 0 R/W 0 Always write “0”. W 0 Always write “0”.
TMP92CM22 TMRB1 Mode Register 7 TB1MOD (1192H) Bit symbol After reset Read-modify -write instruction is prohibited TB1CT1 Read/Write Function 6 5 4 3 2 1 0 TB1ET1 TB1CP0I TB1CPM1 TB1CPM0 TB1CLE TB1CLK1 TB1CLK0 0 0 R/W 0 W 0 TB1FF1 Inversion trigger 0: Trigger disable 1: Trigger enable Invert when UC12 is loaded into TB1CP1H/L Invert when UC12 matches with TB1RG1H/L R/W 1 Software capture control 0 0 0 Capture timing 00: 0: Software 01: capture 1: Undefined 10: 11: Disable INT
TMP92CM22 TMRB0 Flip-flop Control Register 7 TB0FFCR (1183H) Bit symbol − Read/Write After reset 6 5 4 − TB0C1T1 TB0C0T1 W 1 3 2 1 TB0E1T1 TB0E0T1 TB0FFC1 R/W 1 0 0 0 TB0FFC0 W* 0 0 1 1 TB0FF0 inversion trigger TB0FF0 control -write 0: Trigger disable 00: Invert instruction is prohibited 1: Trigger enable Read-modify Function Always write “11”.
TMP92CM22 TMRB1 Flip-flop Control Register 7 TB1FFCR (1193H) Bit symbol TB1FF1C1 Read/Write After reset 6 5 4 TB1FF1C0 TB1C1T1 TB1C0T1 W* 1 3 2 1 TB1E1T1 TB1E0T1 TB1FFC1 R/W 1 0 0 0 TB1FFC0 W* 0 0 1 1 Read-modify Function TB1FF1 control TB1FF0 inversion trigger TB1FF0 control -write 00: Invert 0: Trigger disable 00: Invert instruction is prohibited 01: Set 1: Trigger enable 10: Clear Invert when the UC12 value is loaded into TB1CP1H/L.
TMP92CM22 7 TB0RG0L (1188H) TB0RG0H (1189H) TB0RG1L (118AH) TB0RG1H (118BH) TB0CP0L (118CH) 6 TMRB0 register 5 4 bit Symbol − Read/Write W After reset Undefined bit Symbol − Read/Write W After reset Undefined bit Symbol − Read/Write W After reset Undefined bit Symbol − Read/Write W After reset Undefined bit Symbol − Read/Write W After reset Undefined 2 1 0 3 2 1 0 − TB0CP0H bit Symbol (118DH) Read/Write W After reset TB0CP1L (118EH) 3 Undefined bit Symbol
TMP92CM22 3.8.4 Operation in Each Mode (1) 16-bit interval timer mode Generating interrupts at fixed intervals in this example, the interval time is set the timer register TB0RG1H/L to generate the interrupt INTTB01. 7 6 5 4 3 2 1 0 TB0RUN INTETB0 ← 0 0 X X − 0 X 0 ← X 1 0 0 X 0 0 0 Stop TMRB0. Enable INTTB01 and set interrupt level 4. Disable INTTB00. TB0FFCR ← 1 1 0 0 0 0 1 1 Disable the trigger. TB0MOD ← 0 0 1 0 0 1 * Set input clock to prescaler clock, and set capture function to disable.
TMP92CM22 (3) 16-bit programmable pulse generation (PPG) output mode Square wave pulses can be generated at any frequency and duty ratio. The output pulse may be either low active or high active. The PPG mode is obtained by inversion of the timer flip-flop TB0FF0 that is to be enabled by the match of the up counter UC10 with timer register TB0RG0H/L or TB0RG1H/L and to be output to TB0OUT0. In this mode, the following conditions must be satisfied.
TMP92CM22 The following block diagram illustrates this mode. TB0RUN TB0OUT0 (PPG output) Selector TB0IN0 φT1 φT4 φT16 16-bit up counter UC10 Clear F/F (TB0FF0) Matching 16-bit comparator 16-bit comparator TB0RG0H/L Selector TB0RG0-WR Register buffer 10 TB0REG1H/L TB0RUN Internal data bus Figure 3.8.
TMP92CM22 (4) Capture function examples Used capture function, they can be applicable in many ways, for example: 1. One-shot pulse output from external trigger pulse 2. Frequency measurement 3. Pulse width measurement 4. Measurement of difference time 1.
TMP92CM22 Example: To output a 2 [ms] one-shot pulse with a 3 [ms] delay to the external trigger pulse via the TB1IN0 pin. * Clock state : Clock gear 1/1 (fc) Setting in Main Set free running. Count using φT1. TB1MOD ← X X 1 0 1 0 0 1 TB1FFCR ← X X 0 0 0 0 1 0 Load into TB1CP0H/L by rising edge of TB1IN0 pin input. Clear TB1FF0 to 0. Disable inversion of TB1FF0. PDCR ← X X X X − 1 − − PDFC ← X X X X − 1 X X INTE45 ← X − − − X 1 0 0 INTETB1 ← X 0 0 0 X 0 0 0 Enable INT4.
TMP92CM22 Count clock (Prescaler output clock) c+p c TB1IN0 input (External trigger pulse) Load into capture register TB1CP0H/L generate INT4. Generate INTTB11. Load into capture register 1 TB1CP1H/L. Match with TB1RG1H/L Inversion enable Timer output TB1OUT0 pin Pulse width (p) Set it to disable that inversion caused by loading into TB1CP1H/L. Set it to enable that inversion caused by loading into TB1CP0H/L. Figure 3.8.13 One-shot Pulse Output (without delay) 2.
TMP92CM22 3. Pulse width measurement This mode allows measuring the high level width of an external pulse. While keeping the 16-bit timer/event counter counting (Free running) with the prescaler output clock input, external pulse is input through the TB1IN0 pin. Then the capture function is used to load the UC12 values into TB1CP0H/L and TB1CP1H/L at the rising edge and falling edge of the external trigger pulse respectively. The interrupt INT4 occurs at the falling edge of TB1IN0.
TMP92CM22 4. Measurement of difference time This mode is used to measure the difference in time between the rising edges of external pulses input through TB1IN0 and TB1IN1. Keep the 16-bit timer/event counter (TMRB1) counting (Free running) with the prescaler output clock, and load the UC12 value into TB1CP0H/L at the rising edge of the input pulse to TB1IN0. Then the interrupt INT4 is generated.
TMP92CM22 3.9 Serial Channels (SIO) The TMP92CM22 includes 2 serial I/O channels. Each channel is called SIO0 and SIO1. For both channels either UART Mode (Asynchronous transmission) or I/O interface mode (Synchronous transmission) can be selected. • I/O interface mode Mode 0: For transmitting and receiving I/O data using the synchronizing signal SCLK for extending I/O. Mode 1: 7-bit data • UART mode Mode 2: 8-bit data Mode 3: 9-bit data In mode 1 and mode 2 a parity bit can be added.
TMP92CM22 • Mode 0 (I/O interface mode) Bit0 1 2 3 4 5 6 7 Transfer direction • • • Mode 1 (7-bit UART mode) No parity Start Bit0 1 2 3 4 5 6 Stop Parity Start Bit0 1 2 3 4 5 6 Parity Stop Mode 2 (8-bit UART mode) No parity Start Bit0 1 2 3 4 5 6 7 Stop Parity Start Bit0 1 2 3 4 5 6 7 Parity Stop Start Bit0 1 2 3 4 5 6 7 8 Stop Start Bit0 1 2 3 4 5 6 7 Bit8 Stop Mode 3 (9-bit UART mode) Wakeup If bit8=1, denoted address (Select c
TMP92CM22 3.9.
TMP92CM22 Prescaler φT0 2 4 8 16 32 64 φT2 φT8 φT32 Serial clock generation circuit BR1CR BR1CR BR1ADD UART mode BR1CR Baud rate generater SIOCLK Selector φT8 φT32 Selector φT2 Prescaler Selector φT0 TA0TRG (from TMRA0) SC1MOD0 fio ÷2 SCLK1 input Selector SC1MOD0 I/O interface mode (Shared with PF5) SCLK1 output SC1CR I/O interface mode Interrupt request INTRX1 INTTX1 (Shared with PF5) Receive control SC1MOD0 (UART only
TMP92CM22 3.9.2 Operation of Each Circuit (1) Prescaler There is a 6-bit prescaler for generating a clock to SIO0. The clock selected using SYSCR1 is divided by 8 and input to the prescaler as φT0. The prescaler can be run only case of selecting the baud rate generator as the serial transfer clock. Table 3.9.2 shows prescaler clock resolution into the baud rate generator. Table 3.9.
TMP92CM22 (2) Baud rate generator The baud rate generator is a circuit that generates transmission and receiving clocks that determine the transfer rate of the serial channels. The input clock to the baud rate generator, φT0, φT2, φT8, or φT32, is generated by the 6-bit prescaler which is shared by the timers. One of these input clocks is selected using the BR0CR field in the baud rate generator control register.
TMP92CM22 • Integer divider (N divider) For example, when the fC = 39.3216 MHz, the input clock frequency = φT2, the frequency divider N (BR0CR) = 8, and BR0CR = 0, the baud rate in UART mode is as follows: ∗ Clock state Clock gear: Baud rate = 1/1 (fC) fC/32 8 ÷ 16 = 39.3216 × 106 ÷ 16 ÷ 8 ÷ 16 = 9600 (bps) The N + (16 − K)/16 division function is disabled and setting BR0ADD is invalid. N + (16 − K)/16 divider (UART mode only) Note: • Accordingly, when fC = 31.
TMP92CM22 Table 3.9.3 UART Baud Rate Selection (when using baud rate generater and BR0CR = 0) Unit (kbps) Input Clock fSYS [MHz] Frequency Divider φT0 (fSYS/4) φT2 (fSYS/16) φT8 φT32 (fSYS/64) (fSYS/256) 9.8304 2 76.800 19.200 4.800 1.200 ↑ 4 38.400 9.600 2.400 0.600 ↑ 8 19.200 4.800 1.200 0.300 ↑ 10 9.600 2.400 0.600 0.150 12.2880 5 38.400 9.600 2.400 0.600 ↑ A 19.200 4.800 1.200 0.300 14.7456 2 115.200 28.800 7.200 1.800 ↑ 3 76.800 19.200 4.
TMP92CM22 (3) Serial clock generation circuit This circuit generates the basic clock for transmitting and receiving data. • In I/O interface mode In SCLK output mode with the setting SC0CR = 0, the basic clock is generated by dividing the output of the baud rate generator by 2, as described previously. In SCLK input mode with the setting SC0CR = 1, the rising edge or falling edge will be detected according to the setting of the SC0CR register to generate the basic clock.
TMP92CM22 (6) The receiving buffers To prevent overrun errors, the receiving buffers are arranged in a double-buffer structure. Received data is stored one bit at a time in receiving buffer 1 (which is a shift register). When 7 or 8 bits of data have been stored in receiving buffer 1, the stored data is transferred to receiving buffer 2 (SC0BUF); this causes an INTRX0 interrupt to be generated. The CPU only reads receiving buffer 2 (SC0BUF).
TMP92CM22 Handshake function Use of CTS0 pin allows data to be sent in units of one data format; thus, overrun errors can be avoided. The handshake function is enabled or disabled by the SC0MOD0 setting. When the CTS0 pin condition is high level, after completed the current data transmission, data transmission is halted until the CTS0 pin state is low again. However, the INTTX0 interrupt is generated, and it requests the next send from data to the CPU.
TMP92CM22 (9) Transmission buffer The transmission buffer (SC0BUF) shifts out and sends the transmission data written from the CPU form the least significant bit in order. When all the bits are shifted out, the transmission buffer becomes empty and generates an INTTX0 interrupt. (10) Parity control circuit When SC0CR in the serial channel control register is set to 1, it is possible to transmit and receive data with parity. However, parity can be added only in 7-bit UART mode or 8-bit UART mode.
TMP92CM22 2. Parity error The parity generated for the data shifted into receiving buffer 2 (SC0BUF) is compared with the parity bit received via the RXD pin. If they are not equal, a parity error is generated. 3. Framing error The stop bit for the received data is sampled three times around the center. If the majority of the samples are 0, a framing error is generated. (12) Timing generation 1.
TMP92CM22 3.9.
TMP92CM22 SC1MOD0 (120AH) Bit symbol 7 6 5 4 TB8 CTSE RXE WU Read/Write After reset Function 3 2 1 0 SM1 SM0 SC1 SC0 0 0 0 0 R/W 0 Transfer data bit8 0 0 Handshake Receive function control control 0: Receive 0: CTS disable 1: Receive disable enable 1: CTS 0 Wakeup function Serial transmission mode Serial transmission clock (UART) 0: Disable 00: I/O interface mode 00: Timer A0 trigger 1: Enable 01: 7-bit UART mode 01: Baud rate generator 10: 8-bit UART mode 11: 9-bit UART
TMP92CM22 SC0CR (1201H) 7 6 Bit symbol RB8 EVEN Read/Write R After reset Undefined Function Received data bit8 5 4 3 2 1 PE OERR PERR FERR SCLKS R/W 0 Parity 0: Odd 1: Even R (Cleared to 0 when read) 0 Parity addition 0 0 Parity IOC R/W 0 0 0 0: SCLK0 1: Error Overrun 0 0: Baud rate generator 1: SCLK0 pin input Framing 1: SCLK0 0: Disable 1: Enable I/O interface input clock selection 0 Baud rate generator 1 SCLK0 pin input Edge selection for SCLK0 pin (I/O mode) 0
TMP92CM22 SC1CR (1209H) 7 6 Bit symbol RB8 EVEN Read/Write R After reset Undefined Function Received data bit8 5 4 3 2 1 PE OERR PERR FERR SCLKS R/W 0 Parity 0: Odd 1: Even R (Cleared to 0 when read) 0 Parity addition 0 0 Parity IOC R/W 0 0 0 0: SCLK1 1: Error Overrun 0 0: Baud rate generator 1: SCLK1 pin input Framing 1: SCLK1 0: Disable 1: Enable I/O interface input clock selection 0 Baud rate generator 1 SCLK1 pin input Edge selection for SCKL1 pin (I/O mode) 0
TMP92CM22 Bit symbol 6 5 4 − BR0ADDE BR0CK1 BR0CK0 Read/Write After reset Function 0 Always write “0”.
TMP92CM22 BR1CR (120BH) Bit symbol 7 6 5 4 − BR1ADDE BR1CK1 BR1CK0 Read/Write 0 Always write “0”.
TMP92CM22 7 6 5 4 3 2 1 TB7 TB6 TB5 TB4 TB3 TB2 TB1 0 TB0 (for transmission) SC0BUF (1200H) Note: 7 6 5 4 3 2 1 RB7 RB6 RB5 RB4 RB3 RB2 RB1 0 RB0 (for receiving) Prohibit read-modify-write for SC0BUF Figure 3.9.13 Serial Transmission/Receiving Buffer Register (for SIO0 and SC0BUF) SC0MOD1 Bit symbol (1205H) Read/Write After reset Function 7 6 I2S0 FDPX0 5 4 3 2 1 0 R/W 0 0 IDLE2 Duplex 0: Stop 0: Half 1:Run 1: Full Figure 3.9.
TMP92CM22 3.9.4 Operation in Each Mode (1) Mode 0 (I/O interface mode) This mode allows an increase in the number of I/O pins available for transmitting data to or receiving data from an external shift register. This mode includes the SCLK output mode to output synchronous clock SCLK and SCLK input mode to input external synchronous clock SCLK.
TMP92CM22 1. Transmission In SCLK output mode 8-bit data and a synchronous clock are output on the TXD0 and SCLK0 pins respectively each time the CPU writes the data to the transmission buffer. When all data is outputted, INTES0 will be set to generate the INTTX0 interrupt. Timing of writing transmission data SCLK0 output ( = 0 rising mode) (Internal clock timinig) SCLK0 output ( = 1 falling mode) TXD0 Bit0 Bit1 Bit6 Bit7 ITX0C (INTTX0 interrupt request) Figure 3.9.
TMP92CM22 2. Receiving In SCLK output mode, the synchronous clock is outputted from SCLK0 pin and the data is shifted to receiving buffer 1. This starts when the receive interrupt flag INTES0 is cleared by reading the received data. When 8-bit data are received, the data will be transferred to receiving buffer 2 (SC0BUF according to the timing shown below) and INTES0 will be set to generate INTRX0 interrupt. The outputting for the first SCLK0 starts by setting SC0MOD0 to 1.
TMP92CM22 3. Transmission and receiving (Full duplex mode) When the full duplex mode is used, set the level of receive interrupt to “0” and set enable the interrupt level (1 to 6) to the transfer interrupts. In the transfer interrupt program, the receiving operation should be done like the below example before setting the next transfer data. Example: Channel 0, SCLK output Baud rate = 9600 bps fC = 4.
TMP92CM22 (2) Mode 1 (7-bit UART mode) 7-bit UART mode is SC0MOD0 to 01. selected by setting serial channel mode register In this mode, a parity bit can be added. Use of a parity bit is enabled or disabled by the setting of the serial channel control register SC0CR bit; whether even parity or odd parity will be used is determined by the SC0CR setting when SC0CR is set to 1 (Enabled).
TMP92CM22 (4) Mode 3 (9-bit UART mode) 9-bit UART mode is selected by setting SC0MOD0 to 11. In this mode parity bit cannot be added. In the case of transmission the MSB (9th bit) is programmed to SC0MOD0. In the case of receiving it is stored in SC0CR. When the buffer is written and read, the MSB is read or written first, before the rest of the SC0BUF data. Wakeup function In 9-bit UART mode, the wakeup function for slave controllers is enabled by setting SC0MOD0 to 1.
TMP92CM22 Protocol 1. Select 9-bit UART mode on the master and slave controllers. 2. Set the SC0MOD0 bit on each slave controller to 1 to enable data receiving. 3. The master controller transmits one-frame data including the 8-bit select code for the slave controllers. The MSB (Bit8) is set to “1”. Start Bit0 1 2 3 4 5 6 7 Select code of slave controller 8 Stop “1” 4. Each slave controller receives the above frame. If it matches with own select code, clears bit to “0”. 5.
TMP92CM22 Example: To link two slave controllers serially with the master controller using the system clock fIO as the transfer clock. TXD RXD TXD Master • RXD TXD RXD Slave 1 Slave 2 Select code 00000001 Select code 00001010 Master controller setting Main routine PFCR ← − − − − − − 0 1 PFFC ← − − − − − − X 1 INTES0 ← 1 1 0 0 1 1 0 1 Set PF0 to TXD0, and set PF1 to RXD0 pin. Set INTTX0 to enable, and set interrupt level to level 4.
TMP92CM22 3.9.5 Support for IrDA Mode SIO0 includes support for the IrDA 1.0 infrared data communication specification. Figure 3.9.24 shows the block diagram. Transmission data TXD0 IR modulator IR transmitter & LED IR output SIO0 Modem Receive data IR module RXD0 IR demodulator IR receiver IR input TMP92CM22 Figure 3.9.
TMP92CM22 (3) Data format Format of transmission/receiving must set to data length 8-bit, without parity bit, 1 bit of stop bit. Any other settings don’t guarantee the normal operation. (4) SFR Figure 3.9.27 shows the control register SIRCR. If change setting this register, must set it after set operation of transmission/receiving to disable (Both and of this register should be clear to 0).
TMP92CM22 As the same reason, + (16 − K)/16 division function in the baud rate generator of SIO0 cannot be used to generate 115.2 kbps baud rate. Also when the 38.4 kbps and 1/16 pulse width, + (16 − K)/16 division function cannot be used. Table 3.9.5 shows baud rate and pulse width for (16 − K)/16 division function. Table 3.9.5 Baud Rate and Pulse Width for (16 − K)/16 Division Function Output Pulse Width Baud Rate 115.2 kbps 57.6 kbps 38.4 kbps 19.2 kbps 9.6 kbps 2.
TMP92CM22 3.10 Serial Bus Interface (SBI) The TMP92CM22 has a 1-channel serial bus interface. Serial bus interface (SBI0) include following 2 operation modes. • I2C bus mode (Multi master) • Clocked-synchronous 8-bit SIO mode The serial bus interface is connected to an external device through P91 (SDA) and P92 (SCL) in the I2C bus mode; and through P90 (SCK), P91 (SO), and P92 (SI) in the clocked-synchronous 8-bit SIO mode. Each pin is specified as follows.
TMP92CM22 3.10.2 Control The following registers are used to control the serial bus interface and monitor the operation status.
TMP92CM22 3.10.4 I2C Bus Mode Control Register The following registers are used to control and monitor the operation status when using the serial bus interface (SBI) in the I2C bus mode. Serial Bus Interface Control Register 1 7 SBI0CR1 (1240H) Bit symbol BC2 Read/Write BC1 5 4 BC0 0 0 3 2 ACK W After reset ReadFunction modify-write instruction is prohibited.
TMP92CM22 Serial Bus Interface Control Register 2 SBI0CR2 (1243H) Bit symbol 6 MST TRX Read/Write After reset Readmodify-write instruction is prohibited.
TMP92CM22 Serial Bus Interface Status Register SBI0SR (1243H) Bit symbol 7 6 5 4 MST TRX BB PIN Read/Write After reset ReadFunction modify-write instruction is prohibited.
TMP92CM22 Serial Bus Interface Baud Rate Register 0 SBI0BR0 (1244H) Readmodify-write 7 6 Bit symbol − I2SBI0 Read/Write W R/W After reset 0 Function instruction is prohibited. Always write “0”. 5 4 3 2 1 0 0 IDLE2 0: Stop 1: Run Operation during IDLE 2 mode 0 Stop 1 Run Serial Bus Interface Baud Rate Register 1 7 SBI0BR1 (1245H) Read- Bit symbol modify-write Function instruction is prohibited.
TMP92CM22 3.10.5 Control in I2C Bus Mode (1) Acknowledge mode specification Set the SBI0CR1 to 1 for operation in the acknowledge mode. The TMP92CM22 generates an additional clock pulse for an acknowledge signal when operating in master mode. In the transmitter mode during the clock pulse cycle, the SDA pin is released in order to receive the acknowledge signal from the receiver.
TMP92CM22 2. Clock synchronization In the I2C bus mode, in order to wired-AND a bus, a master device which pulls down a clock line to low level, in the first place, invalidate a clock pulse of another master device which generates a high-level clock pulse. The master device with a high-level clock pulse needs to detect the situation and implement the following procedure. The TMP92CM22 has a clock synchronization function for normal data transfer even when more than one master exists on the bus.
TMP92CM22 (6) Transmitter/receiver selection Set the SBI0CR2 to “1” for operating the TMP92CM22 as a transmitter. Clear the to “0” for operation as a receiver.
TMP92CM22 (8) Interrupt service requests and interrupt cancellation When a serial bus interface interrupt request 0 (INTSBE0) occurs, the SBI0SR2 is cleared to “0”. During the time that the SBI0SR2 is “0”, the SCL line is pulled down to the low level. The is cleared to “0” when end of transmission or receiving 1 word of data. And when writing data to SBI0DBR or reading data from SBI0DBR, is set to “1”. The time from the being set to “1” until the SCL line is released takes tLOW.
TMP92CM22 The TMP92CM22 compares the levels on the bus’s SDA line with those of the internal SDA output on the rising edge of the SCL line. If the levels do not match, arbitration is lost and SBI0SR is set to “1”. When SBI0SR is set to “1”, SBI0SR are cleared to “00” and the mode is switched to slave receiver mode. Thus, clock output is stopped in data transfer after setting = “1”.
TMP92CM22 (14) Software reset function The software reset function is used to initialize the SBI circuit, when SBI is rocked by external noises, etc. When write first “10” next “01” to SBI0CR2, reset signal is inputted to serial bus interface circuit, and circuit is initialized. All command registers except SBI0CR2 and status flag except SBI0CR2 are initialized to value of just after reset.
TMP92CM22 3.10.6 Data Transfer in I2C Bus Mode (1) Device initialization In first, set the SBI0BR1, SBI0CR1. Set SBI0BR1 to “1” and clear bits 7 to 5 and 3 in the SBI0CR1 to “0”. Next, set a slave address and the ( = “0” when an addressing format) to the I2C0AR. And, write “000” to SBI0CR2, “1” to , “10” to and “00” to . Set initialization status to slave receiver mode by this setting.
TMP92CM22 SCL line 1 2 3 4 5 6 7 8 SDA line A6 A5 A4 A3 A2 A1 A0 R/ W Start condition 9 ACK Acknowledge signal from a slave device Slave address + Direction bit INTSBE0 interrupt request Output of master Output of slave Figure 3.10.13 Start Condition and Slave Address Generation (3) 1-word data transfer Check the by the INTSBE0 interrupt process after the 1-word data transfer is completed, and determine whether the mode is a master or slave. 1.
TMP92CM22 When the is “0” (Receiver mode) When the next transmitted data is other than 8 bits, set and read the received data from SBI0DBR to release the SCL line (Data which is read immediately after a slave address is sent is undefined). After the data is read, becomes “1”. Serial clock pulse for transferring new 1 word of data is defined SCL and outputs “L” level from SDA pin with acknowledge timing.
TMP92CM22 2. If = 0 (Slave mode) In the slave mode the TMP92CM22 operates either in normal slave mode or in slave mode after losing arbitration. In the slave mode, an INTSBE0 interrupt request generate when the TMP92CM22 receives a slave address or a GENERAL CALL from the master device, or when a GENERAL CALL is received and data transfer is completed, or after matching received address. In the master mode, the TMP92CM22 operates in a slave mode if it losing arbitration.
TMP92CM22 (4) Stop condition generation When SBI0SR = 1, the sequence for generating a stop condition is started by writing “111” to SBI0CR2 and “0” to SBI0CR2. Do not modify the contents of SBI0CR2 until a stop condition has been generated on the bus. When the bus’s SCL line has been pulled low by another device, the TMP92CM22 generates a stop condition when the other device has released the SCL line and SDA pin rising.
TMP92CM22 (5) Restart Restart is used during data transfer between a master device and a slave device to change the data transfer direction. The following description explains how to restart when this device is in the master mode. Clear the SBI0CR2 to “000” and set the SBI0CR2 to “1” to release the bus. The SDA line remains the high level and the SCL pin is released. Since a stop condition is not generated on the bus, other devices assume the bus to be in a busy state.
TMP92CM22 3.10.7 Clocked-synchronous 8-bit SIO Mode Control The following registers are used to control and monitor the operation status when the serial bus interface (SBI) is being operated in clocked synchronous 8-bit SIO mode. Serial Bus Interface 0 Control Register 1 SBI0CR1 (1240H) Bit symbol 6 SIOS SIOINH Read/Write After reset Readmodify-write instruction is prohibited.
TMP92CM22 Serial Bus Interface 0 Control Register 2 7 SBI0CR2 (1243H) 6 5 4 Bit symbol 3 2 SBIM1 SBIM0 Read/Write 1 0 − − W After reset 0 0 Serial bus interface operation mode selection 00: Port mode 01: SIO mode 2 10: I C bus mode 11: (Reserved) ReadFunction modify-write instruction is prohibited. Note 1: Set the SBI0CR1 to “000” before switching to a clocked-synchronous 8-bit SIO mode. Note 2: Please always write “00” to SBICR2<1:0>.
TMP92CM22 (1) Serial Clock 1. Clock source SBI0CR1 is used to select the following functions: Internal clock In internal clock mode one of seven frequencies can be selected. The serial clock signal is output to the outside on the SCK pin.
TMP92CM22 2. Shift edge Data is transmitted on the leading edge of the clock and received on the trailing edge. Leading edge shift Data is shifted on the leading edge of the serial clock (on the falling edge of the SCK pin input/output). Trailing edge shift Data is shifted on the trailing edge of the serial clock (on the rising edge of the SCK pin input/output).
TMP92CM22 (2) Transfer modes The SBI0CR1 is used to select a transmit, receive or transmit/receive mode. 1. 8-bit transmit mode Set a control register to a transmit mode and write transmission data to the SBI0DBR. After the transmit data has been written, set the SBI0CR1 to “1” to start data transfer. The transmitted data is transferred from the SBI0DBR to the shift register and output, starting with the least significant bit (LSB), via the SO pin and synchronized with the serial clock.
TMP92CM22 Clear SCK pin (Output) * a0 SO pin a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 b6 b7 INTSBE0 interrupt request a SBI0DBR b Writing transmission data (a) Internal clock Clear SCK pin (Input) * a0 SO pin a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 INTSBE0 interrupt request a SBI0DBR b Writing transmission data (b) External clock Figure 3.10.
TMP92CM22 SCK pin SO pin Bit6 Bit7 tSODH = 3.5/fSYS [s] (Min) Figure 3.10.26 Transmission Data Hold Time at End Transmit 2. 8-bit receive mode Set the control register to receive mode and set the SBI0CR1 to “1” for switching to receive mode. Data is received into the shift register via the SI pin and synchronized with the serial clock, starting from the least significant bit (LSB). When the 8-bit data is received, the data is transferred from the shift register to the SBI0DBR.
TMP92CM22 Clear SCK pin (Output) a0 SI pin a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 INTSEB0 interrupt request a SBI0DBR Read receive data b Read receive data Figure 3.10.27 Receiver Mode (Example: Internal clock) 3. 8-bit transmit/receive mode Set a control register to a transmit/receive mode and write data to the SBI0DBR. After the data is written, set the SBI0CR to “1” to start transmitting/receiving.
TMP92CM22 Clear SCK pin (Output) SO pin * a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 c0 c1 c2 c3 c4 c5 c6 c7 d0 d1 d2 d3 d4 d5 d6 d7 SI pin INTSBE0 interrupt SBI0DBR Interrupt a c b d Write transmission data (b) Write transmission data (a) Read receiving data (c) Read receiving data (d) Figure 3.10.
TMP92CM22 3.11 Analog/Digital Converter The TMP92CM22 incorporates a 10-bit successive approximation-type analog/digital converter (AD converter) with 8-channel analog input. Figure 3.11.1 is a block diagram of the AD converter. The 8-channel analog input pins (AN0 to AN7) are shared with the input-only port G so they can be used as an input port.
TMP92CM22 3.11.1 Analog/Digital Converter Registers The AD converter is controlled by the three AD mode control registers: ADMOD0, ADMOD1, and ADMOD2. The eight AD conversion data result registers (ADREG0H/L to ADREG7H/L) store the results of AD conversion. Figure 3.11.2 shows the registers related to the AD converter.
TMP92CM22 AD Mode Control Register 1 ADMOD1 (12B9H) Bit symbol 7 6 5 4 VREFON I2AD − − Read/Write After reset Function 3 2 1 0 − ADCH2 ADCH1 ADCH0 0 0 0 R/W 0 VREF application control 0 0 IDLE2 Always write “0”. 0: Stop 0 0 Always write Always “0”. write “0”.
TMP92CM22 AD Conversion Result Register 0 Low 7 ADREG0L (12A0H) Bit symbol 6 ADR01 5 4 3 2 1 0 ADR00 ADR0RF Read/Write R After reset Undefined 0 Stores lower 2 bits of AD conversion result AD conversion Function R data storage flag 1: Conversion result stored AD Conversion Result Register 0 High ADREG0H (12A1H) Bit symbol 7 6 5 4 3 2 1 0 ADR09 ADR08 ADR07 ADR06 ADR05 ADR04 ADR03 ADR02 1 0 Read/Write R After reset Undefined Function Stores upper 8 bits AD conver
TMP92CM22 AD Conversion Result Register 2 Low 7 ADREG2L (12A4H) Bit symbol 6 ADR21 5 4 3 2 1 0 ADR20 ADR2RF Read/Write R After reset Undefined 0 Stores lower 2 bits of AD conversion result.
TMP92CM22 AD Conversion Result Register 4 Low 7 ADREG4L (12A8H) Bit symbol 6 ADR41 5 4 3 2 1 0 ADR40 ADR4RF Read/Write R After reset Undefined 0 Stores lower 2 bits of AD conversion result.
TMP92CM22 AD Conversion Result Register 6 Low 7 ADREG6L (12ACH) Bit symbol 6 ADR61 5 4 3 2 1 0 ADR60 ADR6RF Read/Write R After reset Undefined 0 Stores lower 2 bits of AD conversion result.
TMP92CM22 3.11.2 Description of Operation (1) Analog reference voltage A high-level analog reference voltage is applied to the VREFH pin; a low-level analog reference voltage is applied to the VREFL pin. To perform AD conversion, the reference voltage, the difference between VREFH and VREFL, is divided by 1024 using string resistance. The result of the division is then compared with the analog input voltage.
TMP92CM22 (3) Starting AD conversion To start AD conversion, program “1” to ADMOD0 in AD mode control register 0, or ADMOD1 in AD mode control register 1 and input falling edge on ADTRG pin. When AD conversion starts, the AD conversion busy flag ADMOD0 will be set to “1”, indicating that AD conversion is in progress.
TMP92CM22 3. Channel fixed repeat conversion mode Setting ADMOD0 and ADMOD0 to “10” selects conversion channel fixed repeat conversion mode. In this mode data on one specified channel is converted repeatedly. When conversion has been completed, ADMOD0 is set to “1” and ADMOD0 is not cleared to “0” but held at “1”. INTAD interrupt request generation timing is determined by the setting of ADMOD0.
TMP92CM22 (5) AD conversion time 84 states (8.4 μs at fSYS = 20 MHz) are required for the AD conversion of one channel. (6) Storing and reading the results of AD conversion The AD conversion data upper and lower registers (ADREG0H/L to ADREG7H/L) store the results of AD conversion. (ADREG0H/L to ADREG7H/L are read-only registers.) In channel fixed repeat conversion mode, the conversion results are stored successively in registers ADREG0H/L to ADREG3H/L.
TMP92CM22 Example: 1. Convert the analog input voltage on the AN3 pin and write the result, to memory address 0800H using the AD interrupt (INTAD) processing routine. Setting of main routine 7 6 5 4 3 2 1 0 INTE0AD ← X 1 0 0 − − − − ADMOD1 ← 1 1 0 0 0 0 1 1 Enable INTAD and set it to interrupt level 4. Set pin AN3 to the analog input channel. ADMOD0 ← X X 0 0 0 0 0 1 Start conversion in channel fixed single conversion mode. Interrupt routine processing example 2.
TMP92CM22 3.12 Watchdog Timer (Runaway detection timer) The TMP92CM22 contains a watchdog timer of runaway detecting. The watchdog timer (WDT) is used to return the CPU to the normal state when it detects that the CPU has started to malfunction (Runaway) due to causes such as noise. When the watchdog timer detects a malfunction, it generates a non-maskable interrupt INTWD to notify the CPU of the malfunction. Connecting the watchdog timer output to the reset pin internally forces a reset.
TMP92CM22 3.12.2 Operation The watchdog timer generates an INTWD interrupt when the detection time set in the WDMOD has elapsed. The watchdog timer must be cleared “0” in software before an INTWD interrupt will be generated. If the CPU malfunctions (e.g., if runaway occurs) due to causes such as noise, but does not execute the instruction used to clear the binary counter, the binary counter will overflow and an INTWD interrupt will be generated.
TMP92CM22 3.12.3 Control Registers The watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR. (1) Watchdog timer mode register (WDMOD) 1. Setting the detection time for the watchdog timer in This 2-bit register is used for setting the watchdog timer interrupt time used when detecting runaway. On a reset this register is initialized to WDMOD = 00. The detection time for WDT is 215/fSYS [s]. (The number of system clocks is approximately 65, 536.) 2.
TMP92CM22 WDMOD (1300H) Bit symbol 7 6 5 WDTE WDTP1 WDTP0 Read/Write After reset Function 4 3 2 − I2WDT R/W 1 0 0 RESCR − R/W 0 0 WDT control Select detecting time 1: Enable 1 0 Always write “0” 15 00: 2 /fIO IDLE2 0: Stop 17 01: 2 /fIO 1: Operate 19 10: 2 /fIO 21 0 0 1: Internally connects WDT out to the reset pin Always write “0” 11: 2 /fIO Watchdog timer out control 0 − 1 Connects WDT out to a reset IDLE2 control 0 Stop 1 Operation Watchdog timer detection t
TMP92CM22 4. 4.1 Electrical Characteristics Absolute Maximum Ratings Parameter Symbol Rating Power supply voltage Vcc −0.5 to 4.0 Input voltage VIN −0.5 to Vcc + 0.
TMP92CM22 DC Characteristics (1/2) Vcc = 3.3 ± 0.3 V/fc = 4 to 40 MHz/Ta = −40 to 85°C Parameter Power supply voltage Symbol VCC (DVCC = AVCC) Condition fc = 4 to 40 MHz (fSYS = 125 kHz to 20 MHz) Min 3.0 Typ. Max Unit 3.6 V (DVSS = AVSS = 0 V) Input low voltage VIL0 P00 to P07 (D0 to D7) 0.6 P10 to P17 (D8 to D15) Input low voltage VIL1 P40 to P47 P50 to P57 P60 to P67 0.3 × VCC P76 PD2, PD3 PF0, PF3, PF6, PF7 PG0 to PG7 Input low voltage −0.3 VIL2 V P90 to P92 PA0 to PA2, PA7 0.
TMP92CM22 DC Characteristics (2/2) Vcc = 3.3 ± 0.3 V/fc = 4 to 40 MHz/Ta = −40 to 85°C Parameter Condition Symbol Min Typ. Max Output low voltage VOL IOL = 1.6 mA Output high voltage VOH IOH = −400 μA Input leakage current ILI 0.0 ≤ Vin ≤ VCC 0.02 5 ILO 0.2 ≤ Vin ≤ VCC − 0.2 0.05 10 VSTOP VIL2 = 0.2 × Vcc, VIH2 = 0.8 × Vcc Output leakage current Power down voltage (at STOP, RAM backup) RESET pull-up resistor Programmable pull-up resistor RRST Pin capacitance CIO 0.45 Unit V 2.
TMP92CM22 4.2 AC Characteristics 4.2.1 Basis Bus Cycle Read cycle Vcc = 3.3 ± 0.3 V/fc = 4 to 40 MHz/Ta = −40 to 85°C No. Parameter Symbol Min Max fSYS = fSYS = 20 MHz 125 kHz Unit (fc = 40 MHz) (fc = 4 MHz) 1 OSC period (X1/X2) tOSC 25 250 25 250 ns 2 System clock period (= T) tCYC 50 8000 50 8000 ns 3 CLKOUT low width tCL 0.5T − 15 10 3985 ns 4 CLKOUT high width tCH 0.
TMP92CM22 (1) Read cycle (0 waits, fc = fOSCH, fFPH = fc/1) tOSC X1 tCYC tCL tCH CLKOUT tKT tTK WAIT A0 to A23 tAD CSx tHA R/ W tAR tRK tHR RD tRR tRD D0 to D31 Note: Data input The phase relation between X1 input signal and the other signals is unsettled. The timing chart above is an example.
TMP92CM22 (2) Write cycle (0 waits, fc = fOSCH, fFPH = fc/1) tOSC X1 tCYC tCL tCH CLKOUT tTK tKT WAIT A0 to A23 CSx R/ W tAW tWA tWK WRxx tWW tDW D0 to D31 tWD Data output tRDO RD Note: The phase relation between X1 input signal and the other signals is unsettled. The timing chart above is an example.
TMP92CM22 (3) Read cycle (1 wait) CLKOUT WAIT A0 to A23 tAD3 CSx R/ W RD tRR3 tRD3 Data input D0 to D31 (4) Write cycle (1 wait) CLKOUT WAIT A0 to A23 CSx R/ W WRxx tWW3 tDW3 D0 to D31 tRD0 Data output RD 92CM22-221 2007-02-16
TMP92CM22 4.2.2 Page ROM Read Cycle (1) 3-2-2-2 mode Vcc = 3.3 ± 0.3 V/fc = 4 to 40 MHz/Ta = −40 to 85°C No. Parameter Symbol Min Max fSYS = fSYS = Unit 20 MHz 125 kHz (fc = 40 MHz) (fc = 4 MHz) 1 System clock period ( = T) tCYC 8000 50 8000 ns 2 A0, A1 → D0 to D31 input tAD2 2.0T − 50 50 15950 ns 3 A2 to A23 → D0 to D31 input tAD3 3.0T − 50 100 23950 ns 4 RD falling → D0 to D31 input tRD3 2.
TMP92CM22 4.3 AD Conversion Characteristics Parameter Symbol Min Typ. Analog reference voltage (+) VREFH VCC − 0.2 VCC VCC Analog reference voltage (−) VREFL VSS VSS VSS + 0.2 AD converter power supply voltage AVCC VCC VCC VCC AD converter power supply ground AVSS VSS VSS Analog input voltage AVIN VREFL Analog current for analog reference voltage IREF = 1 Analog current for analog reference voltage = 0 ET Total error (Include quantize error of ± 0.5 LSB ) 4.
TMP92CM22 4.5 Serial Channel Timing (I/O interface mode) Note: Symbol “X” in the following table means the period of clock “fSYS”, it’s same period of the system clock “fSYS” for CPU core. The period of fSYS depends on the clock gear setting or changing high-speed oscillator/low-speed oscillator and so on. (1) SCLK input mode Parameter fSYS = 20 MHz (fc = 40 MHz) Variable Symbol Min SCLK period Max Min Max fSYS = 125 kHz (fc = 4 MHz) Min Unit Max tSCY 16X 0.
TMP92CM22 tSCY SCLK Output mode/ input rising mode SCLK (Input falling mode) tOSS Output data TXD tOHS 0 tSRD Input data RXD 4.6 2 3 2 Valid 3 Valid 1 tHSR tRDS 1 Valid 0 Valid Interrupt, Capture Note: Symbol “X” in the following table means the period of clock “fSYS”, it’s same period of the system clock “fSYS” for CPU core. The period of fSYS depends on the clock gear setting or changing high-speed oscillator/low-speed oscillator and so on.
TMP92CM22 4.7 Recommended Oscillation Circuit TMP92CM22 is evaluated by below oscillator vender. When selecting external parts, make use of this information. Note 1: Total loads value of oscillation is sum of external (or internal) loads (C1 and C2) and floating loads of actual assemble board. There is a possibility of miss operating using C1 and C2 values in below table. When designing board, it should design minimum length pattern around oscillator.
TMP92CM22 (2) TMP92CM22 recommended ceramic oscillator: Murata Manufacturing Co., Ltd. Following table shows circuit parameter recommended. IC Name Oscillation Frequency [MHz] Type (Old number) Parameter of Elements C1 [pF] C2 [pF] Rf [Ω] Rd [Ω] CSTCR4M00G55-R0 (New and old is same product No.) (39) (39) Open 0 SMD Lead CSTLS4M00G56-B0 (CSTS0400MG06) (47) (47) Open 0 CSTCR6M00G55-R0 (New and old is same product No.
TMP92CM22 5. Table of Special Function Registers (SFRs) The SFRs include the I/O ports and peripheral control registers allocated to the 8 Kbytes address space from 000000H to 001FFFH.
TMP92CM22 Table 5.
TMP92CM22 [2] Interrupt controller Address Name 00D0H INTE12 1H INTE3 2H 3H 4H INTETA01 5H INTETA23 [3] Address Name 00E0H INTE45 1H INTETB1 Address Name 00F0H INTE0AD 1H INTETC01 DMA controller Address 2H INTETBO1 2H INTETC23 1H DMA1V 2H DMA2V 3H INTESB0 4H 3H INTETC45 3H DMA3V 4H INTETC67 4H DMA4V 5H 5H DMA5V 6H 6H 5H SIMC 6H IIMC 7H 7H 7H INTWDT 8H INTETB0 8H 9H 9H 8H INTCLR 9H AH INTETBO0 AH BH INTES0 CH INTES1 DH BH AH IIMC2 BH CH CH CH DH DH DH EH INTEP0 FH
TMP92CM22 [6] 8-bit timer [7] 16-bit timer Address Address Name 1100H TA01RUN [8] UART/SIO Name Address Name Address Name 1180H TB0RUN 1H 1190H TB1RUN 1H 1200H SC0BUF 1H SC0CRS 2H TA0REG 2H TB0MOD 2H TB1MOD 2H C0MOD0 3H TA1REG 3H TB0FFCR 4H 3H TB1FFCR 3H BR0CR 4H 4H BR0ADD 5H 5H 6H 6H 6H 5H SC0MOD1 6H 7H 7H 7H 7H SIRCR 8H TA23RUN 8H TB0RG0L 9H TB0RG0H 8H TB1RG0L 9H TB1RG0H 8H SC1BUF 9H SC1CR AH TB0RG1L BH TB0RG1H AH TB1RG1L BH TB1RG1H AH SC1MOD0 BH BR1CR CH TB0CP0L
TMP92CM22 (1) I/O port (1/3) Symbol P1 Name Port 1 Address 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 0004H R/W Data from external port (Output latch register is cleared to “0”) P47 P4 Port 4 P46 P45 P44 0010H P43 P42 P41 P40 R/W Data from external port (Output latch register is cleared to “0”) P57 P5 Port 5 P56 P55 P54 0014H P53 P52 P51 P50 R/W Data from external port (Output latch register is cleared to “0”) P67 P6 Port 6 P66 P65 P64 0018H P63 P62 P6
TMP92CM22 I/O port (2/3) Symbol Name Port 1 P1CR control register Address 0006H (Prohibit RMW) 7 6 5 4 3 2 1 0 P17C P16C P15C P14C P13C P12C P11C P10C 0 0 0 0 0 0 0 0 W 0: Input 1: Output P1F Port 1 P1FC function register W 0007H (Prohibit RMW) 0/1 0: Port 1: Data bus (D8 to D15) Port 4 P4CR control register 0012H (Prohibit RMW) P47C P46C P45C P44C P43C P42C P41C P40C 0 0 0 0 P43F P42F P41F P40F 1 1 1 1 P53C P52C P51C P50C 0 0 0 0 P53F P52F
TMP92CM22 I/O port (3/3) Symbol Name Port 9 P9CR control register Address 7 6 5 4 3 0026H (Prohibit RMW) 2 1 0 P92C P91C P90C W 0 0 0 0: Input 1: Output P92F P91F P90F W Port 9 P9FC function register 0 0027H (Prohibit RMW) 0: Port, SI 0 0 0: Port 0: Port, SCK 1: SCL 1: SO, SDA input 1: SCK Note output Note P92ODE Port 9 P9ODE ODE register 0025H (Prohibit RMW) W 0 PC6C Port C PCCR control register PC5C 0 Port C function register 0 0 drain drain PC1C 0 0 0: Input
TMP92CM22 (2) Interrupt control (1/2) Symbol Name Address 7 6 5 4 3 2 INT2 INTE12 INT1 & INT2 enable 00D0H I2C R 0 1: INT2 I2M2 − − 0 − − 0 I2M1 R/W 0 0 I2M0 0 Interrupt request level.
TMP92CM22 Interrupt control (2/2) Symbol Name Address 7 6 5 4 3 2 − INTEP0 INTP0 enable 00EEH − − 0 − − 0 − − 0 − − 0 Always write “0”.
TMP92CM22 (3) DMA controller Symbol DMA0V Name DMA0 start Address 7 6 5 4 3 2 1 0 DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 0 0 0 0 0 DMA1V1 DMA1V0 0 0 DMA2V1 DMA2V0 0 0 DMA3V1 DMA3V0 0 0 DMA4V1 DMA4V0 0 0 DMA5V1 DMA5V0 0 0 DMA6V1 DMA6V0 0 0 DMA7V1 DMA7V0 0 0 R/W 0100H vector 0 DMA0 start vector DMA1V DMA1 start DMA1V5 DMA1V4 DMA1V3 0 0 0 DMA1V2 R/W 0101H vector 0 DMA1 start vector DMA2V DMA2 start DMA2V5 DMA2V4 DMA2V3 DMA2V2 R/W 0
TMP92CM22 (4) Memory controller (1/2) Symbol B0CSL Name Block 0 MEMC control register low Address 7 0140H (Prohibit RMW) B0E 6 5 4 B0WW2 B0WW1 W 1 B0WW0 3 0 0 Write waits 001: 0 waits 010: 1 wait 101: 2 waits 110: 3 waits 111: 4 waits 011: WAIT pin Others: Reserved − − B0REC B0OM1 2 1 0 B0WR2 B0WR1 W 1 B0WR0 0 0 Read waits 001: 0 waits 010: 1 wait 101: 2 waits 110: 3 waits 111: 4 waits 011: WAIT pin Others: Reserved B0OM0 B0BUS1 B0BUS0 W B0CSH Block 0 MEMCT control register high 0
TMP92CM22 Memory controller (2/2) Symbol Name Address 7 Block EX MEMC BEXCSL control register low 6 5 4 3 BEXWW2 BEXWW1 BEXWW0 W 0 1 0 Write waits 001: 0 waits 010: 1 wait 101: 2 waits 110: 3 waits 111: 4 waits 011: WAIT pin Others: Reserved − − − 0158H (Prohibit RMW) Block EX MEMC BEXCSH control register high 0 Always write “0”. 0159H (Prohibit RMW) 0 Always write “0”. 0 Always write “0”.
TMP92CM22 (5) Clock gear Symbol Name Address System SYSCR0 clock 10E0H control 0 7 6 5 4 3 2 − − R/W R/W 1 1 0 GEAR1 GEAR0 0 0 0 Always write “1”. Always write “0”. − GEAR2 R/W 0 1 Always write “0”. Select gear value of high frequency (fc) System SYSCR1 clock 000: fc 10E1H 001: fc/2 control 1 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) − WUPTM1 WUPTM0 HALTM1 R/W 0 clock 1 Always write “0”.
TMP92CM22 (6) 8-bit timer Symbol Name Address TMRA01 TA01RUN RUN register 1100H 7 6 5 4 TA0RDE R/W 0 Double buffer 0: Disable 1: Enable 3 2 I2TA01 TA01PRUN 0 0 IDLE2 TMRA01 UP counter prescaler (UC1) 0: Stop 1: Operate 0: Stop and clear 1: Run (Count up) UP counter (UC0) 8-bit timer register 0 1102H (Prohibit RMW) − W Undefined TA1REG 8-bit timer register 1 1103H (Prohibit RMW) − W Undefined TMRA01 TA01MOD mode register 1104H TA01M0 0 0 PWM01 0 00: 8-bit timer mode 01: 16-bi
TMP92CM22 (7) 16-bit timer (1/2) Symbol Name Address Timer B0 TB0RUN RUN register 1180H 7 6 5 − − R/W Timer B0 TB0MOD mode register 1182H (Prohibit RMW) 0 Always write “0”. 0 Always write “0”. − TB0FFCR flip-flop − control register 1 1 Always write “11”.
TMP92CM22 16-bit timer (2/2) Symbol Name Address 7 6 3 2 TB1RDE − 5 4 I2TB0 TB1PRUN 0 0 R/W Timer B1 TB1RUN RUN 0 1190H register Double IDLE2 0: Stop 0: Disable 1: Operate 1: Enable TB1CT1 TB1ET1 R/W Timer B1 TB1MOD mode register 0 TB1RUN R/W Always write “0”.
TMP92CM22 (8) UART/Serial channel (1/2) Symbol Name Address Serial SC0BUF channel 0 buffer register 1200H (Prohibit RMW) Serial SC0CR channel 0 control register 1201H 7 6 RB7 TB7 RB6 TB6 RB8 R Undefined EVEN Receive data bit8 5 PE R/W 0 0 Parity 0: Odd 1: Even TB8 4 3 2 RB5 RB4 RB3 RB2 TB5 TB4 TB3 TB2 R(Receiving) / W(Transmission) Undefined Parity 0: Disable 1: Enable CTSE OERR PERR FERR R (Clear o after reading) 0 0 0 1: Error Overrun Parity Framing RXE WU SM1 1 0 RB1 TB1
TMP92CM22 UART/Serial channel (2/2) Symbol Name Address Serial SC1BUF channel 1 buffer register 1208H (Prohibit RMW) SC1CR control register 6 RB6 TB6 5 RB8 R Undefined EVEN 4 3 2 RB5 RB4 RB3 RB2 TB5 TB4 TB3 TB2 R (Receiving)/W (Transmission) 1 0 RB1 TB1 RB0 TB0 Undefined Serial channel 1 7 RB7 TB7 1209H PE R/W 0 Receive data bit8 Parity 0: Odd 1: Even TB8 CTSE 0 Parity 0: Disable 1: Enable OERR PERR FERR R (Clear 0 after reading) 0 0 0 1: Error Overrun Parity Framing SCLKS IO
TMP92CM22 (9) I2C bus/Serial channel (1/2) Symbol Name Address 7 BC2 1240H (Prohibit RMW) 2 I C mode SBI0 SBI0CR1 control register 1 SBI0 SIOS buffer register 1241H (Prohibit RMW) 5 BC1 W 0 0 Number of transfer bits 000: 8 001: 1 010: 2 100: 4 101: 5 110: 6 1240H 0 (Prohibit Transfer RMW) 0: Stop SIO mode 1: Start SBI0DBR 6 DB7 SIOINH 4 3 BC0 ACK 0 R/W 0 2 mode SIOM1 0: Disable 1: Enable SIOM0 0 0 W 0 0 SCK0/ SCK2 SCK1 SWRMON W R/W 0 0 0/1 Setting of the divide value “n” 000:
TMP92CM22 I2C bus/Serial channel (2/2) Symbol Name SBI0 SBI0BR0 baud rate register 0 Address − W 1244H 2 0 (I C mode) (Prohibit Always write “0”. RMW) − 1244H W (SIO mode) 0 (Prohibit Always RMW) write “0”. P4EN R/W 0 SBI0 SBI0BR1 baud rate register 1 7 1245H Clock control 6 5 4 3 2 1 0 I2SBI0 R/W 0 IDLE2 0: Abort 1: Operate − R/W 0 Always write “0”. − W 0 Always write “0”.
TMP92CM22 (10) AD converter (1/2) Symbol Name Address 7 6 5 4 3 EOCF ADBF − − ITM0 R 0 ADMOD0 AD mode control register 0 12B8H 0 0 Always AD AD conversion conversion write “0”. end flag busy flag 0: Busy 0: End 1: Busy 1: End VREFON 0 Always write “0”.
TMP92CM22 AD converter (2/2) Symbol Name Address AD result ADREG4L register 4 low register 4 high register 5 Low register 5 high register 6 low register 6 high register 7 low register 7 high 0 ADR4RF 0 ADR47 ADR46 ADR45 ADR44 ADR43 ADR42 R 12AAH ADR50 ADR5RF R R Undefined 0 ADR59 ADR58 ADR57 ADR56 12ABH ADR55 ADR54 ADR53 ADR52 R Undefined ADR61 12ACH ADR60 ADR6RF R R Undefined ADR69 0 ADR68 ADR67 ADR66 12ADH ADR65 ADR64 ADR63 ADR62 R Undefined ADR71 12AEH
TMP92CM22 (11) Watchdog timer Symbol Name Address 7 6 5 3 2 1 0 WDTE WDTP1 WDTP0 4 − I2WDT RESCR − 0 0 0 R/W 1 WDT WDMOD mode 1300H register WDT control 1: Enable WDCR WDT 1301H control (Prohibit RMW) register 0 R/W Select detecting time 15 00: 2 /fIO 17 01: 2 /fIO 19 10: 2 /fIO 21 11: 2 /fIO Always write “0”. 0 0 1: Internally Always connects write “0”. 0: Stop WDT out 1: Operate to the reset pin.
TMP92CM22 6. Port Section Equivalent Circuit Diagram ■ Reading the circuit diagram Basically, the gate symbols written are the same as those used for the standard CMOS logic IC [74HCXX] series. The dedicated signal is described below. STOP: This signal becomes active “1” when the halt mode setting register is set to the STOP mode and the CPU executes the HALT instruction. When the drive enable bit is set to “1”, however, STOP remains at “0”.
TMP92CM22 ■ P70 ( RD ), P71 ( WRLL ), P72 ( WRLU ), P73, P74 (CLKOUT), P75 ( R/ W ), P80 ( CS0 ), P81 ( CS1 ), P82 ( CS2 ), and P83 ( CS3 ) VCC Output data P-ch Output Stop ■ N-ch PA0, PA1, PA2, and PA7 VCC Input Input data ■ P91 (SO/SDA) and P92 (SI/SCL) VCC Output data P-ch Open-drain output enable N-ch Stop I/O Input data Input enable 92CM22-252 2007-02-16
TMP92CM22 ■ PF0 (TXD0) and PF3 (TXD1) VCC Output data P-ch Open-drain output enable N-ch Stop I/O Input data Input enable ■ PG0 (AN0), PG1 (AN1), PG2 (AN2), PG3 (AN3/ ADTRG ), PG4 (AN4), PG5 (AN5), PG6 (AN6), and PG7 (AN7) Analog input channel select P-ch Analog input Input N-ch Input data Input enable ■ RESET VCC 100 kΩ (Typ.
TMP92CM22 ■ X1 and X2 Clock Oscillator X2 High-frequency oscillation enable N-ch P-ch X1 ■ VREFH and VREFL VREFON P-ch VREFH String resistance VREFL ■ AM0 and AM1 Input Input data ■ NMI Input NMI Schmitt 92CM22-254 2007-02-16
TMP92CM22 7. Points to Note and Restrictions (1) Notation 1. The notation for built-in I/O registers is as follows register symbol . Example: 2. TA01RUN denotes bit TA0RUN of register TA01RUN. Read-modify-write instructions (RMW) An instruction in that the CPU reads data from memory and writes the data to the same memory location by using one instruction. • Example 1: SET 3, (TA01RUN) … Set bit3 of TA01RUN. Example 2: INC 1, (100H) … Increment the data at 100H.
TMP92CM22 (2) Points to note a) AM0 and AM1 pins This pin is connected to the VCC (Power supply level) or VSS (Ground level) pins. Do not alter the level when the pin is active. b) Reservation area of address area TMP92CM22 don’t include reservation area. c) Warm-up counter The warm-up counter operates when STOP mode is released, even if the system is using an external oscillator.
TMP92CM22 8. Package Dimensions P-LQFP100-144-0.
TMP92CM22 92CM22-258 2007-02-16
