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TMP92CZ26AXBG

Data Book

32bit Micro controller

TLCS-900/H1 series

TMP92CZ26AXBG

Rev0.2 09/Dec./2005

TENTATIVE

It’s first version technical data sheet.

Since this revision 0.2 is still under working, there may

be some mistakes in it.

When you will start to design, please order the latest

one.

Summary of content (751 pages)

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Data Book 32bit Micro controller TLCS-900/H1 series TMP92CZ26AXBG TENTATIVE It’s first version technical data sheet. Since this revision 0.2 is still under working, there may be some mistakes in it. When you will start to design, please order the latest one. Rev0.2 09/Dec.
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Table of Contents TLCS-900/H1 Devices TMP92CZ26A 1. Outline and Features ････････････････････････････････････････ 92CZ26A-1 2. Pin Assignment and Pin Functions ････････････････････････････ 92CZ26A-6 2.1 Pin Assignment Diagram ････････････････････････････････ 92CZ26A-6 2.2 Pin names and Functions ･･･････････････････････････････ 92CZ26A-8 3. Operation ･･････････････････････････････････････････････････ 92CZ26A-14 3.1 CPU ･･･････････････････････････････････････････････････ 92CZ26A-14 3.
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.12 8 bit timers (TMRA) ･･････････････････････････････････ 92CZ26A-266 3.13 16 bit timer (TMRB) ･･････････････････････････････････ 92CZ26A-294 3.14 Serial channel (SIO) ･･････････････････････････････････ 92CZ26A-315 3.15 Serial Bus Interface (SBI) ･････････････････････････････ 92CZ26A-344 3.16 USB controller ･･････････････････････････････････････ 92CZ26A-366 3.17 SPIC (SPI controller) ･････････････････････････････････ 92CZ26A-477 3.
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TMP92CZ26A CMOS 32-Bit Micro controllers TMP92CZ26AXBG 1. Outline and Features TMP92CZ26A is high-speed advanced 32-bit micro-controller developed for controlling equipment which processes mass data. TMP92CZ26AXBG is housed in a 228-pin BGA package. (1) CPU : 32-bit CPU(High-speed 900/H1 CPU) • Compatible with TLCS-900/L1 instruction code • 16Mbytes of linear address space • General-purpose register and register banks • Micro DMA : 8channels (62.
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TMP92CZ26A (4) (5) External memory expansion • Expandable up to 3.
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TMP92CZ26A (17) Touch screen interface • Built-in Switch of Low-resistor, and available to delete external components for shift change row/column (18) Watch dog timer (19) Melody/alarm generator • Melody: Output of clock 4 to 5461Hz • Alarm: Output of the 8 kinds of alarm pattern • 5 kinds of interval interrupt (20) MMU • Expandable up to 3.
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TMP92CZ26A (28) Stand-by function • Three Halt modes • Each pin status programmable for stand-by mode • Built-in power supply management circuits (PMC) for leak current provision : IDLE2 (programmable), IDLE1, STOP (29) Clock controller • Built-in two blocks of clock doubler (PLL). PLL supplies 48 MHz for USB and 80 MHz for CPU from 10MHz • Clock gear function: Selectable high-frequency clock fc to fc/16 • Clock for Timer (fs = 32.768 kHz) (30) Operating voltage: • Internal VCC= 1.
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TMP92CZ26A (AN0 to AN1)PG0 to PG1 (AN2, MX)PG2 (AN3, MY, ADTRG )PG3 (AN4 to AN5)PG4 to PG5 AVCC, AVSS VREFH, VREFL 10-bit 6ch AD Converter 900/H1 CPU XWA W A XBC B C XDE D E H L (PY)P97 Touch Screen I/F (TSI) (TXD0)P90 (RXD0)P91 SERIAL I/O SIO0 XHL XIX IX I2 S (I2S0) XIY IY XIZ IZ I2 S (I2S1) XSP SP (PX, INT4)P96 (CTS0, SCLK0)P92 (I2S0CKO)PF0 (I2S0DO)PF1 (I2S0WS)PF2 (I2S1CKO)PF3 (I2S1DO)PF4 (I2S1WS)PF5 (SDA)PV6 (SCL)PV7 D+ D(X1USB) PX5 2 SBI (I Cbus) USB 8BIT TIMER (TMRA0)
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TMP92CZ26A 2. Pin Assignment and Pin Functions The assignment of input/output pins for TMP92CZ26A, their names and functions are as follows; 2.1 Pin Assignment Diagram (Top View) Figure 2.1.1 shows the pin assignment of the TMP92CZ26A.
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TMP92CZ26A Table 2.1.1 Pin number and the name Ball No.
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TMP92CZ26A 2.2 Pin names and Functions The names of the input/output pins and their functions are described below. Table 2.2.1 Pin names and functions (1/6) Pin name D0 to D7 P10 to P17 D8 to D15 P40 to P47 A0 to A7 P50 to P57 A8 to A15 P60 to P67 A16 to A23 P70 Number of Pins 8 8 8 8 8 1 1 Functions I/O Data: Data bus D0 to D7. I/O Port 1: I/O port. Input or output is specifiable in units of bit. I/O Data : Data bus D8 to D15. Output Port 4: Output port. Output Address : Address bus A0 to A7.
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TMP92CZ26A Table 2.2.1 Pin names and functions (2/6) Pin name Number of Pins P86 I/O Functions Output Port 86 : Output port. Output Expanded address ZD : Outputs “Low” when address is within specified address area. ND0CE Output Chip select of NAND Flash 0: Outputs “Low” when NAND Flash 0 is enable. P87 Output Port 87 : Output port.
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TMP92CZ26A Table 2.2.1 Pin names and functions (3/6) Pin name PF0 I2S0CKO PF1 I2S0DO PF2 I2S0WS PF3 I2S0WS PF4 I2S1CKO PF5 I2S1WS PF7 SDCLK PG0 to PG1 AN0 to AN1 Number of Pins 1 1 1 1 1 1 1 2 PG2 AN2 1 I/O I/O Output I/O Output I/O Output I/O Output I/O Output I/O Functions Port F0: I/O port. Outputs clock of I2S0. Port F1: I/O port. Outputs data of I2S0. Port F2: I/O port. Outputs word select signal of I2S0. Port F3: I/O port. Outputs clock of I2S1. Port F4: I/O port. Outputs data of I2S1.
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TMP92CZ26A Table 2.2.1 Pin names and functions (4/6) Pin name PK0 LCP0 PK1 LLOAD PK2 LFR PK3 LVSYNC PK4 LHSYNC PK5 LGOE0 PK6 LGOE1 PK7 LGOE2 PL0 to PL7 LD0 to LD7 Number of Pins 1 1 1 1 1 1 1 1 8 PM1 TA1OUT 1 I/O Functions Output Port K0: Output port. Output Signal for LCD driver. Output Port K1: Output port. Output Signal for LCD driver.: Data load signal Output Port K2: Output port. Output Signal for LCD driver. Output Port K3: Output port. Output Signal for LCD driver.
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TMP92CZ26A Table 2.2.1 Pin names and functions (5/6) Pin name PR3 SPCLK PT0 to PT7 LD8 to LD15 PU0 to PU4,PU6 LD16 to LD20,LD22 PU5 LD21 Number of Pins 1 8 6 1 PU7 LD23 SCLK0 I/O Output I/O Output I/O Output I/O Output I/O 1 EO_TRGOUT PV0 I/O Output Output 1 I/O Output Functions Port R3: I/O port. Clock output pin of SD card. Port T0 to T7: I/O port. Data bus for LCD driver: LD8 to LD15. Port U0 to U4 , U6: I/O port Data bus for LCD driver: LD16 to LD20, LD22.
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TMP92CZ26A Table 2.2.1 Pin names and functions (6/6) Pin name Number of Pins I/O Functions Data pin connected to USB. D+, D- 2 I/O In case USB is not used, connect both pins to pull-up(DVCC3A) or pull-down resistor for protect current flows it. CLKOUT 1 Output Internal clock output pin. Operation mode; Fix to AM1=”0”,AM0=”1” for 16 bit external bus starting. AM1,AM0 2 Input Fix to AM1=”1”,AM0=”0” is prohibit to set. Fix to AM1=”1”,AM0=”1” for BOOT (32 bit internal Mask ROM) starting.
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TMP92CZ26A 3. Operation This section describes the basic components, functions and operation of the TMP92CZ26A. 3.1 CPU The TMP92CZ26A contains an advanced high-speed 32-bit CPU (900/H1 CPU) 3.1.1 CPU Outline 900/H1 CPU is high-speed and high-performance CPU based on 900/L1 CPU. 900/H1 CPU has expanded 32-bit internal data bus to process Instructions more quickly. Outline is as follows: Table 3.1.
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TMP92CZ26A 3.1.2 Reset Operation When resetting the TMP92CZ26A microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input Low for at least 20 system clocks (32µs at X1=10MHz). At reset, since the clock doublers (PLL0) is bypassed and clock-gear is set to 1/16, system clock operates at 625 kHz(X1=10MHz). When the Reset has been accepted, the CPU performs the following.
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92CZ26A-16 Figure 3.1.1 TMP92CZ26A Reset timing chart SRxxB SRWR WRxx D0∼15 SRxxB RD D0∼15 CS2 CS0,1, 3 A23∼0 RESET : High-Z DATA-OUT DATA-IN Sampling Sampling fSYS×(15.5∼16.
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TMP92CZ26A This LSI has the restriction for the order of supplying power. Be sure to supply external 3.3V power with 1.5V power is supplied. Power On Stand-by Mode (PMC) Power Off DVCC1A 1.5V Power DVCC1B DVCC1C Power supply is rising with After 1.5V power in 100mS, and stabilizes. Power supply is falling with in 100mS, and stabilizes. After 1.5V power supply is rising, set 3.3V to ON. 3.3V Power supply is falling, set 3.3V to OFF.
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TMP92CZ26A 3.1.3 Setting of AM0 and AM1 Set AM1 and AM0 pins as Table 3.1.2 shows according to system usage. Table 3.1.
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TMP92CZ26A 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP92CZ26A. 000000H Internal I/O (8 Kbyte) Direct area(n) 000100H 64Kbyte area (nn) 001FF0H 002000H 010000H Internal RAM (288 Kbyte) 046000H 04A000H (Internal Back Up RAM 16kbyte) External memory 16Mbyte area (R) F00000H Provisional Emulator Control Area (64kbyte) (−R) (R+) (Note1) (R + R8/16) F10000H (R + d8/16) (nnn) External memory FFFF00H FFFFFFH Vector table (256 Byte) ( = Internal area) Figure 3.2.
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TMP92CZ26A 3.3 Clock Function and Standby Function TMP92CZ26A contains (1) clock gear, (2) clock doubler (PLL), (3) standby controller and (4) noise-reducing circuit. They are used for low-power, low-noise systems. This chapter is organized as follows: 3.3.1 Block diagram of system clock 3.3.2 SFRs 3.3.3 System clock controller 3.3.4 Prescaler clock controller 3.3.5 Noise-reducing circuit 3.3.
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TMP92CZ26A The clock operating modes are as follows: (a) PLL-OFF Mode (X1, X2 pins only), (b) PLL-ON Mode (X1, X2, and PLL). Figure 3.3.1 shows a transition figure. The clock frequency input from the X1 and X2 pins is called fOSCH and the clock frequency input from the XT1 and XT2 pins is called fs. The clock frequency selected by SYSCR1 is called the system clock fSYS. And one cycle of fSYS is defined to as one state.
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TMP92CZ26A 3.3.
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TMP92CZ26A TMP92CZ26A has two PLL circuits: one is for CPU (PLL0) and the other for USB (PLL1). Each PLL can be controlled independently. Frequency of external oscillator is 6 to 10MHz. Don’t connect oscillator more than10MHz. When clock is input by using external oscillator, range of input frequency is 6 to10MHz. Don’t input the clock over 10MHz. Table 3.3.1 Setting example for fOSCH (a) PLL, USB (PLL0 ON/PLL1ON) High frequency: fOSCH System clock: fSYS System clock: fSYS USB clock: fUSB 10.
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TMP92CZ26A 3.3.
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TMP92CZ26A 7 EMCCR0 (10E3H) 4 3 2 1 0 PROTECT − EXTIN DRVOSCH DRVOSCL Read/Write R R/W R/W R/W R/W After reset 0 0 0 1 1 Protect flag Always 1: External fc oscillator fs oscillator 0: OFF write “0”.
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TMP92CZ26A 7 PLLCR0 (10E8H) 6 5 bit symbol FCSEL LUPFG Read/Write R/W R After reset 0 0 Function 4 Select Lock-up fc-clock timer 0 : fOSCH Status flag 1 : fPLL 0 : not end 3 2 1 0 1 : end Note: Be carefull that logic of PLLCR0 is different from 900/L1’s DFM.
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TMP92CZ26A 3.3.3 System clock controller The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O. SYSCR0 and SYSCR0 control enabling and disabling of each oscillator. SYSCR1 sets the high frequency clock gear to either 1, 2, 4, 8 or 16 (fc, fc/2, fc/4, fc/8, fc/16). These functions can reduce the power consumption of the equipment in which the device is installed.
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TMP92CZ26A 3.3.4 Clock doubler (PLL) PLL0 outputs the fPLL clock signal, which is 12 or 16 times as fast as fOSCH. That is, the low-speed frequency oscillator can be used as external oscillator, even though the internal clock is high-frequency. Since Reset initializes PLL0 to stop status, setting to PLLCR0 and PLLCR1-register is needed before use. Like an oscillator, this circuit requires time to stabilize. This is called the lock-up time and it is measured by 12-stage binary counter.
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TMP92CZ26A The following is a setting example for PLL0-starting and PLL0-stopping. (Example-1) PLL0-starting PLLCR0 EQU 10E8H PLLCR1 EQU 10E9H LUP: Enables PLL0 operation and starts lock-up. LD (PLLCR1),1XXXXXXXXB ; BIT 5,(PLLCR0) ; JR Z,LUP ; LD (PLLCR0), X1XXXXXXB ; Changes fc from 10 MHz to 60 MHz.
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TMP92CZ26A Limitation point on the use of PLL0 1. If you stop PLL operation during using PLL0, you should execute following setting in the same order. LD (PLLCR0),X0XXXXXXB ; Change the clock fPLL to fOSCH LD (PLLCR1),0XXXXXXXB ; Stop PLL0 X: Don't care 2. If you shift to STOP mode during using PLL, you should execute following setting in the same order.
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TMP92CZ26A 3.3.5 Noise reduction circuits Noise reduction circuits are built in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator circuit (2) Reduced drivability for low-frequency oscillator circuit (3) Single drive for high-frequency oscillator circuit (4) SFR protection of register contents These are set in EMCCR0 to EMCCR2 registers.
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TMP92CZ26A (2) Reduced drivability for low-frequency oscillator circuit (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) C1 XT1 pin Enable oscillation Resonator EMCCR0 C2 fS XT2 pin (Setting method) The drivability of the oscillator is reduced by writing 0 to the EMCCR0 register. By Reset, is initialized to “1”.
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TMP92CZ26A (4) Runaway provision with SFR protection register (Purpose) Provision in runaway of program by noise mixing. Write operation to specified SFR is prohibited so that provision program in runaway prevents that it is in the state which is fetch impossibility by stopping of clock, memory control register (Memory controller, MMU) is changed. And error handling in runaway becomes easy by INTP0 interruption. Specified SFR list 1.
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TMP92CZ26A 3.3.6 Standby controller (1) Halt Modes and Port Drive-register When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP Mode, depending on the contents of the SYSCR2 register and each pin-status is set according to PxDR-register.
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TMP92CZ26A The operation of each of the different Halt Modes is described in Table 3.3.3. Table 3.3.
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TMP92CZ26A Table 3.3.
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TMP92CZ26A (Example - releasing IDLE1 Mode) An INT0 interrupt clears the Halt state when the device is in IDLE1 Mode. Address 8200H LD (PCFC), 02H ; Sets PC1 to INT0 interrupt. 8203H 8206H LD LD (IIMC0), 00H (INTE0), 06H ; Select INT0 interrupt rising edge. ; Sets INT0 interrupt level to 6. 8209H EI 5 ; Sets CPU interrupt level to 5. 820BH 820EH LD HALT (SYSCR2), 28H ; Sets Halt mode to IDLE1 mode. ; Halts CPU. INT0 INT0 interrupt routine.
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TMP92CZ26A (3) Operation a. IDLE2 Mode In IDLE2 Mode, only specific internal I/O operations, as designated by the IDLE2 Setting Register, can take place. Instruction execution by the CPU stops. Figure 3.3.8 illustrates an example of the timing for clearance of the IDLE2 Mode Halt state by an interrupt. X1 A0~A23 D0~D31 Data Data RD WR Interrupt for releasing Halt IDLE2 mode Figure 3.3.8 Timing chart for IDLE2 Mode Halt state cleared by interrupt b.
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TMP92CZ26A c. STOP Mode When STOP Mode is selected, all internal circuits stop, including the internal oscillator. After STOP Mode has been cleared system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize. Figure 3.3.10 illustrates the timing for clearance of the STOP Mode Halt state by an interrupt. Warm-up time X1 A0~A23 D0~D31 Data Data RD Interrupt for releasing Halt STOP mode Figure 3.3.
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TMP92CZ26A Table 3.3.
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TMP92CZ26A Table 3.3.
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TMP92CZ26A Table 3.3.
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TMP92CZ26A 3.4 Boot ROM The TMP92CZ26A contains boot ROM for downloading a user program, and supports two kinds of downloading methods. 3.4.1 Operation Modes The TMP92CZ26A has two operation modes: MULTI mode and BOOT mode. The operation mode is selected according to the AM1 and AM0 pin levels when RESET is asserted. (1) MULTI mode: After reset, the CPU fetches instructions from external memory and executes them.
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TMP92CZ26A 3.4.2 Hardware Specifications of Internal Boot ROM (1) Memory map Figure 3.4.1 shows a memory map of BOOT mode. The boot ROM incorporated in the TMP92CZ26A is an 8-Kbyte ROM area mapped to addresses 3FE000H to 3FFFFFH. In MULTI mode, the boot ROM is not mapped and the above area is mapped as an external area.
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TMP92CZ26A 3.4.3 Outline of Boot Operation The method for downloading a user program can be selected from two types: from UART, or via USB. After reset, the boot program on the internal boot ROM executes as shown in Figure 3.4.2. Regardless of the downloading method used, the boot program downloads a user program into the internal RAM and then branches to the internal RAM. Figure 3.4.3 shows how the boot program uses the internal RAM (common to all the downloading methods).
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TMP92CZ26A 002000H Work Area for Boot Program (4 Kbytes) 003000H Download Area for User Program (282 Kbytes) 049800H Stack Area for Boot Program (2 Kbytes) 049FFFH Figure 3.4.
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TMP92CZ26A (1) Port settings Table 3.4.3 shows the port settings by the boot program. When designing your application system, please also refer to Table 3.4.4 for recommended pin connections for using the boot program. The boot program only sets the ports shown in the table below; other ports are left as they are after reset or at startup of the boot program. Table 3.4.
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TMP92CZ26A Table 3.4.4 Recommended Pin Connections Port Name UART USB Function Name Recommended Pin Connections for Each Download Method I/O UART Connect to the level shifter. USB P90 TXD0 Output No special setting is needed for booting via USB. P91 RXD0 Input −−− D+ I/O No special setting is needed for booting via UART. −−− D− I/O Connect to the USB connector by adding a dumping resistor If USB is not used, add a (27Ω recommended).
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TMP92CZ26A (2) I/O register settings Table 3.4.5 shows the I/O registers that are set by the boot program. After the boot sequence, if execution moves to an application system program without a reset being asserted, the settings of these I/O registers must be taken into account. Also note that the registers in the CPU and the internal RAM remain in the state after execution of the boot program. Table 3.4.
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TMP92CZ26A 3.4.4 Downloading a User Program via UART (1) Connection example Figure 3.4.4 shows an example of connections for downloading a user program via UART (using a 16-bit NOR Flash memory device as program memory).
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TMP92CZ26A (3) UART data transfer format Table 3.4.6 to Table 3.4.11 show the supported frequencies, data transfer format, baud rate modification command, operation command, and version management information, respectively. Please also refer to the description of boot program operation later in this section. Table 3.4.6 Supported Frequencies (X1) 6.00 MHz 8.00 MHz 9.00 MHz 10.00 MHz Note: The built-in PLL (clock multiplier) is not used regardless of the oscillation frequency. Table 3.4.
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TMP92CZ26A Table 3.4.8 Baud Rate Modification Command Baud Rate (bps) 9600 19200 38400 57600 115200 Modification Command 28H 18H 07H 06H 03H Note 1: If fOSCH (oscillation frequency) is 10.0 MHz, 57600 and 115200 bps are not supported. Note 2: If fOSCH (oscillation frequency) is 6.00, 8.00, or 9.00 MHz, 38400, 57600, and 115200 bps are not supported. Table 3.4.9 Operation Command Operation Command Operation C0H User program start Table 3.4.
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TMP92CZ26A the baud rate is not changed, the initial baud rate data (28H: 9600 bps) must be sent. Baud rate modification becomes effective after the echo back transmission is completed. 8. The 9th byte is used to echo back the received data to the PC when the data received in the 8th byte is one of the baud rate modification data corresponding to the operating frequency of the microcontroller. Then, the baud rate is changed.
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TMP92CZ26A b) Error codes The boot program uses the error codes shown in Table 3.4.12 to notify the PC of its processing status. Table 3.4.12 Error Codes Error Code 62H Meaning Unsupported baud rate 64H Invalid operation command A1H Framing error in received data A3H Overrun error in received data Note 1: If a receive error occurs while a user program is being received, no error code will be sent to the PC. Note 2: After sending an error code, the boot program stops operation.
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TMP92CZ26A d) Notes on Intel Hex format (binary) 1. After receiving the checksum of a record, the boot program waits for the start mark (3AH for “:”) of the next record. If data other than 3AH is received between records, it is ignored. 2. Once the PC program has finished sending the checksum of an end record, it must wait for 2 bytes of data (upper and lower bytes of SUM) before sending any other data.
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TMP92CZ26A e) User program receive error If either of the following error conditions occurs while a user program is being received, the boot program stops operation. If the record type is other than 00H, 01H, or 02H If a checksum error occurs f) Measured frequency/baud rate error When the boot program receives matching data, it measures the oscillation frequency. If an error is within plus or minus 3%, the boot program decides on that frequency.
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TMP92CZ26A (5) Others a) Handshake function Although the CTS pin is available in the TMP92CZ26A, the boot program does not use it for transfer control. b) RS-232C connector The RS-232C connector must not be connected or disconnected while the boot program is running. c) Software on the PC When downloading a user program via UART, special application software is needed on the PC.
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TMP92CZ26A 3.4.5 Downloading a User Program via USB (1) Connection example Figure 3.4.5 shows an example of connections for downloading a user program via USB (using a 16-bit NOR Flash memory device as program memory). PUCTL R1 = 1.5 kΩ R4 = 100 kΩ R2 = 27 Ω PC R3 = 27 Ω PU6, LD22 RXD,P91 P82, CS2 P70, RD PJ2, SRWR D+ D− TMP92CZ26A AM0 D0 to D15 CE OE WE NOR Flash D0 to D15 AM1 A0 to A19 A1 to A20 Note 1: The value of pull-up and pull-down resistors are recommended values.
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TMP92CZ26A The following shows an overview of the USB communication flow.
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TMP92CZ26A Table 3.4.15 Vendor Request Commands Command Name Value of Operation Notes bRequest Microcontroller information command 00H Send microcontroller information Microcontroller information data is sent by bulk IN transfer after the setup stage is completed. User program transfer start command 02H Receive a user program Set the size of a user program in wIndex. The user program is received by bulk OUT transfer after the setup stage is completed.
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TMP92CZ26A Table 3.4.
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TMP92CZ26A ConfigrationDescriptor Field Name Value bLength 09H bDescriptorType 02H wTotalLength 0020H Meaning 9 bytes Configuration descriptor Total length (32 bytes) which each descriptor of both configuration descriptor, interface and endpoint is added. bNumInterfaces 01H There is one interface.
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TMP92CZ26A Table 3.4.19 Information Returned for the Microcontroller Information Command Microcontroller Information TMP92CZ26A ASCII Code 54H, 4DH, 50H, 39H, 32H, 43H, 5AH, 32H, 36H,20H, 20H, 20H, 20H, 20H, 20H Table 3.4.20 Information Returned for the User Program Transfer Result Command Transfer Result Value Error Conditions No error 00H User program not received 02H The user program transfer result is received without the user program transfer start command being received first.
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TMP92CZ26A (3) Description of the USB boot program operation The boot program loads a user program in Intel Hex format sent from the PC into the internal RAM. When the user program has been loaded successfully, the user program starts executing from the first address received. The boot program thus enables users to perform customized on-board programming. a. Operation procedure 1. Connect the USB cable. 2. Set the AM0 and AM1 pins to “1” and reset the microcontroller. 3.
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TMP92CZ26A b. Notes on the user program format (binary) 1. After receiving the checksum of a record, the boot program waits for the start mark (3AH for “:”) of the next record. If data other than 3AH is received between records, it is ignored. 2. Since the address pointer is initially set to 00H, the record type to be transferred first does not have to be an address record. 3. Addresses 3000H to 497FFH (282 Kbytes) are allocated as the user program download area.
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TMP92CZ26A (4) Others a) USB connector The USB connector must not be connected or disconnected while the boot program is running. b) Software on the PC To download a user program via USB, a USB device driver and special application software are needed on the PC.
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TMP92CZ26A 3.5 Interrupts Interrupts are controlled by the CPU Interrupt Mask Register (bits 12 to 14 of the Status Register) and by the built-in interrupt controller.
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TMP92CZ26A DMA soft start request Interrupt processing Interrupt specified by DMA start vector ? YES Clear interrupt request flag NO Interrupt vector calue “V” read interrupt request F/F clear Start specified by HDMA General-purpose interrupt processing YES to HDMA processing flow NO PUSH PC PUSH SR SR ← Level of accepted interrupt + 1 INTNEST ← INTNEST + 1 Data transfer by micro DMA Micro DMA processing COUNT ← COUNT − 1 PC ← (FFFF00H + V) COUNT = 0 NO Interrupt processing program RET
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TMP92CZ26A 3.5.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. However, in the case of software interrupts and illegal instruction interrupts generated by the CPU, the CPU skips steps (1) and (3), and executes only steps (2), (4), and (5). (1) The CPU reads the interrupt vector from the interrupt controller.
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TMP92CZ26A Table 3.5.
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TMP92CZ26A Default Priority 51 52 53 54 55 56 57 58 59 60 − to − Type Maskable Interrupt Source and Source of Micro DMA Request INTADHP: AD most priority conversion end INTAD: AD conversion end INTTC0/INTDMA0: Micro DMA0 /HDMA0 end INTTC1/INTDMA1: Micro DMA1 /HDMA1 end INTTC2/INTDMA2: Micro DMA2 /HDMA2 end INTTC3/INTDMA3: Micro DMA3 /HDMA3 end INTTC4/INTDMA4: Micro DMA4 /HDMA4 end INTTC5/INTDMA5: Micro DMA5 /HDMA5 end INTTC6 : Micro DMA6 end INTTC7 : Micro DMA7 end (Reserved) Note 1: When standing-up m
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TMP92CZ26A 3.5.2 Micro DMA processing In addition to general-purpose interrupt processing, the TMP92CZ26A also includes a micro DMA function and HDMA function. This section explains about Micro DMA function. For the HDMA function, please refer 3.23 DMA controller. Micro DMA processing for interrupt requests set by micro DMA is performed at the highest priority level for maskable interrupts (Level 6), regardless of the priority level of the interrupt source.
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TMP92CZ26A If micro DMA requests are set simultaneously for more than one channel, priority is not based on the interrupt priority level but on the channel number: The lower the channel number, the higher the priority (Channel 0 thus has the highest priority and channel 7 the lowest). Note: Don’t start any micro DMAs by one interrupt. If any micro DMA are set by it, micro DMA that channel number is biggest (priority is lowest) is not started.
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TMP92CZ26A (2) Soft start function The TMP92CZ26A can initiate micro DMA/HDMA either with an interrupt or by using the micro DMA /HDMA soft start function, in which micro DMA or HDMA is initiated by a Write cycle which writes to the register DMAR. Writing “1” to each bit of DMAR register causes micro DMA or HDMA to be performed once. On completion of the transfer, the bits of DMAR for the completed channel are automatically cleared to “0”.
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TMP92CZ26A (4) Detailed description of the transfer mode register 0 0 0 Mode DMAMn[4:0] 000zz 001zz 010zz 011zz 100zz 101zz 110zz 1 1 1 00 ZZ: DMAM0 to 7 Mode Description Destination INC mode (DMADn +) ← (DMASn) DMACn ← DMACn - 1 if DMACn = 0 then INTTCn Execution Time 5 states Destination DEC mode (DMADn -) ← (DMASn) DMACn ← DMACn - 1 if DMACn = 0 then INTTCn 5 states Source INC mode (DMADn) ← (DMASn +) DMACn ← DMACn - 1 if DMACn = 0 then INTTCn 5 states Source DEC mode (DMADn) ← (DMAS
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TMP92CZ26A 3.5.3 Interrupt Controller Operation The block diagram in Figure 3.5.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 59 interrupts channels there is an interrupt request flag (consisting of a flip-flop), an interrupt priority setting register and a micro DMA /HDMA start vector register.
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Micro DMA/HDMA counter 0 interrupt 92CZ26A-77 INTTC4/INTDMA4 INTTC5/INTDMA5 INTTC6 INTTC7 INT1 INT2 INT3 INT4 INTALM INTTA4 INTTA5 INT0 INTWD Q Q Figure 3.5.
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TMP92CZ26A (1) Interrupt priority setting registers Symbol Name Address 7 6 F0H − R − 5 4 3 − R/W − I0C R 0 − INTE0 INT0 enable Always write “0”. INTE12 INTE34 INTE56 INT1 & INT2 enable INT3 & INT4 enable INT5 & INT6 enable D0H D1H D2H INT2 I2M2 I2M1 R/W 0 0 I2C R 0 I2M0 0 INT4 I4M2 I4M1 R/W 0 0 INT6 I6M2 I6M1 R/W 0 0 I4C R 0 I6C R 0 I1C R 0 I4M0 I3C R 0 0 I6M0 I5C R 0 0 − INTE7 INT7 enable D3H − R − − R/W − I7C R 0 Always write “0”.
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TMP92CZ26A Symbol Name Address INTTB00 & INTETB0 INTTB01 D8H enable INTTB10 & INTETB1 INTTB11 D9H enable INTRX0 & INTES0 INTTX0 DBH enable INTSBI & INTESBIADM INTADM E0H enable INTESPI INTSPI enable E1H 7 6 5 4 INTTB01 (TMRB0) ITB01C ITB01M2 ITB01M1 ITB01M0 ITB00C R R/W R 0 0 0 0 0 INTTB11 (TMRB1) ITB11C ITB11M2 ITB11M1 ITB11M0 ITB10C R R/W R 0 0 0 0 0 INTEUSB enable E3H enable E5H 0 0 − − 0 0 − − − − − − Always write “0”.
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TMP92CZ26A Symbol Name Address 7 6 5 4 3 2 1 0 − INTELCD INTLCD enable INTI2S0 & INTEI2S01 INTI2S1 enable INTRSC & INTENDFC INTRDY enable INTEP0 0INTEAD EAH EBH ECH INTP0 enable EEH INTAD & INTADHP enable EFH Interrupt request flag INTLCD ILCD1C ILCDM2 ILCDM1 ILCDM0 R R/W Always write “0”.
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TMP92CZ26A Symbol Name Address 7 6 5 4 3 2 ITC1M0 ITC0C ITC0M2 INTTC1/INTDMA1 INTETC01 /INTEDMA01 INTETC23 /INTEDMA23 INTTC0/INTDMA0 & INTTC1/INTDMA1 ITC1C F1H enable INTTC3/INTDMA3 ITC3C F2H enable ITC1M1 INTTC0/INTDMA0 R/W 0 0 INTTC3/INTDMA3 ITC3M2 ITC3M1 0 R 0 R 0 /INTEDMA45 INTETC67 INTTC4/INTDMA4 & INTTC5/INTDMA5 ITC5C F3H enable INTTC6 & INTTC7 enable ITC3M0 ITC2C R/W 0 0 0 R 0 INTWD enable F7H ITC5M2 ITC5M1 ITC5M0 ITC7C R 0 R/W 0 0 INTTC7 (DMA7) ITC4
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TMP92CZ26A (2) Symbol External interrupt control Name Address Interrupt IIMC0 7 6 5 4 3 2 1 0 I5EDGE I4EDGE I3EDGE I2EDGE I1EDGE I0EDGE I0LE − W W W W W W R/W R/W 0 0 0 0 0 0 0 F6H input mode INT5EDGE INT4EDGE INT3EDGE INT2EDGE INT1EDGE INT0EDGE INT0 (Prohibit control 0 RMW) 0: Rising 0: Rising 0: Rising 0: Rising 0: Rising 0: Rising 1: Falling 1: Falling 1: Falling 1: Falling 1: Falling 1: Falling 0: Edge 0 Always write “0”.
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TMP92CZ26A (3) Symbol SIO receive interrupt control Name SIO SIMC interrupt mode control Address 7 6 5 4 3 2 1 0 − − IR0LE W W W 0 0 1 F5H Always Always 0:INTRX0 (Prohibit write “0” write “0” edge RMW) (Note) mode 1:INTRX0 level mode Note: When using the micro DMA transfer end interrupt, always write “1”.
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TMP92CZ26A (4) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA /HDMA start vector, as given in Table 3.5.1 to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction. INTCLR Symbol INTCLR Name Address Interrupt F8H clear (Prohibit control RMW) ← 0AH ; Clears interrupt flag INT0.
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TMP92CZ26A Symbol Name Address 7 6 DMA0 DMA0V start 5 4 3 DMA0V5 DMA0V4 DMA0V3 2 1 0 DMA0V2 DMA0V1 DMA0V0 0 0 0 DMA1V2 DMA1V1 DMA1V0 0 0 0 DMA2V2 DMA2V1 DMA2V0 0 0 0 DMA3V2 DMA3V1 DMA3V0 0 0 0 DMA4V2 DMA4V1 DMA4V0 0 0 0 DMA5V2 DMA5V1 DMA5V0 0 0 0 DMA6V2 DMA6V1 DMA6V0 0 0 0 DMA7V2 DMA7V1 DMA7V0 0 0 0 R/W 100H 0 vector 0 0 DMA0 start vector DMA1 DMA1V start DMA1V5 DMA1V4 DMA1V3 0 0 0 R/W 101H vector DMA1 start vector DMA2 DMA2V
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TMP92CZ26A (7) Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer, once started, to continue until the value in the transfer counter register reaches “0”. Setting any of the bits in the register DMAB which correspond to a micro DMA channel (as shown below) to “1” specifies that any micro DMA transfer on that channel will be a burst transfer.
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TMP92CZ26A (8) Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore, if immediately before an interrupt is generated, the CPU fetches an instruction which clears the corresponding interrupt request flag, the CPU may execute this instruction in between accepting the interrupt and reading the interrupt vector. In this case, the CPU will read the default vector 0004H and jump to interrupt vector address FFFF04H.
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TMP92CZ26A 3.6 DMAC (DMA Controller) The TMP92CZ26A incorporates a DMA controller (DMAC) having six channels. This DMAC can realize data transfer faster than the micro DMA function by the 900/H1 CPU. The DMAC has the following features: 1) Six independent channels of DMA 2) Two types of transfer start requests Hardware request (using an interrupt source connected with the INTC) or software request can be selected for each channel.
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TMP92CZ26A 3.6.1 Block Diagram Figure 3.6.1 shows an overall block diagram for the DMAC.
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TMP92CZ26A 3.6.2 SFRs The DMAC has the following SFRs. These registers are connected to the CPU via a 16-bit data bus. (1) HDMASn (DMA Transfer Source Address Setting Register) The HDMASn register is used to set the DMA transfer source address. When the source address is updated by DMA execution, HDMASn is also updated. HDMAS0 to HDMAS5 have the same configuration. Although the bus sizing function is supported, the address alignment function is not supported.
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TMP92CZ26A (2) HDMADn (DMA Transfer Destination Address Setting Register) The HDMADn register is used to set the DMA transfer destination address. When the destination address is updated by DMA execution, HDMADn is also updated. HDMAD0 to HDMAD5 have the same configuration. Although the bus sizing function is supported, the address alignment function is not supported.
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TMP92CZ26A (3) HDMACAn (DMA Transfer Count A Setting Register) The HDMACAn register is used to set the number of times a DMA transfer is to be performed by one DMA request. HDMACAn contains 16 bits and can specify up to 65536 transfers (0001H = one transfer, FFFFH = 65535 transfers, 0000H = 65536 transfers). Even when the transfer count A is updated by DMA execution, HDMACAn is not updated. HDMACA0 to HDMACA5 have the same configuration.
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TMP92CZ26A (4) HDMACBn (DMA Transfer Count B Setting Register) The HDMACBn register is used to set the number of times a DMA request is to be made. HDMACBn contains 16 bits and can specify up to 65536 requests (0001H = one request, FFFFH = 65535 requests, 0000H = 65536 requests). When the transfer count B is updated by DMA execution, HDMACBn is also updated. HDMACB0 to HDMACB5 have the same configuration.
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TMP92CZ26A (5) HDMAMn (DMA Transfer Mode Setting Register) The HDMAMn register is used to set the DMA transfer mode. HDMAM0 to HDMAM5 have the same configuration.
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TMP92CZ26A (6) HDMAE (DMA Operation Enable Register) The HDMAE register is used to enable or disable the DMAC operation. Bits 0 to 5 correspond to channels 0 to 5. Unused channels should be set to “0”. 7 HDMAE (097EH) HDMAE Register 5 4 6 bit Symbol 3 2 1 0 DMAE5 DMAE4 DMAE3 DMAE2 DMAE1 DMAE0 0 0 0 0 0 Read/Write R/W After reset 0 DMA channel operation Function 0: Disable 1: Enable Note: Read-modify-write instructions can be used on this register. Figure 3.6.
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TMP92CZ26A 3.6.3 DMAC Operation Description (1) Overall flowchart Figure 3.6.9 shows a flowchart for DMAC operation when an interrupt (DMA) is requested.
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TMP92CZ26A (2) Bus arbitration The TMP92CZ26A includes three controllers (DMA controller, LCD controller, SDRAM controller) that function as bus masters apart from the CPU. These controllers operate independently and assert a bus request as required. The controller that receives a bus acknowledgement acts as the bus master. No priorities are assigned to these three controllers, and bus requests are processed in the order in which they are asserted.
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TMP92CZ26A 3.6.4 Setting Example This section explains how to set the DMAC using an example. (1) Transferring music data from internal RAM to I2S by DMA transfer The 32 Kbytes of data stored in the internal RAM at addresses 2000H to 9FFFH shall be transferred to FIFO-RAM via I2S. Each time an INTI2S request is asserted, 64 bytes (4 bytes x 16 times) shall be transferred to FIFO-RAM using DMAC channel 0. Since INTI2S is an FIFO empty interrupt, the first data must be set in advance.
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TMP92CZ26A 3.6.5 Note 1. In case of using S/W start with HDMA, transmission start is to set to "1" DMAR register. However DMAR register can't be used to confirm flag of transmission end. DMAR register reset to "0" when HDMA release bus occupation once with HDMATR function. We recommend to use HDMACBn register (counter value) to confirm flag of transmission end.
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TMP92CZ26A 3.6.6 Considerations for Using More Than One Bus Master In the TMP92CZ26A, the LCD controller, SDRAM controller, and DMA controller may act as the bus master apart from the CPU. Therefore, care must be exercised to enable each of these functions to operate smoothly.
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TMP92CZ26A Sample 1) Calculation example for CPU + HDMA Conditions: CPU operation speed (fSYS) : 60 MHz I2S sampling frequency : 48 KHz (60 MHz/25/50 = 48 KHz) I2S data transfer bit length : 16 bits DMAC channel 0 used to transfer 5 Kbytes from internal RAM to I2S Calculation example: DMAC source data read time: Internal RAM data read time = 1 state/4 bytes (However, the first 1 byte requires 2 states.
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TMP92CZ26A (2) CPU + LDMA The LCD controller performs DMA transfer (LDMA) after issuing a bus request to the CPU and getting a bus acknowledgement. If LDMA is not performed properly, the LCD display function cannot work properly. Therefore, LDMA must have higher priority than the CPU. While LDMA is being performed, the CPU cannot execute instructions.
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TMP92CZ26A Sample2) Calculation examples for CPU + LDMA Conditions 1: CPU operation speed (fSYS) : 60 MHz Display RAM : Internal RAM Display size : QVGA (320seg × 240com) Display quality : 65536 colors (TFT) Refresh rate : 70 Hz (including 20 clocks of dummy cycles) Calculation example 1: tSTOP (LDMA) = ((SegNum × K / 8) × tLRD) + (1 / fSYS [Hz]) = ((320 × 16 / 8) × 1 / fSYS [Hz] / 4) + (1 / fSYS [Hz]) = ((640) × 16.67 [ns] / 4) + 16.67 [ns] = 2.
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TMP92CZ26A (3) CPU + LDMA + ARDMA The SDRAM controller owns the bus not only when SDRAM is used as the LCD display RAM but also when SDRAM is used as work, data, or stack area. The SDRAM controller occupies the bus (ARDMA) while it refreshes SDRAM data by the auto refresh function. No special consideration is needed for the ARDMA time normally as it ends within several clocks per specified number of states.
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TMP92CZ26A Sample3) Calculation example for CPU + LDMA + ARDMA Conditions: CPU operating speed(fSYS) : 60 MHz Display RAM : 16-bit external SDRAM Display size : QVGA (320seg × 240com) Display quality : 65536 colors (TFT) Refresh rate : 70 Hz (including 20 clocks of dummy cycles) SDRAM auto refresh : Every 936 states (15.6 μs) Calculation example: tSTOP (LDMA) =((SegNum × K / 8) × tLRD) + (8 / fSYS [Hz]) = ((320 ×16 / 8) × 1 / fSYS [Hz] / 2) + (8 / fSYS [Hz]) = ((640) × 16.67 [ns] / 2) + 133.
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TMP92CZ26A (4) CPU + LDMA+ ARDMA + HDMA This is a case in which all the bus masters are active at the same time. Since the LCD display function cannot work properly if the LCD controller cannot perform LDMA properly, the priorities among the four bus masters should be set in the order of LDMA > ARDMA > HDMA > CPU. Before calculating the CPU bus stop rate, the conditions for proper LCD display shall be considered first.
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TMP92CZ26A Sample 4) Calculation example for CPU + LDMA+ ARDMA + HDMA Conditions: CPU operation speed (fSYS) : 60 MHz Display RAM : QVGA (320seg × 240com) Display quality : 65536 colors (TFT) Refresh rate : 70 Hz (including 20 clocks of dummy cycles) SDRAM Auto Refresh : Every 936 states (15.
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TMP92CZ26A HDMATR Register HDMATR (097FH) bit Symbol 7 6 5 4 DMATE DMATR6 DMATR5 DMATR4 Read/Write After reset 2 1 0 DMATR3 DMATR2 DMATR1 DMATR0 0 0 0 R/W 0 0 0 0 Timer Function 3 0 Maximum bus occupancy time setting operation The value to be set in should be obtained by 0: Disable “maximum bus occupancy time / (256/fSYS)”. 1: Enable “00H” cannot be set. Note: Read-modify-write instructions can be used on this register.
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TMP92CZ26A Sample 5) Calculation example when using CPU + LCDC + SDRAMC + HDMA at same time (Worst case) Conditions: CPU operation speed (fSYS) : 80MHz Display RAM : Internal RAM Display size : QVGA (320seg × 240com) Display quality : 16777216 color (TFT) Refresh rate : 70Hz HDMA : Transfers 225 Kbytes from internal RAM to SDRAM Calculation example: = ((SegNum × K/8) × tLRD) + (1/fSYS [Hz]) tSTOP (LCD) = ((320 × 24/8) × 1/fSYS [Hz]/4) + (1/fSYS [Hz]) = ((960) × 12.5 [nS]/4) + 12.5 [nS] = 3.
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TMP92CZ26A 3.7 Function of ports TMP92CZ26A has I/O port pins that are shown in Table 3.7.1 in addition to functioning as general-purpose I/O ports, these pins are also used by internal CPU and I/O functions. Table 3.7.2 lists I/O registers and their specifications. Table 3.7.
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TMP92CZ26A Table 3.7.
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TMP92CZ26A Table 3.7.
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TMP92CZ26A Table 3.7.
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TMP92CZ26A X: Don’t care Table3.7.
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TMP92CZ26A Table3.7.
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TMP92CZ26A Table 3.7.
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TMP92CZ26A 3.7.1 Port 1 (P10 to P17) Port1 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P1CR and function register P1FC. In addition to functioning as a general-purpose I/O port, port1 can also function as a data bus (D8 to D15).
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TMP92CZ26A Port 1 register P1 (0004H) bit Symbol 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 Read/Write R/W After reset Data from external port (Output latch register is cleared to “0”) Port 1 Control register P1CR (0006H) bit Symbol 7 6 5 4 3 2 1 0 P17C P16C P15C P14C P13C P12C P11C P10C 0 0 0 0 0 0 0 0 2 1 0 Read/Write After reset W Function 0: Input 1: Output Port 1 Function register 7 P1FC (0007H) 6 5 4 3 bit Symbol P1F Read/Write W Af
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TMP92CZ26A 3.7.2 Port 4 (P40 to P47) Port4 is an 8-bit general-purpose Output ports. In addition to functioning as a general-purpose Output port, port4 can also function as an address bus (A0 to A7). Each bit can be set individually for function.
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TMP92CZ26A Port 4 register P4 (0010H) bit Symbol 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 P47F P46F P45F P44F P43F P42F P41F P40F 0/1 0/1 0/1 0/1 Read/Write After reset R/W Port 4 Function register P4FC (0013H) bit Symbol Read/Write After reset W 0/1 0/1 0/1 0/1 Note2: 0:Port Function 1:Address bus (A0 to A7) Port 4 Drive register P4DR (0084H) bit Symbol 7 6 5 4 3 2 1 0 P47D P46D P45D P44D P43D P4
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TMP92CZ26A 3.7.3 Port 5 (P50 to P57) Port5 is an 8-bit general-purpose Output ports. In addition to functioning as a general-purpose I/O port, port5 can also function as an address bus (A8 to A15). Each bit can be set individually for function.
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TMP92CZ26A Port 5 register P5 (0014H) bit Symbol 7 6 5 4 3 2 1 0 P57 P56 P55 P54 P53 P52 P51 P50 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 P57F P56F P55F P54F P53F P52F P51F P50F 0/1 0/1 0/1 0/1 Read/Write After reset R/W Port 5 Function register P5FC (0017H) bit Symbol Read/Write After reset W 0/1 0/1 0/1 0/1 Note2: 0:Port Function 1:Address bus (A8 to A15) Port 5 Drive register P5DR (0085H) bit Symbol 7 6 5 4 3 2 1 0 P57D P56D P55D P54D P53D
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TMP92CZ26A 3.7.4 Port 6 (P60 to P67) Port6 is an 8-bit general-purpose I/O ports. Bits can be individually set as either inputs or outputs and function by control register P6CR and function register P6FC. In addition to functioning as a general-purpose I/O port, port6 can also function as an address bus (A16 to A23).
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TMP92CZ26A Port 6 register P6 (0018H) bit Symbol 7 6 5 4 3 2 1 0 P67 P66 P65 P64 P63 P62 P61 P60 Read/Write R/W After reset Data from external port (Output latch register is cleared to “0”) Port 6 Control register P6CR (001AH) bit Symbol 7 6 5 4 3 2 1 0 P67C P66C P65C P64C P63C P62C P61C P60C 0 0 0 0 0 0 0 0 3 2 1 0 P63F P62F P61F P60F 0/1 0/1 0/1 0/1 Read/Write After reset W Function 0:Input 1:Output Port 6 Function register P6FC (001BH) bit
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TMP92CZ26A 3.7.5 Port 7 (P70 to P76) Port7 is a 7-bit general-purpose I/O port (P70 is used for output only). Bits can be individually set as either inputs or outputs by control register P7CR and function register P7FC. In addition to functioning as a general-purpose I/O port, P70 to P76 pins can also function interface-pin for external memory. A reset initializes P70 pin to output port mode, and P71 to P76 pins to input port mode.
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TMP92CZ26A P7CR register P7FC register S P7 register EA24, EA25 S1 Read data P73 (EA24) P74 (EA25) 0 1 Selector 0 Selector P7CR register P7FC register 0 S P7 register 1 R/W P75(R/W, NDR /B ) Selector S1 Port read data 0 Selector NDR/ B P7CR register P7FC register P76 ( WAIT ) P7 register Port read data WAIT Figure 3.7.
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TMP92CZ26A Port 7 register 7 P7 (001CH) bit Symbol 6 5 4 3 2 1 0 P76 P75 P74 P73 P72 P71 P70 Read/Write R/W Data from external port Data from external port After reset Data from external port (Output latch register is (Output latch register is (Output latch register is set to “1”) cleared to “0”) 1 set to “1”) Port 7 Control register 7 P7CR bit Symbol (001EH) Read/Write 6 5 4 P76C P75C P74C 3 2 1 P73C P72C P71C 0 0 0 0 W After reset 0 0 0 Function 0: Input 1:
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TMP92CZ26A Port 8 (P80 to P87) Port 80 to 87 are 8-bit output ports. Resetting sets output latch of P82 to “0” and output latches of P80 to P81, P83 to P87 to “1”. But if it is started at boot mode (AM [1:0]= “11”), output latch of P82 is set to “1”. Port 8 also function as interface-pin for external memory. Writing “1” in the corresponding bit of P8FC, P8FC2 enables the respective functions. Resetting resets P8FC to “0” and P8FC2 to “0”, sets all bits to output ports.
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TMP92CZ26A Port 8 register bit Symbol P8 (0020H) 7 6 5 4 3 2 1 0 P87 P86 P85 P84 P83 P82 P81 P80 1 1 1 1 1 0 (Note3) 1 1 Read/Write R/W After reset Port 8 Function register 7 6 5 4 3 2 1 0 P87F P86F P85F P84F P83F P82F P81F P80F 0 0 0 0 0 0 0: Port 1: 0: Port 1: bit Symbol P8FC (0023H) Read/Write W After reset Function 0: Port 1: CSZB 0: Port 1: CSZC 0 Refer to following table 0: Port 1: CS1 0 0: Port 1: CS0 Port 8 Function r
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TMP92CZ26A 3.7.7 Port 9 (P90 to P92, P96, P97) P90 to P92 are 3-bit general-purpose I/O port. I/O can be set on bit basis using the control register. Resetting sets P90 to P92 to input port and all bits of output latch to”1”. P96 to P97 are 2-bit general-purpose input port. Writing “1” in the corresponding bit of P9FC enables the respective functions. Resetting resets the P9FC to “0”, and sets all bits to input ports.
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TMP92CZ26A Reset Direction control (on bit basis) Internal data bus P9CRwrite Function control (on bit basis) P9FCwrite S Output latch A S Selector P9 write P91(RXD0) P92(SCLK0, CTS0 ) B SCLK0 output S B Selector P9 read A RXD0 input SCLK0 input CTS0 input Figure 3.7.15 P91, 92 Internal data bus Reset Function control P9FC write AVCC TSICR0 Switch for TSI typ.
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TMP92CZ26A Port 9 register P9 (0024H) bit Symbol Read/Write 7 6 P97 P96 5 4 3 2 0 P91 P90 R/W Data from external port (Output latch register is set to “1”) R Data from external port After reset 1 P92 Port 9 control register 7 P9CR (0026H) 6 5 4 3 bit Symbol Read/Write After reset Function 2 1 0 P92C P91C W 0 P90C 0 0 Refer to following table Port 9 function register 7 P9FC (0027H) 6 bit Symbol Read/Write After reset 5 4 3 2 P96F W 0 0: Input port 1: INT4 Function
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TMP92CZ26A Port A (PA0 to PA7) Port A0 to A7 are 8-bit general-purpose input ports with pull-up resistor. In addition to functioning as general-purpose I/O ports, port A0 to A7 can also Key-on wake-up function as Keyboard interface. The various functions can each be enabled by writing a “1” to the corresponding bit of the Port A Function Register (PAFC). Resetting resets all bits of the register PAFC to “0” and sets all pins to be input port. INTKEY Rising edge -ditection Internal data bus 3.7.
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TMP92CZ26A Port A register PA (0028H) bit Symbol Read/Write After reset 7 6 5 4 3 2 1 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 R Data from external port Port A Function register bit Symbol PAFC (002BH) Read/Write After reset Function 7 6 5 4 3 2 1 0 PA7F PA6F PA5F PA4F PA3F PA2F PA1F PA0F 0 0 0 0: KEY IN disable 0 0 1: KEY IN enable 0 0 0 W Port A Drive register bit Symbol PADR (008AH) Read/Write After reset Function 7 6 5 4 3 2 1 0 PA7D PA6D PA5D PA4D P
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TMP92CZ26A Port C (PC0 to PC7) PC0 to PC7 are 8-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets Port C to an input port. It also sets all bits of the output latch register to “1”. In addition to functioning as a general-purpose I/O port, Port C can also function as input pin for timers (TA0IN, TA2IN), input pin for external interruption (INT0 to INT3), Extension address function (EA26, EA27, EA28) and output pin for Key (KO8).
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TMP92CZ26A (2) PC1 (INT1, TA0IN), PC3 (INT3, TA2IN) Reset Direction control Internal data bus PCCR write Function control PCFCwrite S PC1 (INT1,TA0IN) PC3 (INT3, TA2IN) Output latch PCwrite S B Selector A PC read Level/edge selection and Rising/Falling selection INT1 INT3 IIMC TA0IN TA2IN Figure 3.7.
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TMP92CZ26A (3) PC4 (EA26), PC5 (EA27), PC6 (EA28) Reset Direction control (on bit basis) PCCRwrite Internal data bus Function control (on bit basis) PCFC write S A B Selector S Output latch PC write PC4(EA26) PC5(EA27) PC6(EA28) C EA26 EA27 EA28 S B Selector PC read A Figure 3.7.22 Port C4, C5, C6 (4) PC7 (KO8) Reset Direction control PCCR write Function control Internal data bus PCFC write PC7(KO8) S Output latch Open-drain enable PC write S B Selector PC read A Figure 3.7.
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TMP92CZ26A Port C register PC (0030H) bit Symbol Read/Write After reset 7 6 5 4 3 2 1 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 R/W Data from external port (Output latch register is set to “1”) Port C control register PCCR (0032H) bit Symbol Read/Write After reset Function 7 6 5 4 3 2 1 0 PC7C PC6C PC5C PC4C PC3C PC2C PC1C PC0C 0 0 0 0 0 0 W 0 0 0: Input 1: Output Port C function register PCFC (0033H) bit Symbol Read/Write After reset Function 7 6 5 4 3 2 1 0
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TMP92CZ26A 3.7.10 Port F (PF0 to PF5, PF7) Port F0 to F5 are 6-bit general-purpose I/O ports. Resetting sets PF0 to PF5 to be input ports. It also sets all bits of the output latch register to “1”. In addition to functioning as general-purpose I/O port pins, PF0 to PF5 can also function as the output for I2S0, I2S1. A pin can be enabled for I/O by writing a “1” to the corresponding bit of the Port F Function Register (PFFC). Port F7 is 1-bit general-purpose output port.
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TMP92CZ26A Reset Direction control (on bit basis) Internal data bus PFCR write Function control (on bit basis) PFFC write S Output latch S A Selector PF write B I2S0CKO output I2S1CKO/X1D4output PF0 (I2S0CKO) PF3 (I2S1CKO) S B Selector PF read A Figure 3.7.
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TMP92CZ26A (2) Port F7 (SDCLK), Port F7 is general-purpose output port. In addition to functioning as general-purpose output port, PF7 can also function as the SDCLK output. Internal data bus Reset Function control (on bit basis) PFFC write A S S Output latch SDCLK Selector B PF write PF read Figure 3.7.
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TMP92CZ26A Port F register 7 bit Symbol PF (003CH) Read/Write After reset 6 PF7 R/W 1 5 4 3 2 1 0 PF5 PF4 PF3 PF2 PF1 PF0 R/W Data from external port (Output latch register is set to “1”) Port F control register 7 6 bit Symbol PFCR (003EH) Read/Write After reset Function 5 4 3 2 1 0 PF5C PF4C PF3C PF2C PF1C PF0C 0 0 0 0 W 0 0 Refer to following table Port F function register 7 bit Symbol PFFC (003FH) Read/Write After reset PF7F W 1 Function 0: Port 1: SDCLK 6 5 4
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TMP92CZ26A 3.7.11 Port G (PG0 to PG5) PG0 to PG5 are 6-bit input port and can also be used as the analog input pins for the internal AD converter. PG3 can also be used as ADTRG pin for the AD converter. PG2, PG3 can also be used as MX, MY pin for Touch screen interface. (PG) register is prohibited to access by byte. All the instruction (Arithmetic/Logical/ Bit operation and rotate/shift instruction) access by byte are prohibited. Word access is Internal data bus always needed.
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TMP92CZ26A Port G register 7 PG (0040H) 6 Bit Symbol Read/Write After reset 5 4 3 2 1 0 PG5 PG4 PG3 PG2 PG1 PG0 R Data from external port Note: Selection of the input channel of AD converter and ADTRG input mode register is enabled by setting AD converter.
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TMP92CZ26A 3.7.12 Port J (PJ0 to PJ7) PJ0 to PJ4 and PJ7 are 6-bit output port. Resetting sets the output latch PJ to “1”, and they output “1”. PJ5 to PJ6 are 2-bit input/output port. In addition to functioning as port, Port J also functions as output pins for SDRAM ( SDRAS , SDCAS , SDWE , SDLLDQM, SDLUDQM, and SDCKE), SRAM ( SRWR , SRLLB and SRLUB ) and NAND-Flash(NDALE and NDCLE). Above setting is used the function register PJFC.
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TMP92CZ26A Reset Direction control PJCR write Internal data bus Function control PJFC write S Output latch A S Selector PJ write NDALE, NDCLE output B S B Selector PJ read A Figure 3.7.
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TMP92CZ26A Port J register bit Symbol PJ (004CH) Read/Write 7 6 5 4 3 2 1 0 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 1 1 1 1 3 2 1 0 R/W 1 After reset Data from external port (Output latch register is set to “1”) 1 Port J control register 7 bit Symbol PJCR (004EH) Read/Write After reset Function 6 5 PJ6C PJ5C 4 W 0 0 0: Input, 1: Output Port J function register bit Symbol PJFC (004FH) Read/Write After reset Function 7 6 5 4 3 2 1 0 PJ7F PJ6F PJ5F PJ4F PJ3F PJ2F
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TMP92CZ26A 3.7.13 Port K (PK0 to PK7) PK0 to PK7 are 8-bit output ports. Resetting sets the output latch PK to “0”, and PK0 to PK7 pins output “0”. In addition to functioning as output port function, Port K also function as output pins for LCD controller (LCP0, LHSYNC, LLOAD, LFR, LVSYNC, and LGOE0 to LGOE2). Above setting is used the function register PKFC.
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TMP92CZ26A Port K register PK (0050H) bit Symbol Read/Write After reset 7 6 5 4 3 2 1 0 PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 0 0 0 0 0 0 0 0 R/W Port K function register PKFC (0053H) bit Symbol Read/Write After reset Function 7 6 5 4 3 2 1 0 PK7F PK6F PK5F PK4F PK3F PK2F PK1F PK0F 0 0 0 0 0 0:Port 1: LHSYNC 0: Port 1: LVSYNC W 0:Port 1:LGOE2 0:Port 1:LGOE1 0:Port 1:LGOE0 0 0: Port 1: LFR 0 0: Port 1: LLOAD 0 0: Port 1: LCP0 Port K drive register PKDR
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TMP92CZ26A 3.7.14 Port L (PL0 to PL7) PL0 to PL7 are 8-bit output ports. Resetting sets the output latch PL to “0”, and PL0 to PL7 pins output “0”. In addition to functioning as a general-purpose output port, Port L can also function as a data bus for LCD controller (LD0 to LD7). Above setting is used the function register PLFC. Reset Internal data bus Function control PLFC write R Output latch PL write LD0 to LD7 A S Selector B PL read Figure 3.7.
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TMP92CZ26A Port L register PL (0054H) bit Symbol Read/Write After reset 7 6 5 4 3 2 1 0 PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 0 0 0 0 0 0 0 0 R/W Port L function register PLFC (0057H) bit Symbol Read/Write After reset Function 7 6 5 4 3 2 1 0 PL7F PL6F PL5F PL4F PL3F PL2F PL1F PL0F 0 0 0 0: Port 0 0 W 0 0 0 1: Data bus for LCDC (LD7 toLD0) Port L drive register PLDR (0095H) bit Symbol 7 6 5 4 3 2 1 0 PL7D PL6D PL5D PL4D PL3D PL2D PL1D PL0D 1
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TMP92CZ26A 3.7.15 Port M (PM1, PM2, PM7) PM1, PM2 and PM7 are 3-bit output ports. Resetting sets the output latch PM to “1”, and PM1, PM2 and PM7 pins output “1”. In addition to functioning as output ports, Port M also function as output pin for timers (TA1OUT), output pins for RTC alarm ( ALARM ), output pin for melody/alarm generator (MLDALM, MLDALM ) and Power control pin (PWE). Above setting is used the function register PMFC.
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TMP92CZ26A Reset Function control (on bit basis) Internal data bus PMFC write S Output latch S A Y Selector B PM write PM2 ( ALARM , MLDALM ) PM read MLDALM ALARM A S Y Selector B Figure 3.7.39 Port M2 Reset Function control (on bit basis) Internal data bus PMFC write S Output latch PM write S A Y Selector B PM read PWE Figure 3.7.
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TMP92CZ26A Port M register 7 PM (0058H) bit Symbol Read/Write After reset 6 5 4 3 PM7 R/W 1 2 1 PM2 PM1 0 R/W 1 1 Port M function register 7 bit Symbol PMFC (005BH) Read/Write After reset 6 5 4 3 PM7F W 0 2 1 PM2F PM1F 0 W 0: Port 1: PWE Function 0 0 0: Port 1: ALARM at =1, MLDALM at =0 0: Port 1: MLDALM at =1, TA1OUT at =0 Port M drive register 7 PMDR (0096H) bit Symbol Read/Write After reset Function 6 5 4 3 PM7D 2 1 PM2D PM1D R/W R/W 1
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TMP92CZ26A 3.7.16 Port N (PN0 to PN7) PN0 to PN7 are 8-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets Port N to an input port. In addition to functioning as a general-purpose I/O port, Port N can also function as interface pin for key-board (KO0 to KO7). This function can set to open-drain type output buffer.
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TMP92CZ26A Port N register bit Symbol PN (005CH) Read/Write After reset 7 6 5 4 3 2 1 0 PN7 PN6 PN5 PN4 PN3 PN2 PN1 PN0 R/W Data from external port (Output latch register is set to “1”) Port N control register bit Symbol PNCR (005EH) Read/Write After reset Function 7 6 5 4 3 2 1 0 PN7C PN6C PN5C PN4C PN3C PN2C PN1C PN0C 0 0 0 0 1: Output 0 0 0 W 0 0: Input Port N function register bit Symbol PNFC (005FH) Read/Write After reset Function 7 6 5 4 3 2 1 0 P
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TMP92CZ26A 3.7.17 Port P (PP1 to PP7) Port P1 to P5 are 6-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port P1 to P5 to input port and output latch to “0”. In addition to functioning as general-purpose I/O port pins, P0 to P5 can also function as output pin for timers (TA3OUT, TA5OUT, TA7OUT), input pin for timers (TB0IN0, TB1IN0), input pin for external interruption (INT5 to INT7). Port P6 and P7 are 2-bit output port.
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TMP92CZ26A Reset Direction control (on bit basis) PPCR write Internal data bus Function control (on bit basis) PPFC write R Output latch A S Selector B PP write PP3 (INT5, TA7OUT) TA7OUT S B Selector PP read A Level/edge selection and Rising/Falling selection INT5 IIMC Figure 3.7.
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TMP92CZ26A Internal data bus Reset Function control (on bit basis) PPFC write R Output latch A S Selector PP write B TB0OUT0 output TB1OUT0 output Figure 3.7.
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TMP92CZ26A Port P register PP (0060H) bit Symbol Read/Write After reset 7 6 5 PP7 PP6 PP5 4 0 0 3 2 1 PP4 PP3 PP2 R/W Data from external port (Output latch register is cleared to “0”) 0 PP1 Port P control register 7 6 bit Symbol PPCR (0062H) Read/Write After reset Function 5 4 PP5C PP4C 0 0 3 2 1 PP3C PP2C W 0 0 0: Input 1: Output 0 PP1C 0 Port P function register PPFC (0063H) bit Symbol Read/Write After reset Function 7 6 5 PP7F PP6F PP5F 4 0 0 0 0:Port 1:TB1
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TMP92CZ26A 3.7.18 Port R (R0 to R3) Port R0 to R3 are 4-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port R0 to R3 to input port and output latch to “0”. In addition to functioning as general-purpose I/O port pins, PR0 to PR3 can also function as SPI controller pin (SPCLK, SPCS , SPDO and SPDI). Above setting is used the control register PRCR and function register PRFC.
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TMP92CZ26A Reset Direction control (on bit basis) Internal data bus PRCR write Function control (on bit basis) PRFC write S A Selector B R Output latch PR write SPDO, SPCS , SPCLK PR read PR1(SPDO), PR2( SPCS ), PR3(SPCLK) S B Selector A Figure 3.7.
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TMP92CZ26A Port R register 7 PR (0064H) 6 5 4 bit Symbol Read/Write 3 2 1 0 PR3 PR2 PR1 PR0 R/W Data from external port After reset (Output latch register is cleared to “0”) Port R control register 7 PRCR (0066H) 6 5 4 bit Symbol Read/Write After reset Function 3 2 1 0 PR3C PR2C PR1C PR0C W 0 0 0: Input, 1: Output 0 0 Port R function register 7 PRFC (0067H) 6 5 4 bit Symbol Read/Write After reset 3 2 1 0 PR3F PR2F PR1F PR0F 0 0 W 0: Port 1: SPCLK Function P
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TMP92CZ26A 3.7.19 Port T (PT0 to PT7) Port T0 to T7 are 8-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port T0 to T7 to input port and output latch to “0”. In addition to functioning as general-purpose I/O port pins, PT0 to PT7 can also function as data bus pin for LCD controller (LD8 to LD15). Above setting is used the control register PTCR and function register PTFC.
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TMP92CZ26A Port T register bit Symbol PT (00A0H) Read/Write 7 6 5 4 3 2 1 0 PT7 PT6 PT5 PT4 PT3 PT2 PT1 PT0 R/W Data from external port (Output latch register is cleared to “0”) After reset Port T control register PTCR (00A2H) bit Symbol Read/Write After reset Function 7 6 5 4 3 2 1 0 PT7C PT6C PT5C PT4C PT3C PT2C PT1C PT0C 0 0 0 0 0 0 W 0 0 0: Input 1: Output Port T function register PTFC (00A3H) bit Symbol Read/Write After reset Function 7 6 5 4 3 2
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TMP92CZ26A 3.7.20 Port U (PU0 to PU7) Port U0 to U7 are 8-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port U0 to U7 to input port and output latch to “0”. In addition to functioning as general-purpose I/O port pins, PU0 to PU7 can also function as data bus pin for LCD controller (LD16 to LD23) and SDCLK input function. Above setting is used the control register PUCR and function register PUFC.
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TMP92CZ26A Reset Direction control (on bit basis) PUCR wirte Internal data bus Function control (on bit basis) PUFC write R Output latch A S Selector B PU write LD21 S B Selector PU read A Figure 3.7.
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TMP92CZ26A Port U register PU (00A4H) Bit Symbol Read/Write After reset 7 6 5 4 3 2 1 0 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 R/W Data from external port (Output latch register is cleared to “0”) Port U control register PUCR (00A6H) Bit Symbol Read/Write After reset Function 7 6 5 4 3 2 1 0 PU7C PU6C PU5C PU4C PU3C PU2C PU1C PU0C 0 0 0 0 0 0 W 0 0 0: Input 1: Output Port U function register PUFC (00A7H) Bit Symbol Read/Write After reset Function 7 6 5 4 3 2 1
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TMP92CZ26A 3.7.21 Port V (PV0 to PV4, PV6, PV7) Port V0 to V2, V6 and V7 are 5-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port V0 to V2, V6 and V7 to input port and output latch to “0”. In addition to functioning as general-purpose I/O port pins, PV can also function as input or output pin for SBI (SDA, SCL) and output for SIO(SCLK0) (Note). Above setting is used the control register PVCR and function register PVFC.
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TMP92CZ26A Internal data bus Reset R Output latch PV3 PV4 PV write PV read Figure 3.7.58 Port V3, V4 Reset Direction control (on bit basis) Internal data bus PVCR write Function control (on bit basis) PVFC write A R Output latch S PV6(SDA) Selector PV write Open-drain enable PVFC2 B SDA,SCL output S B Selector PV read A SDA,SCL input Figure 3.7.
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TMP92CZ26A Port V register PV (00A8H) bit Symbol Read/Write After reset 7 6 PV7 PV6 5 4 3 2 1 0 PV4 PV3 PV2 R/W PV1 PV0 R/W Data from external port Data from external port (Output latch register is cleared to “0”) (Output latch register is cleared to “0”) Port V control register PVCR (00AAH) bit Symbol Read/Write After reset Function 7 6 PV7C PV6C 5 4 3 2 PV2C 0 0 0: Input 1: Output 0 1 0 PV1C PV0C W 0 0 0: Input 1: Output Port V function register PVFC (00ABH) bit Sym
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TMP92CZ26A 3.7.22 Port W (PW0 to PW7) Port W0 to W7 are 8-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port W0 to W7 to input port and output latch to “0”. Above setting is used the control register PWCR and function register PWFC. Reset Direction control (on bit basis) Internal data bus PWCR write Function control (on bit basis) PWFC write PW0 to PW7 R Output latch PW write S B Selector PW read A Figure 3.7.
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TMP92CZ26A Port W register bit Symbol PW (00ACH) Read/Write 7 6 5 4 3 2 1 0 PW7 PW6 PW5 PW4 PW3 PW2 PW1 PW0 R/W Data from external port (Output latch register is cleared to “0”) After reset Port W control register PWCR (00AEH) bit Symbol Read/Write After reset Function 7 6 5 4 3 2 1 0 PW7C PW6C PW5C PW4C PW3C PW2C PW1C PW0C 0 0 0 0 0 0 W 0 0 0: Input 1: Output Port W function register PWFC (00AFH) bit Symbol Read/Write After reset Function 7 6 5 4 3 2
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TMP92CZ26A 3.7.23 Port X (PX4, PX5 and PX7) Port X5 and X7 are 2-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port X5 and X7 to input port and output latch to “0”. In addition to functioning as general-purpose I/O port pins, PX5 and PX7 can also function as USB clock input pin (X1USB). Above setting is used the control register PXCR and function register PXFC. Port X4 is 1-bit general-purpose output port. Resetting sets output latch to “0”.
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TMP92CZ26A Reset Direction control (on bit basis) PXCR write Internal data bus Function control (on bit basis) PXFC write PX5 (X1USB) PX7 R Output latch PX write S B Selector PX read A X1USB input Figure 3.7.
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TMP92CZ26A Port X register 7 bit Symbol PX (00B0H) Read/Write 6 PX7 R/W 5 4 PX5 PX4 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 R/W Data from external port After reset (Output latch register is cleared to “0”) Port W control register 7 bit Symbol PXCR (00B2H) Read/Write After reset Function 6 PX7C W 0 0: Input 1: Output 5 4 PX5C W 0 0: Input 1: Output Port W function register 7 bit Symbol PXFC (00B3H) Read/Write After reset 6 PX7F W 0 5 4 PX5F PX4F W 0 0:Port 1: Reserved 0 0:
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TMP92CZ26A 3.7.24 Port Z (PZ0 to PZ7) Port Z0 to Z7 are 8-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port Z0 to Z7 to input port and output latch to “0”. In addition to functioning as general-purpose I/O port function, Port Z can also function as communication for debug mode (EI_PODDATA, EI_SYNCLK, EI_PODREQ, EI_REFCLK, EI_TRGIN, EI_COMRESET, EO_MCUDATA and EO_MCUREQ). These functions are operated when it is started in debug mode.
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TMP92CZ26A Reset Debug mode Direction control (on bit basis) Internal data bus PZCR write R Output latch A S PZ6(EO_MCUDATA) PZ7(EO_MCUREQ) Selector PZ write B EO_MCUDATA EO_MCUREQ S B Selector PZ read A Figure 3.7.
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TMP92CZ26A Port Z register PZ (0068H) bit Symbol Read/Write After reset 7 6 5 4 3 2 1 0 PZ7 PZ6 PZ5 PZ4 PZ3 PZ2 PZ1 PZ0 R/W Data from external port (Output latch register is cleared to “0”) Port Z control register bit Symbol PZCR (006AH) Read/Write After reset Function 7 6 5 4 3 2 1 0 PZ7C PZ6C PZ5C PZ4C PZ3C PZ2C PZ1C PZ0C 0 0 0 0 0 0 W 0 0 0: Input 1: Output Port Z drive register bit Symbol PZDR (009AH) Read/Write After reset Function 7 6 5 4 3 2 1 0 P
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TMP92CZ26A 3.8 Memory Controller (MEMC) 3.8.1 Functions TMP92CZ26A has a memory controller with a variable 4-block address area that controls as follows. (1) 4-block address area support Specifies a start address and a block size for 4-block address area (block0 to 3). * SRAM or ROM : All CS-blocks (CS0 to CS3) are supported. * SDRAM : Either CS1 or CS2-blocks is supported. * Page-ROM : Only CS2-blocks is supported. * NAND-Flash : CS setting is not needed.
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TMP92CZ26A 3.8.2 Control register and Operation after reset release This section describes the registers to control the memory controller, the state after reset release and necessary settings. (1) Control Register The control registers of the memory controller are as follows and Table 3.8.1 to Table 3.8.2. ･ Control register: BnCSH/BnCSL(n=0 to 3, EX) Sets the basic functions of the memory controller that is the connecting memory type, the number of waits to be read and written.
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TMP92CZ26A Table 3.8.
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TMP92CZ26A Table 3.8.
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TMP92CZ26A (2) Operation after releasing reset The data bus width at starting is determined depending on state of AM1/AM0 pins after releasing reset. Then, the external memory access as follows; AM1 0 0 1 1 AM0 0 1 0 1 Start Mode Don’t use this setting Start with 16-bit data bus (note) Don’t use this setting Start with BOOT(32-bit internal-MROM ) Note: A memory to be used to start after releasing reset is either NOR-Flash or Masked-ROM.NAND-Flash, SDRAM can’t be used.
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TMP92CZ26A 3.8.3 Basic functions and register setting In this section, setting of the block address area, the connecting memory and the number of waits out of the memory controller’s functions are described. (1) Block address area specification The block address areas of CS0 to CS3 are specified by MSAR0 to MSAR3 and MAMR0 to MAMR3. (a) Memory start address register Figure 3.8.1 shows the memory start address registers. MSAR0 to MSAR3 set the start addresses for the CS0 to CS3 areas.
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TMP92CZ26A (b) Memory address mask registers Figure 3.8.3 shows the memory address mask registers. MAMR0 to MAMR3 are used to set the size of the CS0 to CS3 areas by specifying a mask for each bit of the start address set in MAMR0 to MAMR3. The compare operation used to determine if an address is in the CS0 to CS3 areas is only performed for bus address bits corresponding to bits set to 0 in these registers. Also, the address bits that can be masked by MAMR0 to MAMR3 differ between CS0 to CS3 areas.
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TMP92CZ26A (c) Setting memory start addresses and address areas An example of specifying a 64-Kbyte address area starting from 010000H using the CS0 areas i describes. Set 01H in MSAR0 (Corresponding to the upper 8 bits of the start address). Next, calculate the difference between the start address and the anticipated end address (01FFFFH) based on the size of the CS0 area. Bits 20 to 8 of the result correspond to the mask value to be set for the CS0 area.
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TMP92CZ26A Table 3.8.3 Valid Area Sizes for Each CS Area Size (Byte) 256 512 32 K 64 K 128 K 256 K 512 K 1M 2M 4M 8M ○ ○ ○ ○ ○ ○ ○ ○ ○ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ CS area CS0 CS1 CS2 CS3 ○ ○ Note:“Δ” indicates areas that cannot be set by memory start address register and address mask register combinations.
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TMP92CZ26A (2) Connection Memory Specification Setting BnCSH specifies the memory type to be connected with the block address areas. The interface signal is output according to the set memory as follows; BnCSH BnOM1 BnOM0 Function 0 0 SRAM/ROM (Default) 0 1 (Reserved) 1 0 (Reserved) 1 1 SDRAM Note1: SDRAM should be set only with CS1 or CS2 . (3) Data Bus Width Specification The data bus width is set for every block address area.
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TMP92CZ26A Operand Data Size (bit) Operand Start Bus width of Mem ory Address (bit) 4n + 0 8/16/32 8 16/32 8/16 32 8 16 32 4n + 1 8 4n + 2 4n + 3 4n + 0 8 16/32 8 4n + 1 16 32 16 CPU Data CPU Address 8 4n + 2 16 32 8 4n + 3 16 32 8 4n + 0 16 32 8 4n + 1 16 32 32 8 4n + 2 16 32 8 4n + 3 16 32 4n + 0 4n + 1 4n + 1 4n + 2 4n + 2 4n + 3 4n + 3 4n + 3 (1) 4n + 0 (2) 4n + 1 4n + 0 (1) 4n + 1 (2) 4n + 2 (1) 4n + 1 (2) 4n + 2 4n + 1 (1) 4n + 2 (2) 4n + 1 4n + 2 4n + 2 (1) 4n + 3 (2) 4n + 4 (
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TMP92CZ26A (4) Wait control The external bus cycle completes for two states minimum(25 ns at fSYS = 80 MHz). Setting the BnCSL specifies the number of waits in the write cycle, and BnCSL specifies the number of waits in the read cycle.
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TMP92CZ26A (5) Recovery (Data hold) cycle control Some memory have an AC specification about data hold time from CE or OE for read cycle and a data confliction problem may occur. To avoid this problem, 1-dummy cycle can be inserted after CSm-block access cycle by setting “1” to BmCSH register. This 1-dummy cycle is inserted when the next cycle is for another CS-block. BnCSH 0 No dummy cycle is inserted (Default). 1 Dummy cycle is inserted.
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TMP92CZ26A (6) Adjust Function for the timing of control signal This function can change the timing of CSn , CSZx , CSXx ,R/ W , RD , WRxx , SRWR and SRxxB signals and adjust the timing according to the set-up/hold time of the memories. As for the CSn , CSZx , CSXx ,R/ W and WRxx , SRWR , SRxxB (at write cycle), it can be changed for only 1 CS area. While for RD and SRxxB (at read cycle), it can be changed for all CS areas.
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TMP92CZ26A RDTMGCR0/1 00 TCRS = 0.5 × fSYS (Default) 01 TCRS = 1.5 × fSYS 10 TCRS = 2.5 × fSYS 11 TCRS = 3.5 × fSYS TCRS:The delay from (CSn) to (RD,SRxxB). T1 T2 T3 TW Tn-2 Tn-1 Tn SDCLK (80MHz) A23 to 0 CSn R/ W TAC TAC RD Read cycle SRxxB TCRS TCRH Input D15 to 0 WRxx Write cycle SRWR TCWH TCWS SRxxB D15 to 0 Output TCWS Note: TW cycle is inserted by setting BnCSL register. If it is set to 0-Wait, TW cycle is not inserted.
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TMP92CZ26A (7) Basic bus timing (a) External read/write cycle (0 waits) SDCLK (60 MHz) T1 T2 CSn A23 to A0 RD , SRxxB Read D15 to D0 Input SRWR , SRxxB Write WRxx D15 to D0 Output (b) External read/write cycle (1 wait) SDCLK (60 MHz) T1 TW T2 CSn A23 to A0 RD , SRxxB Read D15 to D0 Input SRWR , SRxxB Write WRxx D15 to D0 Output 92CZ26A-195
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TMP92CZ26A (c) External read bus cycle (1 wait + TAC: 1fSYS + TCRS: 1.5fSYS + TCRH: 1fSYS) External write bus cycle (1 wait + TAC: 1fSYS + TCWS/H: 1.
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TMP92CZ26A (e) External read/write cycle (4 waits + WAIT pin input mode) T1 T2 T3 T4 T5 T6 TW SDCLK (80 MHz) CSn A23 to 0 RD SRxxB Read D15 to 0 Input SRWR , SRxxB Write WRxx D15 to 0 Output WAIT Sampling (f) Sampling External read bus cycle (4 waits + WAIT pin input mode +TAC: 1fSYS + TCRS: 1.5fSYS + TCRH: 1fSYS) External write bus cycle (4 waits + WAIT pin input mode + TAC: 1fSYS + TCWS/H: 1.
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TMP92CZ26A (8) Connecting to external memory Figure 3.8.4 shows an example of how to connect external 16-bit SRAM and 16-bit NOR flash to the TMP92CZ26A. TMP92CZ26A 16-bit SRAM RD OE SRLLB LDS SRLUB UDS SRWR R/W CS0 D [15:0] CE Not connect I/O [16:1] A0 A1 A0 A2 A1 A3 A2 16-bit NOR flash OE WE CS2 CE DQ [15:0] A0 A1 A2 Figure 3.8.
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TMP92CZ26A 3.8.4 ROM Page mode Access Control This section describes ROM page mode accessing and how to set registers. ROM page mode is set by PMEMCR. (1) Operation and how to set the registers TMP92CZ26A supports ROM access with the page mode. The ROM access with the page mode is specified only in CS2. Setting PMEMCR to “1” sets the memory access of CS2 to ROM page mode access. The number of read cycles is set by the PMEMCR.
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TMP92CZ26A 3.8.5 Internal Boot ROM Control This section describes about built-in boot ROM. For the specification of S/W in boot ROM, refer to the section 3.4 boot ROM. (1) BOOT mode BOOT mode is started by following AM1 and AM0 pins condition with reset.
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TMP92CZ26A (4) Disappearing boot ROM After boot sequence in BOOT mode, an application system program may continue to run without reset asserting. In this case, an external memory which is mapped 3FE000H to 3FFFFFH address can not be accessed because of boot ROM is assigned. To solve it, internal boot ROM can be disappered by setting BROMCR to “1”. This is initialized to “0” in BOOT mode. At another starting mode, this bit is initialized to “1”.
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TMP92CZ26A 3.8.6 Cautions (1) Note the timing between CS and RD If the load capacitance of the RD (Read signal) is greater than that of the CS (Chip select signal), it is possible that an unintended read cycle occurs due to a delay in the read signal. Such an unintended read cycle may cause a trouble as in the case of (a) in Figure 3.8.6. SDCLK (60 MHz) A23 to A0 CSm CSn RD (a) Figure 3.8.
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TMP92CZ26A (2) Note the NAND flash area setting Figure 3.8.8 shows a memory map for NAND flash. And since CS3 area is recommended to assign address from 000000H to 3FFFFFH, this case is explained. In this case, “NAND flash” and CS3 area are overlapped. But CS3 pin don’t become active by setting BROMCR to “1”. And also CS0 to CS3 , SDCS , CSXA to CSXB , CSZA to CSZD pins don’t become to active. Note1: In this case, the address from 000000H to 049FFFH of 296 Kbytes in CS3’s memory can’t be used.
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TMP92CZ26A 3.9 External Memory Extension Function (MMU) This is MMU function which can expand program/data area to 3.1G bytes by having 4-type local area. The recommendation address memory map is shown in Figure 3.9.1. However, when total capacity of used memory is less than 16M bytes, please refer to section of Memory controller. Setting of register in MMU is not necessary. An area which can be set as BANK is called LOCAL-area. Since the address for LOCAL area is fixed, it cannot be changed.
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TMP92CZ26A ND 0 CE Memory controller setting pin (512MB) Address memory map ND1CE 000000H pin (512MB) Internal I/O, RAM COMMON-X (2MB) CSXA CSXB 512MB(2MB× 256) 512MB(2MB× 256) CS3-area 4MB 200000H LOCAL-X (2MB) Bank 0 1 2 3 ・・・ 15 LOCAL-Y (2MB) Bank 0 1 2 3 ・・・ 15 ・・・ 255 256 ・・ 511 400000H ・・・ 63 CS1-area 4MB 600000H COMMON-Y (2MB) SDCS : 64MB*(SDRAM case 2MB× 32) or CS1 pin: 128MB (2MB× 64) 800000H LOCAL-Z (4MB) Bank 0 1 2 3 ・・・ 127 128 ・・・ 255 ・・・ 384 ・・・ 5
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TMP92CZ26A 92CZ26A LOCAL-X CSXA to CSXB , EA24 to 28 512MB×2=1024MB LOCAL-Y SDCS or CS1 128MB or *64MB CSXA 000000H Bank0 LOCAL-Z CSZA to CSZD , EA24 to 28 512MB×4=2048MB CSZA CSZD Bank0 Bank0 Bank384 127 511 Internal-I/O and Internal RAM 63 255 CSXB CSZB Bank256 Bank128 255 511 CSZC Bank256 383 Note: In case of connect SDRAM to Y-area, 64MB(2MB×32) is maximum Figure 3.9.
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TMP92CZ26A ND 0 CE pin (512MB) ND1CE pin (512MB) Memory controller setting Address memory map 000000H Internal-I/O, RAM COMMON-X (2MB) 200000H LOCAL-X (2MB) Internal Boot-ROM (8KB) 3FE000H 400000H LOCAL-Y (2MB) 600000H COMMON-Y (2MB) 800000H LOCAL-Z (4MB) Bank 0 1 2 3 ・・・ 15 CS2-area 8MB C00000H COMMON-Z (4MB) FFFF00H FFFFFFH SDCS pin 64MB(4MB×16) Vector area :Internal area : Overlapped with COMMON-Area and disabled setting as LOCAL-area.
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TMP92CZ26A 3.9.2 Control register There are 24-registers for MMU. They are prepared for 8-purpose using (as Program, read-data, write-data and LCDC-display-data, source-data for odd/even number channel DMA, destination-data for odd/even number channel DMA), and 3-local area (LOCAL-X, Y and Z). These 8-purpose registers can access a data accessed easily. (How to use) At first, set enable register and using bank-number of each LOCAL register.
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TMP92CZ26A 3.9.2.1 Program bank register The bank number used as program memory is set to these registers. In certain bank, cannot diverge directly to different bank of same local area. To change program bank number in the same local area is disable.
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TMP92CZ26A 3.9.2.2 LCD display bank register The bank page used as LCD display memory is set to these registers. Since the bank register for CPU and LCDC are prepared independently, the bank page for CPU (Program, Read-data, write-data) can change during LCD display on.
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TMP92CZ26A 3.9.2.3 Read-data bank register The bank number used as read-data memory is set to these registers. The following is an example which read data bank register of LOCAL-X is set to “1”. When “ldw wa, (xix)” instruction is executed, the bank becomes effective at only read data (operand) for xix address. (Example) ld ld ldw ldw xix, 200000h (localrx), 8001h wa,(localrx) wa, (xix) ; ; Set Read data bank.
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TMP92CZ26A 3.9.2.4 Write-data bank register The bank number used as write data memory is set to these registers. The following is an example which data bank register of LOCAL-X is set to “1”. When “ldw (xix), wa” instruction is extended, the bank becomes effective at only cycle for xix address. (Example) ld ld ldw ldw xix, 200000h (localwx), 8001h wa, (localwx) (xix), wa ; ; Set Write data bank.
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TMP92CZ26A 3.9.2.5 DMA-function bank register In addition to functioning as read/write function of CPU, this LSI can also function which transfer data at high-speed by internal DMAC becoming bus master. (Please refer to DMAC section) In Bank for only DMA that different from Bank for CPU or LCDC display data, although condition of program bank, read-bank and write-bank for CPU, bank of Source address and Destination address are enable during operate DMA.
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TMP92CZ26A LOCAL-X register for even-group DMA source bit Symbol LOCALESX (8A0H) 7 6 5 4 X7 X6 X5 X4 Read/Write After reset Function 2 1 0 X3 X2 X1 X0 0 0 0 0 R/W 0 0 0 0 Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.
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TMP92CZ26A LOCAL-X register for even-group DMA destination bit Symbol LOCALEDX (8A8H) 7 6 5 4 X7 X6 X5 X4 Read/Write After reset Function 2 1 0 X3 X2 X1 X0 0 0 0 0 R/W 0 0 0 0 Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.
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TMP92CZ26A LOCAL-X register for odd-group DMA source bit Symbol LOCALOSX Read/Write (8B0H) After reset Function 7 6 5 4 3 2 1 0 X7 X6 X5 X4 X3 X2 X1 X0 0 0 0 0 0 0 0 0 R/W Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.
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TMP92CZ26A LOCAL-X register for odd-group DMA destination LOCALODX (8B8H) bit Symbol 7 6 5 4 X7 X6 X5 X4 Read/Write After reset Function 2 1 0 X3 X2 X1 X0 0 0 0 0 R/W 0 0 0 0 Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.
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TMP92CZ26A 3.9.3 Setting example This is in case of using like following condition. No.
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TMP92CZ26A (b) Sub routine (Bank-0 in LOCAL-Y) Logical Physical address address 400000H 000000H 4000xxH 0000xxH No Instruction 16 17 org ldw 400000H (localwy),8001H 18 19 ldw ldw (locally), 8001H (localrz), 8001H 20 ld xiy,800000H 21 ld Comment ; ; Bank1 in LOCAL-Y is set to write-data for LCD Display RAM ; Bank1 in LOCAL-Y is set as LCD display RAM ; Bank0 in LOCAL-Z is set as read-data for Character-RAM 22 5000yyH 1000yyH wa,(xiy) : 23 24 ld ld (localpy), 82H xix, 400000H 25
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TMP92CZ26A 3.10 SDRAM Controller (SDRAMC) The TMP92CZ26A incorporates an SDRAM controller (SDRAMC) for accessing SDRAM that can be used as data memory, program memory, or display memory.
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TMP92CZ26A 3.10.1 Control Registers The SDRAMC has the following control registers.
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TMP92CZ26A 7 SDCMM (0253H) 6 SDRAM Command Register 5 4 3 Bit symbol Read/Write After reset Function 2 SCMM2 1 0 SCMM1 SCMM0 R/W 0 0 0 Command issue (Note 1) (Note 2) 000: Don’t care 001: Initialization sequence a. Precharge All command b. Eight Auto Refresh commands c.
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TMP92CZ26A 3.10.2 Operation Description (1) Memory access control The SDRAMC is enabled by setting SDACR to “1”. When one of the bus masters (CPU, LCDC, DMAC) generates a cycle to access the SDRAM address area, the SDRAMC outputs SDRAM control signals. Figure3.10.2 to Figure3.10.5 shows the timing for accessing the SDRAM. The number of SDRAM access cycles is controlled by the SDRAMC and does not depend on the number of waits controlled by the memory controller.
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TMP92CZ26A (b) Address multiplex function In access cycles, the A0 to A15 pins output low/column multiplexed addresses. The multiplex width is set by SDACR. Table3.10.2 shows the relationship between the multiplex width and low/column addresses. Table3.10.
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TMP92CZ26A 4CLK 3CLK 3CLK CA (n+2) CA (n+4) SDCLK SDCKE SDLUDQM SDLLDQM SDCS SDRAS SDCAS SDWE A10 RA A15-A0 RA CA (n) D15-D0 D (n) tRCD= 1CLK Bank Active D (n+2) CAS Latency=2CLK D (n+4) CAS Latency=2CLK Read CAS Latency=2CLK Read Read Figure3.10.
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TMP92CZ26A 3CLK 2CLK 2CLK CA (n+2) CA (n+4) SDCLK SDCKE SDLUDQM SDLLDQM SDCS SDRAS SDCAS SDWE A10 RA A15-A0 RA D15-D0 CA (n) D (n) D (n+2) tRCD= 1CLK Bank Active tWR= 1CLK D (n+4) tWR= 1CLK Write tWR= 1CLK Write Write Figure3.10.
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TMP92CZ26A (2) Execution of instructions on SDRAM The CPU can execute instructions that are stored in the SDRAM. However, the following operations cannot be performed. a) Executing the HALT instruction b) Changing the clock gear setting c) Changing the settings in the SDACR, SDCMM, and SDCISR registers These operations, if needed, must be executed by branching to other memory such as internal RAM. (3) Command interval adjustment function Command execution intervals can be adjusted for each command.
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TMP92CZ26A (d) Precharge command SDCLK PRECHARGE COMMAND NOP NOP Next Command NOP TRP *TRP=2CLK (SDCISR= “1”) (e) Read cycle SDCLK COMMAND NOP ACTIVE Row Address A15-A0 NOP READ Column Address NOP NOP Non MUX-address NOP ACTIVE Row Address DIN D15-D0 TRCD TRC *TRCD=2CLK (SDCISR= “1”) *TRC=6CLK (SDCISR= “101”) (f) Write cycle SDCLK COMMAND A15-A0 NOP ACTIVE Row Address NOP WRITE Column Address NOP PRECHARG Non MUX-address NOP Row Address DOUT D15-D0 T
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TMP92CZ26A (4) Read data shift function If the AC specifications of the SDRAM cannot be satisfied when data is read from the SDRAM, the read data can be latched in a port circuit so that the CPU can read the data in the next state. When this read data shift function is used, the read cycle requires additional one state. The write cycle is not affected. The timing waveforms for various cases are shown below.
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TMP92CZ26A (c) Full-page read, the read data shift function enabled (SDACR = “1”, = “0”) SDCLK COMMAND NOP A15-A0 ACTIVE READ NOP Row Address NOP NOP NOP ColumnAddress DIN1 D15-D0 DIN2 DIN3 Internal system clock DIN1 Internal data bus External data latch DIN2 DIN3 CPU data read (5) Read/Write commands The Read/Write commands to be used in 1-word read/single write mode can be specified by using SDACR.
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TMP92CZ26A (6) Refresh control The TMP92CZ26A supports two kinds of refresh commands: Auto Refresh and Self Refresh. (a) Auto Refresh When SDRCR is set to “1”, the Auto Refresh command is automatically issued at intervals specified by SDRCR. The Auto Refresh interval can be specified in a range of 47 states to 1248 states (0.78 μs to 20.8 μs at f SYS = 60 MHz). The CPU operation (instruction fetch and execution) is halted while the Auto Refresh command is being executed. Figure3.10.
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TMP92CZ26A (b) Self Refresh The Self Refresh Entry command is issued by setting SDCMM to “101”. Figure3.10.7 shows the Self Refresh cycle timing. Once Self Refresh is started, the SDRAM is refreshed internally without the need to issue the Auto Refresh command. Note 1: When standby mode is released by a system reset, the I/O registers are initialized and the Self Refresh state is exited. Note that the Auto Refresh function is also disabled at this time.
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TMP92CZ26A The Self Refresh state can be exited by the Self Refresh Exit command. The Self Refresh Exit command is executed when SDCMM is set to “110”. It is also executed automatically in synchronization with HALT mode release. In either of these two cases, Auto Refresh is performed immediately after the Self Refresh state is exited. Then, Auto Refresh is executed at specified intervals. Exiting the Self Refresh state clears SDCMM to “000”.
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TMP92CZ26A (7) SDRAM initialization sequence After reset release, the following sequence of commands can be executed to initialize the SDRAM. 1. Precharge All command 2. Eight Auto Refresh commands 3. Mode Register Set command The above commands are issued by setting SDCMM to “001”. While these commands are issued, the CPU operation (instruction fetch, execution) is halted.
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TMP92CZ26A (8) Connection example Figure3.10.10 shows an example of connections between the TMP92CZ26A and SDRAM. Table3.10.
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TMP92CZ26A 3.10.3 An Example of Calculating HDMA Transfer Time The following shows an example of calculating the HDMA transfer time when SDRAM is used as the transfer source. 1) Transfer from SDRAM to internal SRAM Conditions: System clock (fSYS) SDRAM read cycle SDRAM Auto Refresh interval Internal RAM write cycle Number of bytes to transfer : 60 MHz : Full page (5-1-1-1), 16-bit data bus 16-bit data bus : 936 states (15.
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TMP92CZ26A 3.10.4 Considerations for Using the SDRAMC This section describes the points that must be taken into account when using the SDRAMC. Please carefully read the following to ensure proper use of the SDRAMC. 1) WAIT access When SDRAM is used, the following restriction applies to memory access to other than the SDRAM. In the external WAIT pin input setting of the memory controller, the maximum external WAIT period that can be set is limited to “Auto Refresh interval × 8190”.
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TMP92CZ26A 3.11 NAND Flash Controller (NDFC) 3.11.1 Features The NAND Flash Controller (NDFC) is provided with dedicated pins for connecting with NAND Flash memory. The NDFC also has an ECC calculation function for error correction and supports two types of ECC calculation methods. The ECC calculation method using Hamming codes can be used for NAND Flash memory of SLC (Single Level Cell) type and is capable of detecting a single-bit error for every 256 bytes.
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TMP92CZ26A 3.11.1 Block Diagram NAND Flash Controller Channel 0 (NDFC0) ND_CE* Hamming ECC Generator ND_ALE ND_CLE ECC Code ND_RE* Internal Data Bus Timing Generator ND0CE NDCLE, NDALE, NDRE , ND WE* NDWE , ND_RB* D15~ D0 RS ECC Write Control Register Reed-Solomon ECC Generator DATA_OUT[15:0] DATA_IN[15:0] F/F 80-bit Address Data Reed-Solomon ECC Calculator Figure 3.11.
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TMP92CZ26A 3.11.2 Operation Description 3.11.2.1 Accessing NAND Flash Memory The NDFC accesses data on NAND Flash memory indirectly through its internal registers. This section explains the operations for accessing the NAND Flash. Since no dedicated sequencer is provided for generating commands to the NAND Flash, the levels of the NDCLE, NDALE, and NDCE pins must be controlled by software.
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TMP92CZ26A The NDRE and NDWE signals are explained next. Write and read operations to and from the NAND Flash are performed through the ND0FDTR register. The actual write operation completes not when the ND0FDTR register is written to but when the data is written to the external NAND Flash. Likewise, the actual read operation completes not when the ND0FDTR register is read but when the data is read from the external NAND Flash.
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TMP92CZ26A 3.11.3 ECC Control NAND Flash memory devices may inherently include error bits. It is therefore necessary to implement the error correction processing using ECC (Error Correction Code). Figure 3.11.4 shows a basic flowchart for ECC control.
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TMP92CZ26A 3.11.3.1 Differences between Hamming Codes and Reed-Solomon Codes The NDFC includes an ECC generator supporting NAND Flash memory devices of SLC (or 2LC: two states) type and MLC (or 4LC: four states) type. The ECC calculation using Hamming codes (supporting SLC) generates 22 bits of ECC for every 256 bytes of valid data and is capable of detecting and correcting a single-bit error for every 256 bytes. Error bit detection calculation and correction must be implemented by software.
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TMP92CZ26A 3.11.3.2 Error Correction Methods Hamming ECC • The ECC generator generates 44 bits of ECC for a page containing 512 bytes of valid data. The error correction process must be performed in units of 256 bytes (22 bits of ECC). The following explains how to implement error correction on 256 bytes of valid data using 22 bits of ECC. • If the NAND Flash to be used has a large-capacity page size (e.g. 2048 bytes), the error correction process must be repeated several times to cover the entire page.
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TMP92CZ26A Reed-Solomon ECC • The ECC generator generates 80 bits of ECC for up to 518 bytes of valid data. If the NAND Flash to be used has a large-capacity page size (e.g. 2048 bytes), the error correction process must be repeated several times to cover the entire page. • Basically no calculation is needed for error correction. If error detection is performed properly, the NDFC only needs to refer to the error address and error bit.
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TMP92CZ26A 3.11.4 Description of Registers NAND Flash Control 0 Register 7 6 5 4 3 2 1 0 NDFMCR0 (08C0H) bit Symbol WE ALE CLE CE0 CE1 ECCE BUSY ECCRST Read/Write R/W R/W R/W R/W R/W R/W R W Read-modifywrite instructions cannot be used.
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TMP92CZ26A (c) The bit is used for both Hamming and Reed-Solomon codes. This bit is used to enable or disable the ECC generator. To reset the ECC in the ECC generator (to set to “1”), the ECC generator must be enabled ( = “1”). (d) , , The , , and bits are used for both Hamming and Reed-Solomon codes to control the pins of the NAND Flash memory.
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TMP92CZ26A (i) The bit is used only for Reed-Solomon codes. When using Hamming codes, this bit should be set to “0”. The Reed-Solomon processing unit is comprised of two elements: an ECC generator and an ECC calculator. The latter is used to calculate the error address and error bit position. The error address and error bit position are calculated using an intermediate code generated from the ECC for written data and the ECC for read data.
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TMP92CZ26A NAND Flash Control 1 Register NDFMCR1 (08C2H) 7 6 bit Symbol INTERDY Read/Write R/W After reset 0 Ready interrupt 0: Disable 1: Enable Function (08C3H) bit Symbol 5 2 1 0 INTRSC BUSW ECCS SYSCKE R/W R/W R/W R/W 0 ReedSolomon calculation end interrupt 0: Disable 1: Enable 0 Data bus width 0 0 Clock ECC control calculation 0: 8-bit 1: 16-bit 0: Disable 0:Hamming 1: Enable 1: ReedSolomon 15 14 13 STATE3 STATE2 STATE1 Read/Write 4 3 12 11 10 STATE0 SEER1 SE
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TMP92CZ26A This bit is used to enable or disable the interrupt to be generated when the calculation of error address and error bit position has ended. The interrupt is enabled when this bit is set to “1” and disabled when “0”. (e) The bit is used for both Hamming and Reed-Solomon codes. This bit is used to enable or disable the interrupt to be generated when the status of the NDR/B pin of the NAND Flash changes from “busy” (0) to “ready” (1).
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TMP92CZ26A NDFDTR0 (1FF0H) bit Symbol 7 NAND Flash Data Register 0 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 D15 D14 D13 D12 D11 D10 D9 D8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write After reset R/W Function (1FF1H) bit Symbol NAND Flash Data Register (7-0) Read/Write After reset R/W Function NDFDTR1 (1FF2H)
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TMP92CZ26A Table 3.11.
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TMP92CZ26A NAND Flash ECC Register 0 6 5 4 3 7 NDECCRD0 (08C4H) (08C5H) NDECCRD1 (08C6H) (08C7H) NDECCRD2 (08C8H) (08C9H) NDECCRD3 (08CAH) (08CBH) NDECCRD4 (08CCH) (08CDH) ECCD4 ECCD3 2 1 0 ECCD2 ECCD1 ECCD0 0 0 bit Symbol Read/Write After reset Function ECCD7 ECCD6 ECCD5 0 0 0 15 14 13 12 11 10 9 8 bit Symbol Read/Write After reset Function ECCD15 ECCD14 ECCD13 ECCD12 ECCD11 ECCD10 ECCD9 ECCD8 0 0 0 0 0 7 NAND Flash ECC Register 1 6 5 4 3 R 0 0 0 NAND Fla
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TMP92CZ26A The NAND Flash ECC register is used to read ECC generated by the ECC generator. After valid data has been written to or read from the NAND Flash, setting NDFMCR0 to “0” causes the corresponding ECC to be set in this register. (The ECC in this register is updated when NDFMCR0 changes from “1” to “0”.) When Hamming codes are used, 22 bits of ECC are generated for up to 256 bytes of valid data.
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TMP92CZ26A NAND Flash Reed-Solomon Calculation Result Address Register 7 6 5 4 3 2 NDRSCA0 (08D0H) bit Symbol RS0A7 RS0A6 RS0A5 RS0A4 0 0 0 0 Read/Write After reset 0 RS0A2 RS0A1 RS0A0 0 0 0 0 R Function NAND Flash Reed-Solomon Calculation Result Address Register (7-0) 15 (08D1H) 1 RS0A3 14 13 12 11 10 bit Symbol 9 8 RS0A9 RS0A8 Read/Write R After reset 0 Function NDRSCA1 (08D4H) bit Symbol 7 6 5 4 RS1A7 RS1A6 RS1A5 RS1A4 Read/Write After reset 3 2 1 0
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TMP92CZ26A If error is found at only one address, the error address is stored in the NDRSCA0 register. If error is found at two addresses, the NDRSCA0 and NDRSCA1 registers are used to store the error addresses. In this manner, up to four error addresses can be stored in the NDRSCA0 to NDRSCA3 registers. The number of error addresses can be checked by NDFMCR1.
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TMP92CZ26A 3.11.5 An Example of Accessing NAND Flash of SLC Type 1. Initialization ; ; ***** Initialize NDFC ***** ; Conditions: 8-bit bus, CE0, SLC, 512 (528) bytes/page, Hamming codes ; ld ld 2.
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TMP92CZ26A Executing page program ; ***** Set auto page program***** ; ; ; ldw ld (ndfmcr0),20B0h ; WE enable, CLE enable (ndfdtr0),10h ; Auto page program command ldw (ndfmcr0),2010h ; WE disable, CLE disable Wait setup time (from Busy to Ready) ; ; ; 1. Flag polling 2.
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TMP92CZ26A 3. Read Reading valid data ; ***** Read valid data***** ; ldw (ndfmcr0),2010h ; CE0 enable ; ; ldw ld ldw (ndfmcr0),20B0h ; WE enable, CLE enable (ndfdtr0),00h ; Read command (ndfmcr0),20D0h ; ALE enable ld (ndfdtr0),xxh ; Address write (3 or 4 times) Wait setup time (from Busy to Ready) ; ; ; 1. Flag polling 2.
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TMP92CZ26A 4.
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TMP92CZ26A 3.11.6 An Example of Accessing NAND Flash of MLC Type (When the valid data is processed as 518byte) 1. Initialization ; ; ***** Initialize NDFC ***** ; ; 2.
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TMP92CZ26A Writing ECC to NAND Flash ; ***** Write dummy data & ECC ***** ; ldw (ndfmcr0),5088h ; ECC circuit disable, data write mode ldw (ndfdtr0),xxxxh ldw Write to 207-206hex address: > D79-64 (ndfdtr1),xxxxh ; Redundancy area data write ldw Write to 209-208hex address: > D63-48 (ndfdtr0),xxxxh ; Redundancy area data write ; ; ; ; Redundancy area data write Write to 20B-20Ahex address: > D47-32 ldw (ndfdtr1),xxxxh ldw Write to 20D-20Chex address: > D31-16 (ndfdtr0),xxxxh ; Redundancy area
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TMP92CZ26A 3. Read (including ECC data read) Reading valid data ; ***** Read valid data***** ; ; ; ldw ldw ldw (ndfmcr0),5008h ; CE1 enable (ndfmcr0),50A8h ; WE enable, CLE enable (ndfdtr0),0000h ; Read command 1 ldw ldw ldw (ndfmcr0),50C8h ; ALE enable (ndfdtr0),00xxh ; Address write (4 or 5 times) (ndfmcr0),50A8h ; WE enable, CLE enable ldw (ndfdtr0),0030h ; Read command 2 Wait set up time (from Busy to Ready) ; ; ; 1. Flag polling 2.
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TMP92CZ26A 4.
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TMP92CZ26A 3.11.7 An Example of Connections with NAND Flash TMP92CZ26A 100KΩ NAND Flash 0 NAND Flash 1 NDCLE NDALE CLE ALE CLE ALE NDRE NDWE RE WE RE WE R/B (open drain) R/B (open drain) I/O[15:0] I/O[7:0] 2KΩ NDR/B D[15:0] CE WP CE WP ND0CE ND1CE External circuits for Write Protect Note 1: A reset sets the NDRE and NDWE pins as input ports, so pull-up resistors are needed.
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TMP92CZ26A 3.12 8 Bit Timer (TMRA) The TMP92CZ26A features 8 channel (TMRA0 to TMRA7) built-in 8-bit timers. These timers are paired into 4 modules: TMRA01, TMRA23, TMRA45 and TMRA67. Each module consists of 2 channels and can operate in any of the following 4 operating modes.
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External input clock: TA0IN Prescaler clock φT0TMR φT4 8 Selector 4 Figure 3.12.
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External input clock: TA2IN Prescaler clock φT0TMR φT4 8 Selector 4 Figure 3.12.
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Lowfrequency clock (fs) Prescaler clock φT0TMR φT4 8 Selector 4 Figure 3.12.
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Lowfrequency clock (fs) Prescaler clock φT0TMR φT4 8 Selector 4 Figure 3.12.
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TMP92CZ26A 3.12.2 Operation of Each Circuit (1) Prescaler A 9-bit prescaler generates the input clock to TMRA01.The clock φT0 is selected using the prescaler clock selection register SYSCR0. The prescaler operation can be controlled using TA01RUN in the timer control register. Setting to 1 starts the count; setting to 0 clears the prescaler to 0 and stops operation. Table shows the various prescaler output clock resolutions.
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TMP92CZ26A (3) Timer registers (TA0REG and TA1REG) These are 8-bit registers, which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up counter, the comparator match detect signal goes active. If the value set in the timer register is 00H, the signal goes active when the up counter overflows. The TA0REG are double buffer structure, each of which makes a pair with register buffer.
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TMP92CZ26A (4) Comparator (CP0, CP1) The comparator compares the value in an up counter with the value set in a timer register. If they match, the up counter is cleared to 0 and an interrupt signal (INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time.
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TMP92CZ26A 3.12.3 SFR TMRA01 RUN Register 7 6 5 4 TA0RDE TA01RUN Bit symbol Read/Write R/W (1100H) After Reset 0 Function Double 3 I2TA01 0 In IDLE2 buffer mode 0: Disable 1: Enable 0: Stop 1: Operate 2 1 TA01PRUN TA1RUN R/W 0 0 TMRA01 Up counter prescaler (UC1) 0 TA0RUN 0 Up counter (UC0) 0: Stop and clear 1: Run (Count up) TA0REG double buffer control 0 Disable 1 Enable Count control 0 Stop and clear 1 Run (Count up) Note: The values of bits 4 to 6 of TA01RUN are “1” when read.
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TMP92CZ26A TMRA45 RUN Register 7 6 5 4 TA4RDE TA45RUN Bit symbol Read/Write R/W (1110H) After Reset 0 Function Double 3 I2TA45 0 In IDLE2 buffer mode 0: Disable 1: Enable 0: Stop 1: Operate 2 1 TA45PRUN TA5RUN R/W 0 0 TMRA45 Up counter prescaler (UC5) 0 TA4RUN 0 Up counter (UC4) 0: Stop and clear 1: Run (Count up) TA4REG double buffer control 0 Disable 1 Enable Count control 0 Stop and clear 1 Run (Count up) Note: The values of bits 4 to 6 of TA45RUN are “1” when read.
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TMP92CZ26A TMRA01 Mode Register TA01MOD Bit symbol (1104H) Read/Write After reset Function 7 6 5 4 TA01M1 TA01M0 PWM01 PWM00 3 2 1 0 TA1CLK1 TA1CLK0 TA0CLK1 TA0CLK0 0 0 0 R/W 0 0 0 0 0 Operation mode PWM cycle Source clock for TMRA1 Source clock for TMRA0 00: 8-bit timer mode 00: Reserved 00: TA0TRG 00: TA0IN pin 01: 16-bit timer mode 01: 2 6 01: φT1 01: φT1 10: 8-bit PPG mode 10: 2 7 10: φT16 10: φT4 11: 8-bit PWM mode 11: 2 8 11: φT256 11: φT16 TMRA0 input
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TMP92CZ26A TMRA23 Mode Register TA23MOD Bit symbol (110CH) Read/Write After reset Function 7 6 5 4 3 2 1 0 TA23M1 TA23M0 PWM21 PWM20 TA3CLK1 TA3CLK0 TA2CLK1 TA2CLK0 0 0 0 0 0 0 R/W 0 0 Operation mode PWM cycle TMRA3 clock for TMRA3 TMRA2 clock for TMRA2 00: 8-bit timer mode 00: Reserved 01: 16-bit timer mode 01: 2 10: 8-bit PPG mode 10: 2 11: 8-bit PWM mode 11: 2 00: TA2TRG 00: TA2IN pin 6 01: φT1 01: φT1 7 10: φT16 10: φT4 8 11: φT256 11: φT16 TMRA2 input cl
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TMP92CZ26A TMRA45 Mode Register TA45MOD Bit symbol (1114H) Read/Write After reset Function 7 6 5 4 3 2 1 0 TA45M1 TA45M0 PWM41 PWM40 TA5CLK1 TA5CLK0 TA4CLK1 TA4CLK0 0 0 0 0 0 0 R/W 0 0 Operation mode PWM cycle TMRA5 clock for TMRA5 TMRA4 clock for TMRA4 00: 8-bit timer mode 00: Reserved 01: 16-bit timer mode 01: 2 10: 8-bit PPG mode 10: 2 11: 8-bit PWM mode 11: 2 00: TA4TRG 00: low-frequency clock 6 01: φT1 01: φT1 7 10: φT16 10: φT4 8 11: φT256 11: φT16 TMRA
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TMP92CZ26A TMRA67 Mode Register TA67MOD Bit symbol (111CH) Read/Write After reset Function 7 6 5 4 3 2 1 0 TA67M1 TA67M0 PWM61 PWM60 TA7CLK1 TA7CLK0 TA6CLK1 TA6CLK0 0 0 0 0 0 0 R/W 0 0 Operation mode PWM cycle TMRA7 clock for TMRA7 TMRA6 clock for TMRA6 00: 8-bit timer mode 00: Reserved 01: 16-bit timer mode 01: 2 10: 8-bit PPG mode 10: 2 11: 8-bit PWM mode 11: 2 00: TA6TRG 00: low-frequency clock 6 01: φT1 01: φT1 7 10: φT16 10: φT4 8 11: φT256 11: φT16 TMRA
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TMP92CZ26A TMRA1 Flip-Flop Control Register 7 TA1FFCR (1105H) 6 5 4 Bit symbol 3 2 1 0 TA1FFC1 TA1FFC0 TA1FFIE TA1FFIS Read/Write R/W After reset 1 Function Readmodifywrite instructions are prohibited.
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TMP92CZ26A TMRA3 Flip-Flop Control Register 7 TA3FFCR (110DH) Bit symbol Readmodifywrite instructions are prohibited.
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TMP92CZ26A TMRA5 Flip-Flop Control Register 7 TA5FFCR (1115H) 6 5 4 Bit symbol 3 2 1 0 TA5FFC1 TA5FFC0 TA5FFIE TA5FFIS Read/Write R/W After reset 1 Function Readmodifywrite instructions are prohibited.
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TMP92CZ26A TMRA7 Flip-Flop Control Register 7 TA7FFCR (111DH) 6 5 4 Bit symbol 3 2 1 0 TA7FFC1 TA7FFC0 TA7FFIE TA7FFIS Read/Write R/W After reset 1 Function Readmodifywrite instructions are prohibited.
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TMP92CZ26A Timer Registers TA0REG (1102H) TA1REG (1103H) TA2REG (110AH) TA3REG (110BH) TA4REG (1112H) TA5REG (1113H) TA6REG (111AH) TA7REG (111BH) bit Symbol 7 6 5 4 − − − − Read/Write 3 2 1 0 − − − − 0 0 0 0 − − − − W After reset 0 0 0 0 bit Symbol − − − − Read/Write W After reset 0 0 0 0 0 0 0 0 bit Symbol − − − − − − − − After reset 0 0 0 0 0 0 0 0 bit Symbol − − − − − − − − Read/Write W Read/Write W After reset 0
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TMP92CZ26A 3.12.4 Operation in Each Mode (1) 8-bit timer mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. a. Generating interrupts at a fixed interval (Using TMRA1) To generate interrupts at constant intervals using TMRA1 (INTTA1), first stop TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and TA1REG register respectively. Then, enable the interrupt INTTA1 and start TMRA1 counting.
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TMP92CZ26A b. Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 3.2μs square wave pulse from the TA1OUT pin at fC= 50 MHz, use the following procedure to make the appropriate register settings. This example uses TMRA1; however, either TMRA0 or TMRA1 may be used.
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TMP92CZ26A c. Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparator output (TMRA0 match) TMRA0 up counter (when TA0REG = 5) TMRA1 up counter (when TA1REG = 2) 1 2 3 4 5 1 1 2 3 4 2 5 1 2 3 1 TMRA1 match output Figure 3.12.18 TMRA1 Count Up on Signal from TMRA0 (2) 16 bit timer mode Pairing the two 8-bit timers TMRA0 and TMRA1 configures a 16-bit interval timer.
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TMP92CZ26A The comparator match signal is output from TMRA0 each time the up counter UC0 matches TA0REG, though the up counter UC0 is not be cleared. In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse on which the values in the up counter UC1 and TA1REG match. When the match detect signal is output simultaneously from both the comparator TMRA0 and TMRA1, the up counters UC0 and UC1 are cleared to 0 and the interrupt INTTA1 is generated.
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TMP92CZ26A In this mode a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be smaller than the value set in TA1REG. Although the up counter for TMRA1 (UC1) is not used in this mode, TA01RUN should be set to 1 so that UC1 is set for counting. Figure 3.12.21 shows a block diagram representing this mode.
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TMP92CZ26A Example: To generate 1/4 duty 31.25 kHz pulses (at fC= 50 MHz) 32 μs * Clock state Clcok gear : 1/1 Prescaler of clock gear : 1/2 Calculate the value which should be set in the timer register. To obtain a frequency of 31.25 kHz, the pulse cycle t should be: t = 1/31.25kHz = 32 μs φT1 = 0.16 μs (at 50 MHz); 32 μs ÷ 0.16 μs = 200 Therefore set TA1REG to 200 (C8H) The duty is to be set to 1/4: t × 1/4 = 32 μs × 1/4 = 8 μs 8 μs ÷ 0.16 μs = 50 Therefore, set TA0REG = 50 = 32H.
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TMP92CZ26A (4) 8-bit PWM (Pulse width modulation) output mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output on the TA1OUT pin (Shared with PM1). TMRA1 can also be used as an 8-bit timer. The timer output is inverted when the up counter (UC0) matches the value set in the timer register TA0REG or when 2n counter overflow occurs (n = 6, 7 or 8 as specified by TA01MOD).
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TMP92CZ26A In this mode the value of the register buffer will be shifted into TA0REG if 2n overflow is detected when the TA0REG double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Match with TA0REG Up counter = Q1 Up counter = Q2 n 2 overflow Shift into TA0REG TA0REG (Value to be compared) Q1 Q2 Q2 Register buffer Q3 TA0REG (Register buffer) write Figure 3.12.
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TMP92CZ26A Table 3.12.
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TMP92CZ26A 3.13 16 bit timer / Event counter (TMRB) The TMP92CZ26A incorporates two multifunctional 16-bit timer/event counter (TMRB0, TMRB1) which have the following operation modes: • 16 bit interval timer mode • 16 bit event counter mode • 16 bit programmable pulse generation mode (PPG) Can be used following operation modes by capture function.
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(from TMRA01) TB0IN0 TA1OUT External INT input INT6 Prescaler clock φT0TMR 4 φT4 8 TB0RUN Count clock Slelector 92CZ26A-295 Figure 3.13.
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(from TMRA01) TB1IN0 TA3OUT External INT input INT7 Prescaler clock φT0TMR 4 φT4 8 TB1RUN Count clock Slelector 92CZ26A-296 Figure 3.13.
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TMP92CZ26A 3.13.2 Operation (1) Prescaler The 5-bit prescaler generates the source clock for TMRB0. The prescaler clock (φT0) is selected by the register SYSCR0 of clock gear. This prescaler can be started or stopped using TB0RUN. Counting starts when is set to “1”; the prescaler is cleared to “0” and stops operation when is cleared to “0”. The resolution of prescaler is showed in the Table 3.13.2. Table 3.13.
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TMP92CZ26A (3) Timer registers (TB0RG0H/L, TB0RG1H/L) These two 16-bit registers are used to set the interval time. When the value in the up counter UC10 matches the value set in this timer register, the comparator match detect signal will go active. Setting data for both upper and lower timer registers is needed. For example, using 2-byte data transfer instruction or using 1-byte data transfer instruction twice for lower 8 bits and upper 8 bits in order.
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TMP92CZ26A TB0RG0H/L and the register buffer 10 both have the same memory addresses (1188H and 1189H) allocated to them. If = “0”, the value is written to both the timer register and the register buffer 10. If = “1”, the value is written to the register buffer 10 only.
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TMP92CZ26A (4) Capture registers (TB0CP0H/L, TB0CP1H/L) These 16-bit registers are used to latch the values in the up counter (UC10). Data in the capture registers should be read all 16 bits. For example, using a 2-byte data load instruction or two 1-byte data load instructions. The least significant byte is read first, followed by the most significant byte. (during capture is read, capture operation is prohibited. In that case, the lower 8 bits should be read first, followed by the 8 bits.
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TMP92CZ26A (6) Comparators (CP10, CP11) CP10 and CP11 are 16-bit comparators which compare the value in the up counter UC10 with the value set in TB0RG0H/L or TB0RG1H/L respectively, in order to detect a match. If a match is detected, the comparator generates an interrupt (INTTB00 or INTTB01 respectively). (7) Timer flip-flops (TB0FF0, TB0FF1) These flip-flops are inverted by the match detect signals from the comparators and the latch signals to the capture registers.
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TMP92CZ26A 3.13.3 SFR TMRB0 RUN Register TB0RUN (1180H) Bit symbol Read/Write After Reset Function 7 6 TB0RDE R/W 0 − R/W 0 5 4 3 2 I2TB0 R/W 0 TB0PRUN R/W 0 1 0 TB0RUN R/W 0 Double Always In IDLE2 TMRB0 Up counter buffer write “0” mode prescaler 0: Stop and clear 1: Run (Count up) (UC10) 0: disable 0: Stop 1: enable 1: Operate Count operation , 0 Stop and clear 1 Count up Note: The 1, 4 and 5 of TB0RUN are read as “1” value.
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TMP92CZ26A TMRB0 Mode Register TB0MOD (1182H) Bit symbol 6 5 − − TB0CP0I Read/Write After Reset Prohibit readmodifywrite 7 Function 4 3 TB0CPM1 TB0CPM0 2 1 0 TB0CLE TB0CLK1 TB0CLK0 0 0 W* R/W 0 0 Always write “0”.
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TMP92CZ26A TMRB1 Mode Register TB1MOD (1192H) Bit symbol 6 5 − − TB1CP0I Read/Write After Reset Prohibit readmodifywrite 7 Function 4 3 TB1CPM1 TB1CPM0 2 1 0 TB1CLE TB1CLK1 TB1CLK0 0 0 W* R/W 0 0 Always write “0”.
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TMP92CZ26A TMRB0 Flip-Flop Control Register 7 TB0FFCR (1183H) Bit symbol Prohibit readmodifywrite Function 5 4 − TB0C1T1 TB0C0T1 − W* Read/Write After Reset 6 3 2 1 TB0E1T1 TB0E0T1 TB0FF0C1 R/W 1 1 Always write “11” 0 0 0 TB0FF0C0 W* 0 0 1 TB0FF0 inversion trigger Control TB0FF0 0: Disable trigger 00: Invert 1: Enable trigger 01: Set 1 10: Clear *Always read as “11”.
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TMP92CZ26A TMRB1 Flip-Flop Control Register 7 TB1FFCR (1193H) Bit symbol Prohibit readmodifywrite Function 5 4 − TB1C1T1 TB1C0T1 − W* Read/Write After Reset 6 3 2 1 TB1E1T1 TB1E0T1 TB1FF0C1 1 Always write “11” 0 0 TB1FF0C0 W* R/W 1 0 0 0 1 TB1FF0 inversion trigger Control TB1FF0 0: Disable trigger 00: Invert 1: Enable trigger 01: Set 1 10: Clear *Always read as “11”.
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TMP92CZ26A TB0RG0L (1188H) bit Symbol After reset 4 − − − − 3 2 1 0 − − − − 0 0 0 0 − − − − W 0 0 0 0 − − − − W 0 0 0 0 0 0 0 0 bit Symbol − − − − − − − − 0 0 0 0 0 0 0 0 − − − − − − − − Read/Write TB0RG1H bit Symbol (118BH) Read/Write W W After reset 0 0 0 0 0 0 0 0 bit Symbol − − − − − − − − 0 0 0 0 − − − − Read/Write After reset TB1RG0H bit Symbol (1199H) Read/Write TB1RG1L (119AH) 5 After reset After reset
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TMP92CZ26A 3.13.4 Operation in Each Mode (1) 16 bit timer mode Generating interrupts at fixed intervals In this example, the interrupt INTTB01 is set to be generated at fixed intervals. The interval time is set in the timer register TB0RG1H/L. 7 6 5 4 3 2 1 0 TB0RUN ← – 0 X X – – X 0 Stop TMRB0 INTETB0 ← X 1 0 0 X 0 0 0 Enable INTTB01and set interrupt level 4.
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TMP92CZ26A (3) 16-bit programmable pulse generation (PPG) output mode Square wave pulses can be generated at any frequency and duty ratio. The output pulse may be either low active or high active. The PPG mode is obtained by inversion of the timer flip-flop TB0FF0 that is to be enabled by the match of the up counter UC10 with timer register TB0RG0H/L or TB0RG1H/L and to be output to TB0OUT0. In this mode the following conditions must be satisfied.
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TMP92CZ26A The following block diagram illustrates this mode. TB0RUN TB0OUT0 (PPG output) Selector TB0IN0 φT1 φT4 φT16 16-bit up counter UC10 16-bit comparator Selector Match Clear F/F (TB0FF0) 16-bit comparator TB0RG0H/L TB0RG0-WR TB0RUN Register buffer 0 TB0RG1H/L Internal data bus Figure 3.13.
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TMP92CZ26A (4) Application examples of capture function Used capture function, they can be applied in many ways, for example; 1. One-shot pulse output from external trigger pulse 2. Frequency measurement 3. Pulse width measurement 1.
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TMP92CZ26A Example: To output 2ms one-shot pulse with 3ms delay to the external trigger pulse to TB0IN0pin *Clock state System clock : fSYS Prescaler clock : fSYS/4 Main setting Free-running Count with φT1 TB0MOD ← X X 1 0 1 0 0 1 TB0FFCR ← X X 0 0 0 0 1 0 Load to TB0CP0H/L at the rising edge of TB0IN0 Clear TB0FF0 to “0” Disable TB0FF0 inversion ← PPFC – 1 – – – – – X Select PP6 as TB0OUT0 pin (port setting) INTE56 ← X 1 0 0 X – – – Enable INT6 INTETB0 ← X 0
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TMP92CZ26A Count clock (Prescaler output clock ) c+p c TB0IN0 iput (External trigger pulse) Load into capture register 0 (TB0CP0H/L) INT6 occured Load into capture register 1 (TB0CP1H/L) INTTB01 occured Match with TB0RG1H/L Inversion enable Timer output pin TB0OUT0 Pulse width Enable inversioncaused by loading to TB0CP0H/L Disable inversion caused by loading into TB0CP1H/L (p) Figure 3.13.13 One-shot Pulse Output (without delay) 2.
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TMP92CZ26A 3. Pulse width measurement This mode allows measuring the H level width of an external pulse. While keeping the 16 bit timer/event counter counting (free-running) with the internal clock input, the external pulse is input through the TB0IN0 pin. Then the capture function is used to load the UC10 values into TB0CP0H/L and TB0CP1H/L at the rising edge and falling edge of the external trigger pulse respectively. The interrupt INT6 occurs at the falling edge of TB0IN0.
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TMP92CZ26A 3.14 Serial Channels (SIO) TMP92CZ26A includes 1 serial I/O channel (SIO0). For both channels either UART mode (Asynchronous transmission) or I/O interface mode (Synchronous transmission) can be selected. And, SIO0 includes data modulator that supports the IrDA 1.0 infrared data communication specification.
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TMP92CZ26A 3.14.
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TMP92CZ26A 3.14.2 Operation of Each Circuit (1) Prescaler There is a 6-bit prescaler for generating a clock to SIO0. The prescaler can be run by selecting the baud rate generator as the serial transfer clock. Table 3.14.1 shows prescaler clock resolution into the baud rate generator. Table 3.14.
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TMP92CZ26A (2) Baud rate generator The baud rate generator is the circuit which generates transmission/receiving clock and determines the transfer rate of the serial channels. The input clock to the baud rate generator, φT0, φT2, φT8 or φT32, is generated by the 6-bit prescaler which is shared by the timers. One of these input clocks is selected using the BR0CR field in the baud rate generator control register.
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TMP92CZ26A • Integer divider (N divider) For example, when the source clock frequency (fc) is 19.6608 MHz, the input clock is φT2, the frequency divider N (BR0CR) = 8, and BR0CR = 0, the baud rate in UART Mode is as follows: *Clock state Baud Rate = System clock Prescaler clock : : 1/1 1/2 fC/16 ÷ 16 = 19.6608106 × 106 ÷ 16 ÷ 8 ÷ 16 = 9600 (bps) 8 Note: The N + (16 – K) / 16 division function is disabled and setting BR0ADD is invalid.
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TMP92CZ26A Table 3.14.2 Transfer Rate Selection Unit (kbps) (When baud rate generator is used and BR0CR = 0) fSYS [MHz] Input Clock Frequency Divider N φT0 (fSYS/4) φT2 ( fSYS/16) φT8 (fSYS/64) φT32 (fSYS/256) 7.3728 1 115.200 28.800 7.200 1.800 ↑ 3 38.400 9.600 2.400 0.600 ↑ 6 19.200 4.800 1.200 0.300 ↑ A 11.520 2.880 0.720 0.180 ↑ C 9.600 2.400 0.600 0.150 ↑ F 7.680 1.920 0.480 0.120 9.8304 1 153.600 38.400 9.600 2.400 ↑ 2 76.800 19.200 4.
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TMP92CZ26A (3) Serial clock generation circuit This circuit generates the basic clock for transmitting and receiving data. • In I/O Interface Mode In SCLK Output Mode with the setting SC0CR = 0, the basic clock is generated by dividing the output of the baud rate generator by 2, as described previously. In SCLK Input Mode with the setting SC0CR = 1, the rising edge or falling edge will be detected according to the setting of the SC0CR register to generate the basic clock.
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TMP92CZ26A (6) The Receiving Buffers To prevent Overrun errors, the Receiving Buffers are arranged in a double-buffer structure. Received data is stored one bit at a time in Receiving Buffer 1 (which is a shift register). When 7 or 8 bits of data have been stored in Receiving Buffer 1, the stored data is transferred to Receiving Buffer 2 (SC0BUF); these causes an INTRX0 interrupt to be generated. The CPU only reads Receiving Buffer 2 (SC0BUF).
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TMP92CZ26A (8) Transmission controller • In I/O Interface Mode In SCLK Output Mode with the setting SC0CR = 0, the data in the Transmission Buffer is output one bit at a time to the TXD0 pin on the rising edge or falling of the shift clock which is output on the SCLK0 pin, according to the SC0CR setting.
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TMP92CZ26A Handshake function Serial Channels 0 has a CTS0 pin. Use of this pin allows data can be sent in units of one frame; thus, Overrun errors can be avoided. The handshake functions is enabled or disabled by the SC0MOD setting. When the CTS0 pin goes High on completion of the current data send, data transmission is halted until the CTS0 pin goes Low again. However, the INTTX0 Interrupt is generated, it requests the next data send to the CPU.
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TMP92CZ26A (9) Transmission buffer The transmission buffer (SC0BUF) shifts out and sends the transmission data written from the CPU form the least significant bit (LSB) in order. When all the bits are shifted out, the transmission buffer becomes empty and generates an INTTX0 interrupt. (10) Parity control circuit When SC0CR in the serial channel control register is set to 1, it is possible to transmit and receive data with parity. However, parity can be added only in 7-bit UART mode or 8-bit UART mode.
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TMP92CZ26A 2. Parity error The parity generated for the data shifted into receiving buffer 2 (SC0BUF) is compared with the parity bit received via the RXD pin. If they are not equal, a parity error is generated. Note: The parity error flag is cleared every time it is read. However, if a parity error is detected w¥twice in succession and the parity error flag is read between the two parity errors, it may seem as if the flag had not been cleared.
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TMP92CZ26A (12) Timing generation a.
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TMP92CZ26A 3.14.
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TMP92CZ26A 7 SC0CR (1201H) Prohibit to Read modify Write bit Symbol Read/Write After Reset Function 6 5 4 RB8 EVEN PE R R/W Undefined 0 0 Received Parity Parity data bit 8 0: odd addition 1: even 0: disable 1: enable 3 2 1 OERR PERR FERR R (cleared to 0 when read) 0 0 0 0 SCLKS IOC R/W 0 0 0: SCLK0 0: baud rate 1: error generator 1: SCLK0 Overrun Parity Framing 1: SCLK0 pin input I/O interface input clock selection 0 1 Baud rate generator SCLK0 pin input Edge selection for SCLK pin (
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TMP92CZ26A Bit symbol BR0CR (1203H) 7 6 5 4 3 2 1 0 − BR0ADDE BR0CK1 BR0CK0 BR0S3 BR0S2 BR0S1 BR0S0 0 0 0 0 0 0 0 0 Read/Write R/W After Reset Always write “0” Function +(16−K)/16 division 0: Disable 1: Enable 00: φT0 01: φT2 10: φT8 11: φT32 Divided frequency setting +(16−K)/16 division enable Setting the input clock of baud rate generator 0 Disable 00 Internal clock φT0 1 Enable 01 Internal clock φT2 10 Internal clock φT8 11 Internal clock φT32 7 6 5 4 b
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TMP92CZ26A 7 6 5 4 3 2 1 0 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0 7 6 5 4 3 2 1 0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 (Transmission) SC0BUF (1200H) (Receiving) Note: Prohibit read modify write for SC0BUF. Figure 3.14.9 Serial Transmission/Receiving Buffer Registers (channel 0, SC0BUF) SC0MOD1 (1205H) 7 6 Bit symbol I2S0 FDPX0 Read/Write R/W R/W After Reset 0 Function 5 4 3 2 0 IDLE2 duplex 0: Stop 0: half 1: Run 1: full Figure 3.14.
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TMP92CZ26A 3.14.4 Operation in each mode (1) Mode 0 (I/O Interface Mode) This mode allows an increase in the number of I/O pins available for transmitting data to or receiving data from an external shift register. This mode includes the SCLK output mode to output synchronous clock SCLK and SCLK input mode to input external synchronous clock SCLK.
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TMP92CZ26A a. Transmission In SCLK output mode 8-bit data and a synchronous clock are output on the TXD0 and SCLK0 pins respectively each time the CPU writes the data to the Transmission Buffer. When all data is output, INTES0 will be set to generate the INTTX0 interrupt. Timing to write transmisison data SCLK0 output ( = 0: rising edge mode) (Internal clock timing) SCLK0 output ( = 1: falling edge mode) TXD0 Bit0 Bit1 Bit6 Bit7 ITX0C (INTTX0 interrupt request) Figure 3.14.
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TMP92CZ26A b. Receiving In SCLK Output Mode the synchronous clock is output on the SCLK0 pin and the data is shifted to Receiving Buffer 1. This is initiated when the Receive Interrupt flag INTES0 is cleared as the received data is read. When 8-bit data is received, the data is transferred to Receiving Buffer 2 (SC0BUF) following the timing shown below and INTES0 is set to 1 again, causing an INTRX0 interrupt to be generated. Setting SC0MOD0 to 1 initiates SCLK0 output.
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TMP92CZ26A c. Transmission and Receiving (Full Duplex Mode) When Full Duplex Mode is used, set the Receive Interrupt Level to 0 and set enable the level of transmit interrupt(1 to 6). Ensure that the program which transmits the interrupt reads the receiving buffer before setting the next transmit data. The following is an example of this: Example: Channel 0, SCLK output Baud rate = 9600 bps fsys = 2.
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TMP92CZ26A (2) Mode 1 (7-bit UART Mode) 7-Bit UART Mode is selected by setting the Serial Channel Mode Register SC0MOD0 field to 01. In this mode a parity bit can be added. Use of a parity bit is enabled or disabled by the setting of the Serial Channel Control Register SC0CR bit; whether even parity or odd parity will be used is determined by the SC0CR setting when SC0CR is set to 1 (enabled).
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TMP92CZ26A Main routine 7 6 5 4 3 2 1 P9CR ← X X X X X − 0 0 − Set P91 to function as the RXD0 pin. P9FC ← − − X X X X SC0MOD0 ← − 1 − 1 0 − 1 Enable receiving in 8-bit UART mode. SC0CR 1 BR0CR ← − ← 0 − 0 − 0 0 0 − 1 − 1 − 0 − 0 − 0 Set the transfer rate to 9600 bps. INTES0 ← X 1 0 0 X 0 0 0 Enable the INTTX0 interrupt and set it to interrupt Add odd parity. level 4.
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TMP92CZ26A Protocol 1. Select 9-Bit UART Mode on the master and slave controllers. 2. Set the SC0MOD0 bit on each slave controller to 1 to enable data receiving. 3. The master controller transmits data one frame at a time. Each frame includes an 8-bit select code which identifies a slave controller. The MSB (bit 8) of the data () is set to 1. Start Bit0 1 2 3 4 5 6 7 Select code of slave controller 8 Stop “1” 4. Each slave controller receives the above frame.
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TMP92CZ26A Setting example: To link two slave controllers serially with the master controller using the internal clock fIO as the transfer clock. TXD RXD TXD Master RXD TXD RXD Slave1 Slave 2 Select code 00000001 Select code 00001010 • Setting the master controller Main routine P9FC ← X X XX X − 0 1 ← − − XX X − X 1 Set P90 and P91 to function as the TXD0 and RXD0 pins INTES0 ← X 1 0 0 X 1 0 1 Enable the INTTX0 interrupt and set it to Interrupt Level 4. P9CR respectively.
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TMP92CZ26A 3.14.5 Support for IrDA SIO0 includes support for the IrDA 1.0 infrared data communication specification. Figure 3.14.8 shows the block diagram. Transmisison data SIO0 TXD0 IR modulator IR transmitter & LED IR output Modem Receive data IR demodulator RXD0 IR receiver IR input TMP92CZ26A Figure 3.14.18 Block Diagram (1) Modulation of the transmission data When the transmit data is 0, the modem outputs 1 to TXD0 pin with either 3/16 or 1/16 times for width of baud-rate.
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TMP92CZ26A (3) Data format The data format is fixed as follows: • Data length: 8-bit • Parity bits: none • Stop bits: 1bit (4) SFR Figure 3.14.21 shows the control register SIRCR. Set the data SIRCR during SIO0 is stopping. The following example describes how to set this register: 1) SIO setting ; Set the SIO to UART Mode. ↓ 2) LD (SIRCR), 07H ; Set the receive data pulse width to 16×. 3) LD (SIRCR), 37H ; TXEN, RXEN Enable the Transmission and receiving.
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TMP92CZ26A (5) Notes 1. Baud rate for IrDA When IrDA is operated, set 01 to SC0MOD0 to generate baud-rate. The setting except above (TA0TRG, fIO and SCLK0-input) cannot be used. 2. The pulse width for transmission The IrDA 1.0 specification is defined in Table 3.14.3. Table 3.14.3 Baud rate and pulse width specifications Baud Rate Modulation Rate Tolerance Pulse Width Pulse Width Pulse width (% of rate) (minimum) (typical) (maximum) 88.55 μs 2.4 kbps RZI ±0.87 1.41 μs 78.13 μs 9.
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TMP92CZ26A SIRCR (1207H) Bit symbol 7 6 5 4 PLSEL RXSEL TXEN RXEN Read/Write 3 2 1 0 SIRWD3 SIRWD2 SIRWD1 SIRWD0 0 0 0 R/W After reset 0 0 Function Select transmit pulse width 0: 3/16 1: 1/16 Receive data 0: “H” pulse 1: “L” pulse 0 0 Transmit 0: disable 1: enable Receive 0: disable 1: enable 0 Select receive pulse width Set effective pulse width for equal or more than 2x × (value + 1) + 100ns Can be set : 1 to 14 Can not be set : 0, 15 Select receive pulse width Formula:
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TMP92CZ26A 3.15 Serial Bus Interface (SBI) The TMP92CZ26A has a 1-channel serial bus interface which an I2C bus mode. This circuit supports only I2C bus mode (Multi master). The serial bus interface is connected to an external device through PV6 (SDA) and PV7 (SCL) in the I2C bus mode. Each pin is specified as follows. PVFC2 11 I2C bus mode PVCR 11 PVFC 11 3.15.
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TMP92CZ26A 3.15.2 Serial Bus Interface (SBI) Control The following registers are used to control the serial bus interface and monitor the operation status.
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TMP92CZ26A 3.15.4 I2C Bus Mode Control Register The following registers are used to control and monitor the operation status when using the serial bus interface (SBI) in the I2C bus mode. Serial Bus Interface Control Register 0 SBICR0 (1247H) Prohibit ReadmodifyWrite 7 6 5 4 3 2 1 0 Bit symbol SBIEN − − − − − − − Read/Write R/W After Reset 0 0 0 0 0 0 0 Function SBI R 0 Always read “0”.
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TMP92CZ26A Serial Bus Interface Control Register 1 7 SBICR1 (1240H) Bit symbol BC2 Read/Write Function BC1 5 BC0 R/W After Reset Prohibit Readmodifywrite 6 0 0 0 4 3 ACK − R/W R 0 1 2 SCK2 1 0 SCK1 SCK0/ SWRMON 0 0/1(Note2) R/W 0 R/W Number of transferred bits Acknowledge Always Internal serial clock selection and (Note 1) mode read as software reset monitor specification “1”.
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TMP92CZ26A Serial Bus Interface Control Register 1 SBICR2 Bit symbol (1243H) Read/Write After reset Prohibit Function 7 6 MST TRX 5 4 3 BB PIN SBIM1 W 0 0 selection modifywrite 1 SBIM0 SWRST1 W (Note 1) 0 1 Master/Slave Transmitter Start/Stop Read- 2 0 0 SWRST0 W (Note 1) 0 0 0 Software reset generate Cancel Serial bus interface INTSBI Generation interrupt operating mode selection write “10” and “01”, then an internal reset signal is (Note 2) 0:Generate request 00: Po
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TMP92CZ26A Serial Bus Interface Status Register SBISR Bit symbol (1243H) Read/Write After reset Prohibit 7 6 5 4 MST TRX BB PIN 3 2 1 0 AL AAS AD0 LRB 0 0 0 0 R 0 0 0 1 Transmitter/ I C bus 2 INTSBI Arbitration Slave GENERAL Last Read-modif Slave status Receiver status interrupt lost address CALL received bit y-write monitor status monitor request detection match detection monitor 0:Slave monitor 0:Free monitor monitor detection monitor 0: 0 1:Mast
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TMP92CZ26A Serial Bus Interface Baud Rate Register 0 7 6 5 4 − − SBIBR0 Bit symbol − I2SBI (1244H) Read/Write W R/W Prohibit After reset 0 0 Read-modify Function -write Always IDLE2 read “0” 0: Stop 3 2 1 − − − 0 − R 1 1 R/W 1 1 1 0 Always read as “1” Always write “0”.
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TMP92CZ26A 3.15.5 Control in I2C Bus Mode (1) Acknowledge Mode Specification When slave address is matched or detecting GENERAL CALL, and set the SBICR1 to “1”, TMP92CZ26A operates in the acknowledge mode. The TMP92CZ26A generates an additional clock pulse for an Acknowledge signal when operating in Master Mode. In the transmitter mode during the clock pulse cycle, the SDA pin is released in order to receive the acknowledge signal from the receiver.
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TMP92CZ26A b. Clock synchronization In the I2C bus mode, in order to wired-AND a bus, a master device which pulls down a clock line to low-level, in the first place, invalidate a clock pulse of another master device which generates a high-level clock pulse. The master device with a high-level clock pulse needs to detect the situation and implement the following procedure. The TMP92CZ26A has a clock synchronization function for normal data transfer even when more than one master exists on the bus.
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TMP92CZ26A (6) Transmitter/Receiver selection Set the SBICR2 to “1” for operating the TMP92CZ26A as a transmitter. Clear the to “0” for operation as a receiver.
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TMP92CZ26A (8) Interrupt service requests and interrupt cancellation When a serial bus interface interrupt request (INTSBI) occurs, the SBICR2 is cleared to “0”. During the time that the SBICR2 is “0”, the SCL line is pulled down to the Low level. The is cleared to “0” when a 1-word of data is transmitted or received. Either writing/reading data to/from SBIDBR sets the to “1”. The time from the being set to “1” until the SCL line is released takes tLOW.
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TMP92CZ26A lost and SBISR is set to “1”. When SBISR is set to “1”, SBISR are cleared to “00” and the mode is switched to Slave Receiver Mode. Thus, clock output is stopped in data transfer after setting =“1”. SBISR is cleared to “0” when data is written to or read from SBIDBR or when data is written to SBICR2.
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TMP92CZ26A (14) Software Reset function The software Reset function is used to initialize the SBI circuit, when SBI is rocked by external noises, etc. An internal Reset signal pulse can be generated by setting SBICR2 to “10” and “01”. This initializes the SBI circuit internally. All command registers and status registers are initialized as well. SBICR1is automatically set to “1” after the SBI circuit has been initialized.
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TMP92CZ26A 3.15.6 Data Transfer in I2C Bus Mode (1) Device initialization Set the SBICR1, Set SBIBR1 to “1” and clear bits 7 to 5 and 3 in the SBICR1 to “0”. Set a slave address and the ( = “0” when an addressing format) to the I2CAR. For specifying the default setting to a slave receiver mode, clear “0” to the and set “1” to the , “10” to the .
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TMP92CZ26A b. Slave Mode z In the Slave Mode, the start condition and the slave address are received. After the start condition is received from the master device, while eight clocks are output from the SCL pin, the slave address and the direction bit that are output from the master device are received. When a GENERAL CALL or the same address as the slave address set in I2CAR is received, the SDA line is pulled down to the Low-level at the 9th clock, and the acknowledge signal is output.
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TMP92CZ26A (3) 1-word Data Transfer Check the by the INTSBI interrupt process after the 1-word data transfer is completed, and determine whether the mode is a master or slave. a. If = “1” (Master Mode) Check the and determine whether the mode is a transmitter or receiver. When the = “1” (Transmitter mode) Check the . When is “1”, a receiver does not request data. Implement the process to generate a stop condition (Refer to 3.15.6 (4)) and terminate data transfer.
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TMP92CZ26A When the is “0” (Receiver mode) When the next transmitted data is other than 8 bits, set and read the received data from SBIDBR to release the SCL line (data which is read immediately after a slave address is sent is undefined). After the data is read, becomes “1”. Serial clock pulse for transferring new 1 word of data is defined SCL and outputs “L” level from SDA pin with acknowledge timing.
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TMP92CZ26A Example: In case receive data N times INTSBI interrupt (After transmitting data) 7 6 5 4 3 2 1 0 SBICR1 Reg. ← X X X X X X X X ← SBIDBR Set the bit number of receive data and ACK. Load the dummy data. End of interrupt INTSBI interrupt (Receive data of 1st to (N−2) th) 7 6 5 4 3 2 1 0 ← SBIDBR End of interrupt Load the data of 1st to (N−2)th. Reg. INTSBI interrupt ((N−1) th Receive data) 7 6 5 4 3 2 1 0 SBICR1 Reg.
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TMP92CZ26A b. If = 0 (Slave Mode) In the slave mode the TMP92CZ26A operates either in normal slave mode or in slave mode after losing arbitration. In the slave mode, an INTSBI interrupt request occurs when the TMP92CZ26A receives a slave address or a GENERAL CALL from the master device, or when a GENERAL CALL is received and data transfer is complete, or after matching received address. In the master mode, the TMP92CZ26A operates in a slave mode if it losing arbitration.
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TMP92CZ26A Table 3.15.2 Operation in the slave mode 1 1 0 Conditions Process The TMP92CZ26A loses arbitration Set the number of bits a word in when transmitting a slave address and and write the transmitted data receives a slave address for which the to SBIDBR value of the direction bit sent from another master is “1”. In Salve Receiver Mode, the 1 0 TMP92CZ26A receives a slave address for which the value of the direction bit sent from the master is “1”.
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TMP92CZ26A (4) Stop condition generation When SBISR = “1”, the sequence for generating a stop condition start by writing “1” to SBICR2 and “0” to SBICR2. Do not modify the contents of SBICR2 until a stop condition has been generated on the bus. When the bus’s SCL line has been pulled Low by another device, the TMP92CZ26A generates a stop condition when the other device has released the SCL line and SDA pin rising.
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TMP92CZ26A (5) Restart Restart is used during data transfer between a master device and a slave device to change the data transfer direction. The following description explains how to restart when the TMP92CZ26A is in Master Mode. Clear SBICR2 to 0 and set SBICR2 to 1 to release the bus. The SDA line remains High and the SCL pin is released. Since a stop condition has not been generated on the bus, other devices assume the bus to be in busy state.
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TMP92CZ26A 3.16 USB Controller 3.16.1 Outline This USB controller (UDC) is designed for various serial links to construct USB system. The outline is as follows: (1) Compliant with USB rev1.1 (2) Full-speed: 12 Mbps (Not supported low-speed (1.
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TMP92CZ26A 3.16.1.1 System Configuration The USB controller (UDC) is consisted of following 3 blocks. 1. 900/H1 CPU I/F 2. UDC core block (DPLL, SIE, IFM and PWM), request controller, descriptor RAM and 4 endpoint FIFO 3. USB transceiver About above “1.” is explained at 3.16.2, and “2.” is 3.16.3.
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TMP92CZ26A 3.16.1.2 Example USB host USB device USB host TMP92CZ26A USB USB Connector Connector VCC GND VBUS INTx (detect rising) R6 R7 USB cable X2 10MHz PorTXX X1USB R1 R2 R8 R9 X1 VSS R4 OFF at “H” R5 R3 48MHz D+ D− OFF at "H" If using USB controller in TMP92CZ26A, above setting is needed. 1) Pull-up of D+ pin ・ In the USB standard, in Full Speed connection, D+ pin must be set to pull-up. And this pull-up is needed ON/OFF control by S/W. Recommendation value: R1=1.
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TMP92CZ26A 3.16.2 900/H1 CPU I/F The 900/H1 CPU I/F is a bridge between 900/H1 CPU and UDC and it mainly works following operations. • INTUSB (interrupt from UDC) generation • A bridge for SFR • USB clock control (48 MHz) 3.16.2.1 SFRs The 900/H1 CPU I/F have following SFRs to control UDC and USB transceiver.
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TMP92CZ26A 3.16.2.2 USBCR1 Register This register is used to set USB clock enables, transceiver enable etc. USBCR1 (07F8H) 7 6 1 0 bit Symbol TRNS_USE WAKEUP 5 4 3 2 SPEED USBCLKE Read/Write R/W R/W R/W R/W After reset 0 0 1 0 Function • TRNS_USE (Bit7) 0: Disable USB transceiver 1: Enable USB transceiver Set to “1” for TMP92CZ26A.
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TMP92CZ26A 3.16.2.3 USBINTFRn, MRn Register These SFRs control to generate INTUSB (only one interrupt to CPU) because the UDC outputs 23 interrupt source. The USBINTMRn are mask registers and the USBINTFRn are flag registers. In the INTUSB routine, execute operations according to generated interrupt source after checking USBINTFRn. The below is the common specification for all MASK and FLAG registers. (Common spec for all mask and flag registers.
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TMP92CZ26A 7 6 5 4 3 2 USBINTFR1 (07F0H) bit Symbol INT_URST_STR INT_URST_END INT_SUS INT_RESUME INT_CLKSTOP INT_CLKON Read/Write R/W R/W R/W R/W R/W R/W Prohibit to read modify write After reset 0 0 0 0 0 0 Function When read 0: Not generate interrupt When write 1 0 0: Clear flag 1: − 1: Generate interrupt Note: Above interrupts can release Halt state from IDLE2 and IDLE1 mode.
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TMP92CZ26A USBINTFR2 (07F1H) Prohibit to read modify write 7 6 5 4 3 2 1 0 bit Symbol EP1_FULL_A EP1_Empty_A EP1_FULL_B EP1_Empty_B EP2_FULL_A EP2_Empty_A EP2_FULL_B EP2_Empty_B Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 0 Function When read 0: Not generate interrupt When write 0: Clear flag 1: − 1: Generate interrupt Note: Above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode can not be released.
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TMP92CZ26A 7 6 5 4 3 2 1 USBINTFR4 (07F3H) bit Symbol INT_SETUP INT_EP0 INT_STAS INT_STASN INT_EP1N INT_EP2N INT_EP3N Read/Write R/W R/W R/W R/W R/W R/W R/W Prohibit to read modify write After reset 0 0 0 0 0 0 0 Function When read 0: Not generate interrupt 0 When write 0: Clear flag 1: Generate interrupt 1: − Note: Above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode can not be released.
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TMP92CZ26A • INT_STASN (Bit4) This is a flag for INT_STASN (change host status stage - interrupt). This is set to “1” when the USB host change to status stage at the Control read transfer type. This interrupt is needed if data length is less than wLength (specified by the host). But if the USB host change to status stage, this interrupt is always generated because of this signal is designed by using NAK of first packet. So, to avoid that this interrupt always generate, use mask register USBINTMRn.
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TMP92CZ26A USBINTMR1 bit Symbol (07F4H) Read/Write After reset 7 6 5 4 3 2 MSK_URST_STR MSK_URST_END MSK_SUS MSK_RESUME MSK_CLKSTOP MSK_CLKON R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 Function 0: Be not masked 1: Be masked • MSK_URST_STR (Bit7) This is a mask register for USBINTFR1. • MSK_URST_END (Bit6) This is a mask register for USBINTFR1. • MSK_SUS (Bit5) This is a mask register for USBINTFR1.
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TMP92CZ26A USBINTMR2 (07F5H) 7 6 5 4 3 2 1 0 bit Symbol EP1_MSK_FA EP1_MSK_EA EP1_MSK_FB EP1_MSK_EB EP2_MSK_FA EP2_MSK_EA EP2_MSK_FB EP2_MSK_EB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 1 1 1 1 1 1 1 1 Function 0: Be not masked 1: Be masked • EP1/2_MSK_FA/FB/EA/EB This is a mask register for USBINTFR2 or .
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TMP92CZ26A USBINTMR4 bit Symbol (07F7H) Read/Write After reset 7 6 5 4 3 2 1 MSK_SETUP MSK_EP0 MSK_STAS MSK_STASN MSK_EP1N MSK_EP2N MSK_EP3N R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 Function 0: Be not masked 1: Be masked • MSK_SETUP (Bit7) This is a mask register for USBINTFR4. • MSK_EP0 (Bit6) This is a mask register for USBINTFR4. • MSK_STAS (Bit5) This is a mask register for USBINTFR4.
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TMP92CZ26A 3.16.3 UDC CORE 3.16.3.1 SFRs The UDC CORE has following SFRs to control UDC and USB transceiver.
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TMP92CZ26A Figure 3.16.
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TMP92CZ26A Figure 3.16.
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TMP92CZ26A Figure 3.16.5 UDC CORE SFRs (3/3) Address Read/Write 07E0H R/W SFR Symbol 07E1H R FRAME_L 07E2H R FRAME_H 07E3H R ADDRESS *07E4H – Reserved *07E5H – Reserved Port_Status 07E6H R/W *07E7H – Reserved USBREADY 07E8H W Set Descriptor STALL Note: “*” is not used at TMP92CZ26A.
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TMP92CZ26A 3.16.3.2 EPx_FIFO Register (x: 0 to 3) This register is prepared for each endpoint independently. This is the window register from or to FIFO RAM. In the auto bus enumeration, the request controller in UDC set mode, which is defined at endpoint descriptor for each endpoint automatically. By this, each endpoint is set to voluntary direction.
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TMP92CZ26A 3.16.3.3 bmRequestType Register This register shows the bmRequestType field of device request.
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TMP92CZ26A 3.16.3.5 wValue Register There are 2 registers; the wValue_L register and wValue_H register. wValue_L shows the lower-byte of wValue field of device request and wValue_H register shows upper byte.
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TMP92CZ26A 3.16.3.8 Setup Received Register This register informs for the UDC that an application program recognized INT_SETUP interrupt. SetupReceived (07C8H) 7 6 5 4 3 2 1 0 bit Symbol D7 D6 D5 D4 D3 D2 D1 D0 Read/Write W W W W W W W W After reset 0 0 0 0 0 0 0 0 If this register is accessed by an application program, the UDC release to disabling access to EP0’s FIFO RAM because the UDC recognized the device request is received.
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TMP92CZ26A 3.16.3.10 Standard Request Register This register shows the standard request that is executing now. A bit which is set to “1” shows present executing request.
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TMP92CZ26A 3.16.3.12 DATASET Register This register shows whether FIFO has data or not. The application program can be checked it by accessing this register that whether FIFO has data or not. In the receiving status, when valid data transfer from USB host finished, bit which correspond to applicable endpoint is set to “1” and generate interrupt. And, when application read data of 1-packet, this bit is cleared to “0”.
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TMP92CZ26A Note1: In the receiving mode, if bits that A-packet and B-packet of applicable endpoint are “1”, read data that packet-number should be received, after checking DATASIZE. Note2: In the transmitting mode, if the both A and B bits are not “1”, it means that there are space in FIFO. So, write data for payload or less to FIFO. If transmission become short-packet, write “0” to EOP after writing data to the FIFO.
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TMP92CZ26A 3.16.3.13 EPx_STATUS Register (x: 0 to 7) These registers are status registers for each endpoint. The is common for all endpoint.
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TMP92CZ26A STATUS [2:0] (Bit4 to bit2) These bits show status of endpoint of UDC. The status show whether transfer it or not, or show result of transfer. . These are depending on transfer type. (For the Isochronous transfer type, refer 3.10.6.) 000: READY Receiving: Device can be received. In the endpoint 1 to 7, this register is initialized to “READY” by setting transfer type at SET_CONFIGURATION. In the endpoint 0, this register is initialized to “READY” by detecting USB reset from the host.
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TMP92CZ26A FIFO_DISABLE (Bit1) 0: FIFO enabled 1: FIFO disabled STAGE_ERROR (Bit0) 0: SUCCESS 1: ERROR This bit symbol shows FIFO status except EP0. If the FIFO is set to disabled, the UDC transmits NAK handshake forcibly for the all transfer. Disabled or enabled is set by COMMAND register. This bit is cleared to “0” when transfer type is changed. This bit symbol shows that status stage is not terminated correctly.
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TMP92CZ26A 3.16.3.14 EPx_SIZE Register (x: 0 to 7) These registers have following function. a) In the receiving, showing data number for 1 packet which was received correctly. b) In the transmitting, it shows payload size. But it shows length value when short packet is transferred. This register is not needed to read when it is transmitting. c) Showing dual packet mode and effective packet.
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TMP92CZ26A 7 EP1_SIZE_L_B (07A1H) 2 1 0 bit Symbol DATASIZE9 DATASIZE8 DATASIZE7 Read/Write R R R After reset 0 0 0 7 EP2_SIZE_L_B (07A2H) EP3_SIZE_L_B (07A3H) 1 0 DATASIZE8 DATASIZE7 Read/Write R R R After reset 0 0 0 2 1 0 DATASIZE9 DATASIZE8 DATASIZE7 Read/Write R R R After reset 0 0 0 2 1 0 DATASIZE9 DATASIZE8 DATASIZE7 Read/Write R R R After reset 0 0 0 2 1 0 EP5_SIZE_L_B (07A5H) bit Symbol DATASIZE9 DATASIZE8 DATASIZE7 Read/Write R R
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TMP92CZ26A 7 EP1_SIZE_H_A (07A9H) 2 1 0 bit Symbol DATASIZE9 DATASIZE8 DATASIZE7 Read/Write R R R After reset 0 0 0 7 EP2_SIZE_H_A (07AAH) 1 0 DATASIZE8 DATASIZE7 Read/Write R R R After reset 0 0 0 2 1 0 DATASIZE9 DATASIZE8 DATASIZE7 Read/Write R R R After reset 0 0 0 2 1 0 DATASIZE9 DATASIZE8 DATASIZE7 Read/Write R R R After reset 0 0 0 2 1 0 bit Symbol DATASIZE9 DATASIZE8 DATASIZE7 EP5_SIZE_H_A (07ADH) Read/Write R R R After reset 0 0
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TMP92CZ26A EP1_SIZE_H_B (07B1H) EP2_SIZE_H_B (07B2H) EP3_SIZE_H_B (07B3H) 2 1 0 bit Symbol 7 DATASIZE9 DATASIZE8 DATASIZE7 Read/Write R R R After reset 0 0 0 7 1 0 DATASIZE8 DATASIZE7 Read/Write R R R After reset 0 0 0 6 5 4 2 1 0 DATASIZE9 DATASIZE8 DATASIZE7 Read/Write R R R After reset 0 0 0 6 5 4 3 bit Symbol 2 1 0 DATASIZE9 DATASIZE8 DATASIZE7 Read/Write R R R After reset 0 0 0 2 1 0 bit Symbol DATASIZE9 DATASIZE8 DATASIZE7 Rea
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TMP92CZ26A 3.16.3.15 FRAME Register This register shows frame number which is issued with SOF token from the host and is used for Isochronous transfer type. Each HIGH and LOW registers show upper and lower bits.
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TMP92CZ26A 3.16.3.17 EOP Register This register is used when a dataphase of control transfer type terminate or when a short packet is transmitting of bulk-IN, interrupt-IN. EOP (07CFH) 7 6 5 4 3 2 1 0 bit Symbol EP7_EOPB EP6_EOPB EP5_EOPB EP4_EOPB EP3_EOPB EP2_EOPB EP1_EOPB EP0_EOPB Read/Write W W W W W W W W After reset 1 1 1 1 1 1 1 1 Note: EOP registers are not used at TMP92CZ26A.
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TMP92CZ26A 3.16.3.18 Port Status Register This register is used when a request of printer class is received. In case of request of GET_PORT_STATUS, the UDC operates automatically by using this data. Port Status (07E0H) 7 6 5 4 3 2 1 0 bit Symbol Reserved7 Reserved6 PaperError Select NotError Reserved2 Reserved1 Reserved0 Read/Write W W W W W W W W After reset 0 0 0 1 1 0 0 0 Note: TMP92CZ26A don’t use this register because of not support to printer-class.
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TMP92CZ26A 3.16.3.20 Request Mode Register This register set answer for Class Request either answer automatically in Hardware or control in software. Each bit mean kind of request. When this register is set applicable bit to “0”, answer is executed automatically by hardware. When this register is set applicable bit to “1”, answer is controlled by software. If request is received during hardware control, interrupt signal (INT_SETUP, INT_EP0, INT_STAS, INT_STATUSN) is set to disable.
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TMP92CZ26A 3.16.3.21 COMMAND Register This register sets COMMAND at each endpoint. This register can be set selection of endpoint in bit6 to bit4 and kind of COMMAND in bit3 to bit0. COMMAND for endpoint that is supported is ignored. 7 COMMAND (07D0H) 6 5 4 3 2 1 0 bit Symbol EP[2] EP[1] EP[0] Command[3] Command[2] Command[1] Command[0] Read/Write W W W W W W W After reset 0 0 0 0 0 0 0 Note: When writing to this register, the recovery time of 2clock at 12MHz is needed.
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TMP92CZ26A 1000: FIFO_ENABLE This COMMAND set FIFO of applicable endpoint to enable (EP1 to EP3). If FIFO is set to disable by FIFO_DISABLE COMMAND, this command is used for release disable condition. If during receiving packet, this becomes valid from next token. If USB_RESET is detected from host and RESET COMMAND execute and transfer mode is set by using SET_CONFIG and SET_INTERFACE request, applicable endpoint become FIFO_ENABLE condition.
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TMP92CZ26A 3.16.3.22 INT_Control Register INT_STASN interrupt is disabled and enabled by value that is written to this register. This is initialized to disable by external reset. When setup packet is received, it becomes to disable.
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TMP92CZ26A 3.16.3.24 EPx_MODE Register (x: 1 to 3) This register sets transfer mode of endpoint (EP1 to EP3). If transaction of SET_CONFIG and SET_INTERFACE are set to software control, this control must use appointed config or interface. When it is setting mode, access this register.
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TMP92CZ26A 3.16.3.25 EPx_SINGLE Register This register sets mode of FIFO in each endpoint (SINGLE/DUAL). EPx_SINGLE1 (07D1H) 7 bit Symbol 6 5 4 EP3_SELECT EP2_SELECT EP1_SELECT 3 2 1 0 EP3_SINGLE EP2_SINGLE EP1_SINGLE Read/Write R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 Note: Endpoint 3 support only SINGLE mode at TMP92CZ26A.
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TMP92CZ26A 3.16.3.27 USBREADY Register This register informs finishing writing data to descriptor RAM on UDC. After assigned data to descriptor RAM, write “0” to bit0. 7 USBREADY (07E6H) 6 5 4 3 2 1 0 bit Symbol USBREADY Read/Write R/W After reset 0 USBREADY (Bit0) 0: Writing to descriptor RAM was finished. 1: Writing to descriptor RAM is enable. (However, when during connecting to host, writing to descriptor RAM is prohibited.) USB host TMP92CZ26A VCC GND VSS CPU PortXX R1 = 1.
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TMP92CZ26A 3.16.3.28 Set Descriptor STALL Register This register sets whether returns STALL automatically in data stage or status stage for Set Descriptor Request. 7 Set Descriptor STALL (07E8H) 6 5 4 3 2 1 0 bit Symbol S_D_STALL Read/Write W After reset 0 Bit0: S_D_STALL 0: Software control (Default) 1: Automatically STALL 3.16.3.29 Descriptor RAM Register This register is used for store descriptor to RAM. Size of descriptor is 384 bytes.
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TMP92CZ26A 3.16.4 Descriptor RAM This area stores descriptor that is defined in USB. Device, Config, Interface, Endpoint and String descriptor must set to RAM by using following format.
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TMP92CZ26A Descriptor RAM setting example: Address Data Description Description Device Descriptor 500H 12H bLength 501H 01H bDescriptorType Device Descriptor 502H 00H bcdUSB (L) USB Spec 1.
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TMP92CZ26A Address Data Description Description Interface0 Descriptor AlternateSetting1 52BH 09H 52CH 04H bLength bDescriptorType 52DH 00H bInterfaceNumber 52EH 01H bAlternateSetting 52FH 02H bNumEndpoints 530H 07H bInterfaceClass 531H 01H bInterfaceSubClass 532H 02H bInterfaceProtocol 533H 00H iInterface Interface Descriptor AlternateSetting1 Endoint1 Descriptor 534H 07H bLength 535H 05H bDescriptorType Endpoint Descriptor 536H 01H bEndpointAddress OUT 537H 02H
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TMP92CZ26A Address DATA Description Description Endpoint3 Descriptor 559H 07H bLength 55AH 05H bDescriptorType Endpoint Descriptor 55BH 83H bEndpointAddress IN 55CH 03H bmAttributes Interrupt 8 bytes 55DH 08H wMaxPacketSize (L) 55EH 00H wMaxPacketSize (H) 55FH 01H bInterval 1 ms String Descriptor Length Setup Area 560H 04H bLength Length of String Descriptor0 561H 10H bLength Length of String Descriptor1 562H 00H bLength Length of String Descriptor2 563H 00H bLeng
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TMP92CZ26A 3.16.5 Device Request 3.16.5.1 Standard request UDC support automatically answer in standard request. (1) GET_STATUS Request This request returns status that is appointed of receive side, automatically. bmRequestType bRequest wValue wIndex wLength Data 10000000B GET_STATUS 0 0 2 Device, interface or endpoint status 10000001B Interface 10000010B endpoint Request to device returns following information according to priority of little endian.
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TMP92CZ26A (2) CLEAR_FEATURE request This request clears or disables particular function. bmRequestType bRequest wValue wIndex wLength Data 00000000B CLEAR_ FEATURE Feature selector 0 Interface endpoint 0 None 00000001B 00000010B • Reception side device Feature selector: 1 Present remote wakeup setting is disabled. Feature selector: except 1 STALL state • Reception side interface STALL state • Reception side end point Feature selector: 0 Halt of applicable endpoint is cleared.
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TMP92CZ26A (4) SET_ADDRESS request This request set device address. Following request answer by using this device address. Answer of request is used present device address until status stage of this request finish normally. bmRequestType bRequest wValue wIndex wLength Data 00000000B SET_ADDRESS Device Address 0 0 None (5) GET_DESCRIPTOR request This request returns appointed descriptor.
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TMP92CZ26A (6) SET_DESCRIPTOR request This request sets or enables particular function. bmRequestType 00000000B bRequest wValue wIndex wLength Data SET_ Descriptor Descriptor type 0 Descriptor Descriptor and or length Descriptor index Language ID Automatically answer of this request does not support. According to INT_SETUP interrupt, if receiving request was discerned as SET_DESCRIPTOR request, take back data after it confirmed EP0_DSET_A bit of DATASET register is “1”.
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TMP92CZ26A (9) GET_INTERFACE request This request returns AlternateSetting value that is set by appointed interface. bmRequestType bRequest wValue wIndex wLength Data 10000001B GET_ INTERFACE 0 Interface 1 Alternate setting If there is not appointed interface, it become to STALL state. (10) SET_INTERFACE request This request selects AlternateSetting in appointed interface.
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TMP92CZ26A 3.16.5.2 Printer Class Request UDC does not support “Automatic answer” of printer class request. Transaction for Class request is the same as vendor request; answering to INT_SETUP interrupt. 3.16.5.3 Vendor request (Class request) UDC doesn’t support “Automatic answer” of Vendor request. According to INT_SETUP interrupt, access register that device request is stored, and discern receiving request.
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TMP92CZ26A (b) Control write/request There is no dataphase bmRequestType bRequest wValue wIndex wLength Data 010000xxB Vendor peculiar Vendor peculiar Vendor peculiar 0 None When INT_SETUP is received, judge contents of receiving request by bmRequestType, bRequest, wValue, wIndex, wLength registers. And execute transaction for each request. As application, access Setup_Received register after request was judged. And it must inform that INT_SETUP interrupt was recognized to UDC.
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TMP92CZ26A Below is control flow in UDC watch from application.
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TMP92CZ26A 3.16.6 Transfer mode and Protocol Transaction UDC perform automatically in hardware as follows; • Receive packet • Judge address endpoint transfer mode • Error process • Confirm toggle bit CRC of data receiving packet • Generate including toggle bit CRC of data transmitting packet • Handshake answer (1) Protocol outline Format of USB packet is showed to below. This is processed during transmission and receiving by hardware into UDC.
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TMP92CZ26A (2) Transfer mode UDC support transfer mode in FULL speed. • FULL speed device Control transfer type Interrupt transfer type Bulk transfer type Isochronous transfer type Following is explanation of UDC operation in each transfer mode. Explanation of data flow is explanation until FIFO. (a) Bulk transfer type Bulk transfer type warrants transferring no error between host and function by using detect error and retry. Basically, 3 phases (token, data and handshake are used) are used.
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TMP92CZ26A (a-1) Transmission bulk mode Below is transaction format of bulk transfer during transmitting. • • • Token: IN Data: DATA0/DATA1, NAK, STALL Handshake: ACK Control flow Below is control-flow when UDC receive IN token. 1. Token packet is received and address endpoint number error is confirmed, and it checks whether conform applicable endpoint transfer mode with IN token. If it doesn’t conform, state return to IDLE. 2. Condition of EPx_STATUS register is confirmed.
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TMP92CZ26A IDLE Receive IN token Error ConfirmToken packet • PID • Address • Endpoint • Transfer mode • Error Invalid OK Confirm Handshake answer • Confirm STATUS register (Status) • Confirm DATASET register Stall FIFO empty OK More than MAX payload Generate DATA PID • Attach DATA0/DATA1 • Confirm Datasize register Transmit NAK Transmit STALL OK Transmit data Bit stuff error Set STATUS at STALL OK Attach CRC OK Time out • Set STATUS to TX_ERR • Put back addless pointer of FIFO Wait ACK to hos
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TMP92CZ26A (a-2) Receiving bulk mode Below is transaction format receiving bulk transfer type. It has to follow below. • Token: OUT • Data: DATA0/DATA1 • Handshake: ACK, NAK, STALL Control flow Below is control-flow when UDC receive IN token. 1. Token packet is received and address endpoint number error is confirmed, and it checks whether conform applicable endpoint transfer mode with OUT token. If it doesn’t conform, state return to IDLE. 2. Condition of status register is confirmed.
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TMP92CZ26A IDLE Receive OUT token Error Confirm Token packet • PID • Address • Endpoint • Transfer mode • Error Invalid OK Confirm Status • Confirm STATUS register (status) • Confirm FIFO’s condition Stall FIFO empty Error transaction • Set STATUS at RX_ERR • Put back FIFO address pointer OK Except data PID Time out Generate DATA PID • DATA0/DATA1 • Time out • Toggle check OK Toggle error • Set STATU Sat RX_ERR • Put back FIFO address pointer • Retry recognition clean data Receive data • Error • Co
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TMP92CZ26A (b) Interrupt transfer type Interrupt transfer type use transaction format same with transmission bulk transfer. When transmission by using toggle bit, hardware setting and answer in UDC are same with transmission bulk transfer. Interrupt transfer can be transferred without using toggle bit. In this case, if ACK handshake from host is not received, toggle bit is renewed, and finish normally. UDC clears FIFO for next transfer.
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TMP92CZ26A (c) Control transfer type Control transfer type is configured in below three stages. • Setup stage • Data stage • Status stage Data stage is skipped sometimes. Each stage is configured in one or plural transaction. UDC executes each transaction while managing of three stages in hardware. Control transfer type has below 3 type by whether there is data stage or not, or direction.
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TMP92CZ26A 3. Data packet is received. Device request of 8 bytes from SIE in UDC is transferred to below request register. • bmRequestType register • bmRequest register • wValue register • wIndex register • wLength register 4. After last data was transferred, and compare counted CRC with transferred CRC. If it doesn’t conform, it sets STATUS to RX_ERR and state return to IDLE. At this point it doesn’t return ACK, and host retry. 5.
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TMP92CZ26A IDLE Receive SETUP token Error Confirm Token packet • PID • Address • Endpoint • Transfer mode • Error Invalid OK Error transaction • Set STATUS to RX_ERR • Put back FIFO address point Confirm Status • Confirmation STATUS register (Status) OK Confirm DATA PID • DATA0 • Time out Except DATA0 PID Time out OK Error, more than payload data comunication Receive data • Error • Confirm receving data number OK Transmit ACK OK Normal finish transaction • Set DATASET register • Assert INT_SETUP
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TMP92CZ26A (c-2) Data stage Data stage is configured by one or plural transaction base on toggle sequence. Transaction is same with format transmission or receiving bulk transaction. However, below is difference. • Toggle bit start from “1” by SETUP stage. • It judges whether right or not by comparing IN and OUT token with direction bit of device request. If token that direction is reverse was received, it is recognized as status stage. • INT_ENDPOINT0 interrupt is asserted.
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TMP92CZ26A 4. If ACK handshake from host is received, • Set STATU to READY. • Assert INT_STATUS interrupt. It finishes normally by above transaction. If it is time out without receiving ACK from host, • Set STATUS register to TX_ERR and state return IDLE. And wait restring status stage. At this point, if new SETUP stage is started without status stage finish normally, UDC sets error to STATUS register. (c-3-2) OUT status stage Below is transaction format of OUT status stage.
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TMP92CZ26A (c-4) Stage management UDC manages each stage of control transfer by hardware. Each stage is changed by receiving token from USB host, or CPU accesses register. Each stage in control transfer type has to process combination software. UDC detect following contents from 8-byte data in SETUP stage. (It contents is showed to following.) And, stage is managed by judging control transfer type.
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TMP92CZ26A Stage change condition of control read transfer type 1. 2. 3. Receive SETUP token from host • Start setup stage in UDC. • Receive data in request normally and judge. And assert INT_SETUP interrupt to external. • Change data stage into the UDC. Receive IN token from host • CPU receive request from request register every INT_SETUP interrupt. • Judge request and access Setup Received register for inform that recognized INT_SETUP interrupt to UDC.
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TMP92CZ26A Stage change condition of control write transfer type 1. 2. 3. Receive SETUP token from host. • Start setup stage in UDC. • Receive data in request normally and judge. And assert INT_SETUP interrupt to external. • Change data stage in UDC. Receive OUT token from host. • CPU receive request from request register every INT_SETUP interrupt. • Judge request and access Setup Received register for inform that recognized INT_SETUP interrupt to UDC.
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TMP92CZ26A Stage change condition of control write (no data stage) transfer type 1. 2. Receive SETUP token from host • Start setup stage in UDC. • Receive data in request normally and judge. And assert INT_SETUP interrupt to external. • Change data stage in UDC. Receive IN token from host • CPU receive request from request register every INT_SETUP interrupt. • Judge request and access Setup Received register for inform that recognized INT_SETUP interrupt to UDC.
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TMP92CZ26A (d) Isochronous transfer type Isochronous transfer type is guaranteed transfer by data number that is limited every each frame. However, this transfer don’t retry when error occurs. Therefore, Isochronous transfer type transfer only 2 phases (token, data) and it doesn’t use handshake phase. And data PID for data phase is DATA0 always because of this transaction doesn’t support toggle sequence. Therefore, UDC doesn’t confirm when data PID is receiving mode.
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TMP92CZ26A 5. Below is transaction when SOF token from host is received. • Change the packet A’s FIFO from X Condition to Y Condition. And clear data. • Change the packet B from Y Condition to X Condition. • Set frame number to frame register. • Assert SOF and inform that frame is incremented to external. • DATASET register clears packet A bit and it sets packet B bit arrangement loading in present frame. • Set STATUS to READY. UDC finishes normally by above transaction.
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TMP92CZ26A IDLE Receive IN token Confirm Token packet • PID • Address • Endpoint • Transfer mode • Error Error OK Confirm Status • Confirm STATUS register (status) Invalid OK Generate DATA PID • Attach DATA0 • Confirm DATASIZE register OK Receive SOF without transmitting data Clear X condition (A) Set FULL to STATUS Transmit data Error transaction Set LOST to FRAME register Not renew FRAME number Assert SOF Attach CRC IDLE ReceiveSOF • FRAME noread • BANK shift Shift FIFO BANKs every receive SOF N
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TMP92CZ26A (d-2) Isochronous receiving mode Isochronous transfer type format in receiving is below transaction format. • Token: OUT • Data: DATA0 Control flow Isochronous transfer type is frame management. And data that is written to FIFO by OUT token is received to CPU in next frame. Below are two conditions in FIFO of Isochronous receiving mode transferring X. FIFO for storing data that received from host in present frame (DATASET register bit = 0) Y.
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TMP92CZ26A In renewed frame, Packet A’s FIFO interchange packet B’s FIFO, and transaction is used same flow. If SOF token is not received by error and so on, this data is lost because of frame is not renewed. Nothing problem in receiving PID and if frame data is received with CRC error, USB sets LOST to STATUS on FRAME register, and frame number is not renewed. However, in this case, SOF is asserted and FIFO condition is renewed.
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TMP92CZ26A IDLE Receive OUT token Confirm Token packet • PID • Address • Endpoint • Transfer mode • Error Error OK Invalid Confirm Status Confirming STATUS register (status) OK Confirm DATA PID • Time out • Error OK Error, time out exept data PID Receive SOF nothing transmitting data Clear X Condition (A) Error, receiving data more than payload.
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TMP92CZ26A 3.16.7 Bus Interface and Access to FIFO (1) CPU bus interface UDC prepares two types of FIFO access, single packet and dual packet. In single packet mode, FIFO capacity that is implemented by hardware is used as big FIFO. In dual packet mode, FIFO capacity that is divided into two is used as two FIFOs. And it uses as independent FIFO. Even if UDC is transmitting and receiving to USB host, it can be used bus efficient by to possible load to FIFO.
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TMP92CZ26A (a) Single packet mode This is data sequence of single packet mode when CPU bus interface is used. Figure 3.16.15 is receiving sequence. Figure 3.16.16 is transmitting sequence. Main of this chapter is access to FIFO. Data sequence with USB host refer to chapter 5. Endpoint 0 can’t be changed mode for exclusive single packet mode. Single packet and dual packet of endpoint 1 to 3 can change by setting Epx_SINGLE register. When transferring, don’t change packet.
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TMP92CZ26A Below is transmitting sequence in single packet mode.
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TMP92CZ26A (b) Dual packet mode In dual packet mode, FIFO is divided into A and B packet, it is controlled according to priority in hardware. It can be performed at once, transmitting and receiving data to USB host and exchanges to external of UDC. When it reads out data from FIFO for receiving, confirm condition of two packets, and consider the order of priority. If it has received data to two packets, UDC outputs from first receiving data by FIFO that can be accessed are common in two packets.
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TMP92CZ26A When it writes data to FIFO in transmitting, confirm condition of two packets, and consider the order of priority. When transfer data number is set, set to which packet A and packet B, judge by PACKET_ACTIVE bit. Packet that bit is set to 0 is bit that transfer now. In transmitting and receiving, logic of PACKET_ACTIVE bit is reversed. Therefore, please caution in transmitting. Below is this sequence.
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TMP92CZ26A (c) Issuance of NULL packet If transmitting NULL packet, by input L pulse from EPx_EOPB signal, data of 0 length is set to FIFO, and it can be transferred NULL packet to IN token. But if it set NULL data to FIFO, it is valid only case of SET signal is L level condition (case of FIFO is empty). If it answer to receiving IN token by using NULL packet in a certain period, it is answered by keeping EPx_EOPB signal to L level.
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TMP92CZ26A 3.16.8 USB Device answer USB controller (UDC) sets various register and initialization in UDC in detecting of hardware reset, detecting of USB bus reset, and enumeration answer. Below is explaining about each condition. (1) Condition in detect in bus reset. When UDC detects bus reset on USB signal line, it initializes internal register, and it prepares enumeration operation from USB host.
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TMP92CZ26A ISO transfer mode Below is transfer condition of frame before one. Receiving SOF renews this. OUT (RX) IN (TX) Initial READY READY Not transfer READY FULL Finish normally DATAIN READY Detect in error RXERR TXERR Transfer mode of except ISO transfer This is result previous transfer. When transfer finish, this is renewed.
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TMP92CZ26A 3.16.9 Power Management USB controller (UDC) can be switched from optional resume condition (turn on the power supply condition) to suspend (Suspension) condition, and it can be returned from suspends condition to turn on the power supply condition. This function can be set to low electricity consumption by operating CLK supplying for UDC. (1) Switch to suspend condition USB host can be set USB device to suspend condition by keeping on IDLE state.
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TMP92CZ26A (4) Low power consumption by control of CLK input signal When UDC switches to suspend condition, it stops CLK and switches to low power consumption condition. But as system, this function enables besides low power consumption by stopping source of CLK that is supplied from external. CLK that supply to UDC can be controlled clock supply to USB by using USBINTFR1 and . If UDC switches to suspend condition, USBINTFR1 is set to “1”, and is set to “1”.
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TMP92CZ26A 3.16.
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TMP92CZ26A (2) Register beginning value Register Name Beginning Value Beginning Value OUTSIDE Reset USB_RESET bmRequestType 0x00 0x00 bRequest 0x00 0x00 wValue_L 0x00 wValue_H 0x00 wIndex_L 0x00 wIndex_H 0x00 wLength_L 0x00 wLength_H 0x00 0x00 Register Name Beginning Value Beginning Value OUTSIDE Reset USB_RESET INT control 0x00 0x00 USBBUFF_TEST 0x00 Hold 0x00 USB state 0x01 0x01 0x00 EPx_MODE 0x00 0x00 0x00 EPx_STATUS 0x1C 0x1C 0x00 EPx_SIZE_L_A 0x88 0x88 0x
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TMP92CZ26A (3) USB control flow chart (a) Transaction for standard request (Outline flowchart (Example)) USB interrupt Call USBINT0 function Judge Interrupt SETUP transaction ENDPOINT 0 transaction STATUS transaction 92CZ26A-454 STATUS NAK transaction ENDPOINT 1 transaction
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TMP92CZ26A (b) Condition change Turn on power supply Initialization transaction Normal finish/No transaction Waiting USB interrupt condition Transmit Request error/ S Receive USB token Transaction error/ Transmit STALL Request transaction condition 92CZ26A-455
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TMP92CZ26A (c) Device request and various request judgment Start Get request data Judge Request Standard request CLEAR_FEATURE SET_FEATURE GET_STATUS SET_ADDRESS SET_CONFIGURATION GET_CONFIGURATION SET_INTERFACE GET_INTERFACE SYNCH_FRAME GET_DESCRIPTOR Class request * Error for not support Vendor request * Error for not support End 92CZ26A-456 Error transaction
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TMP92CZ26A (c-1) CLEAR_FEATURE request transaction Start No Is request right？ Yes Judge Recipient Device Disable remote wakeup setting Endpoint Clear stall setting Finish transaction End 92CZ26A-457 Error transaction
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TMP92CZ26A (c-2) SET_FEATURE request transaction Start No Is request right? Yes Judge Recipient Device Enable remote wakeup setting Endpoint Set stall Finish transaction End 92CZ26A-458 Error transaction
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TMP92CZ26A (c-3) GET_STATUS request transaction Start No Is request right? Yes Judge Recipient Device Set self power supply information Interface Set 0 x 0 0 data of 2 bytes Endpoint Set stall information Finish transaction End 92CZ26A-459 Error transaction
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TMP92CZ26A (c-4) SET_CONFIGRATION request transaction Start No Is request right？ Yes No Is EP0 stall？ Yes Is assignment value valid？ No Yes No Is state valid？ Yes Set assignment configuration value Clear stall flag Finish transaction End 92CZ26A-460 Error transaction
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TMP92CZ26A (c-5) GET_CONFIGRATION request transaction Start No Is request right? Yes No Is state valid? Yes Set present configuraion value Finish transaction End 92CZ26A-461 Error transaction
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TMP92CZ26A (c-6) SET_INTERFACE request transaction Start No Is request right? Yes No Is EP0 stall? Yes Is assignment value valid? No Yes No Is state valid? Yes Set each endpoint to assignmented configuration value.
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TMP92CZ26A (c-7) SYNCH_FRAME request transaction Start No Is request right? Yes No Is EP0 stall? Yes Is assignment value valid? No Yes No Is state valid? Yes Set altrenate setting value to present transmitting data.
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TMP92CZ26A (c-8) SYNCH_FRAME request transaction Start No Is request right? Yes Error transaction Finish transaction End (c-9) SET_DESCRIPTOR request transaction Start No Is request right? Yes Finish transaction End 92CZ26A-464 Error transaction
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TMP92CZ26A (c-10) GET_DESCRIPTOR request transaction Start No Is request right? Yes No Is EP0 stall? Yes Is assignment value valid? No Yes No Is state valid? Yes Device Set device descriptor information. Config Set config descriptor information. Write information to FIFO[EP0_fifowrite ( )] End 92CZ26A-465 String Set string descriptor information.
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TMP92CZ26A (c-11) Data read transaction to FIFO by EP0 Start No Is request right? Yes Stage information = data stage Read data from FIFO STATUS_NAK interrupt enable STATUS_NAK interrupt disable Data read from FIFO Stage information = stataus stage All data number renew transfer address Finish transaction End 92CZ26A-466
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TMP92CZ26A (c-12) Data write transaction to FIFO by EP0 Start No Is request right? Yes Set transmitting size to SIZE register Stage information = data stage Write data to FIFO STATUS_NAK interrupt enable Is data number decided time of payload size? Set data size to SIZE register Yes STATUS_ NAK interrupt disable Write data to FIFO Stage information = status stage All data number renew former transfer address End 92CZ26A-467 Finish transaction No
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TMP92CZ26A (c-13) Beginning setting transaction of microcontroller Start Interrupt disable Set Stack point Set Various interrupt Clear vRAM UDC initialization[UDC_INIT] USB farm initialization[USB_INIT] Interrupt enable Main transaction[main ( )] (c-14) Begining setting transaction of UDC Start USBC reset transaction End 92CZ26A-468
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TMP92CZ26A (c-15) Beginning transaction of USB farm changing number Start Renew stage information Renew current information Renew support information Invalid EP except EP0 Various flag Intialization End (c-16) Set DEVICE_ID data to DEVICE_ID of UDC Start Set DEVICE_ID data to DEVICE_ID_RAM area.
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TMP92CZ26A (c-17) Descriptor data set transaction Start Set descriptor data to DESC_RAM area.
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TMP92CZ26A (c-19) Dummy function for not using maskable interrupts. • Transaction performs nothing, therefore outline flow is skipping. (c-20) Request judgment transaction. If transaction result is error, it puts STALL command.
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TMP92CZ26A (c-22) Perform endpoint 0 transaction in except for SETUP stage.
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TMP92CZ26A (c-24) STATUS_NAK interrupt transaction Start Data stage? No Yes Normal finish transaction Error transaction End (c-25) This transaction is no transaction by USB transaction perform in interrupts.
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TMP92CZ26A (c-26) Getting descriptor information (reration of standard request) Start Get device information on descriptor Is config within support? No Yes Get config information on descriptor Interface is within support in config present.
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TMP92CZ26A 3.16.11 Points to Note and Restrictions 1. Limitation of writing to COMMAND register in special timing When “STALL” command is issued, ENDPOINT status might be shift to “INVALID”. To avoid this problem, keep the below routine. a. BULK (IN/OUT) In case issue STALL command to endpoint in BULK transfer, be sure to issue STALL command after stop RD/WR accessing to endpoint; that is UDC returns NAK in the response of token from host. INT_EPxNAK should be used to detect NAK transmit. b.
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TMP92CZ26A 3. When generating toggle error of device controller a. UDC operation If USB host fail to receive ACK transmitted from UDC in OUT transfer, USB host transmits the same data to UDC again. When the FIFO is available to receive, UDC detects toggle error because of detecting the same data(having the same toggle as the data which is received just before) and returns ACK. UDC rejects it because the data have already received normally.
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TMP92CZ26A 3.17 SPIC (SPI Controller) SPIC is a Serial Peripheral Interface Controller that supports only master mode. It can be connected to SD card, MMC (Multi Media Card) etc. in SPI mode. The features are as follows; 1) 32 byte –FIFO (Transmit / Receive) 2) Generate CRC7 and CRC16 (Transmit / Receive data) 3) Baud Rate: 20Mbps max 4) Connect several SD cards and MMC. (Use other output port for /SPCS pin as /CS) 5) Use as general clock synchronous SIO.
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TMP92CZ26A 3.17.1 Block diagram It shows block diagram and connection to SD card in Figure 3.17.1.
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TMP92CZ26A 3.17.2 SFR SFR of SPIC are as follows.These area connected to CPU with 16 bit data bus. (1) SPIMD(SPI Mode setting register) SPIMD register is for operation mode or clock etc.
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TMP92CZ26A (c) Set the status of SPDO pin when data communication is not operating (after transmitting or during receiving). Please don't change the setting of this register when transmitting/receiving is in operation. (d) Select the edge of synchronous clock. Please change the setting when bit is “0”. And set the same value as . SPCLK pin ( = “0”) SPCLK pin (= “1”) SPDO pin MSB LSB Bit0 Bit1 Bit2 Bit3 Bit4 Bit7 Figure 3.17.
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TMP92CZ26A (h) This bit is for Software reset of transmit/receive FIFO pointer. Write SPICT to “0” at ="1", and stop transmitting. After that, by writing to “1”, the read/write pointer of transmit/receive FIFO are initialized. When writing SPICT to “0”, stops transmission after the UNIT data in transmitting is transmitted. Write to“1”, the data in the transmit FIFO becomes to invalid. The data in the transmit shift register is cleared simultaneously.
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TMP92CZ26A (2) SPICT(SPI Control Register) SPICT register is for data length or CRC etc.
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TMP92CZ26A The process that calculating CRC16 of transmits data and sending CRC next to transmit data is explained as follows. (1) Set SPICT to select CRC7 or CRC16 and to select calculating data. (2) To reset SPICR register, write “1” after write to "0". (3) Write transmit data to SPITD register, and wait for finish transmission all data. (4) Read SPICR register, and obtain the result of CRC calculation. (5) Transmit CRC which is obtained in (4) by the same way as (3).
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TMP92CZ26A (d) Select enable/disable of the pin for SD card or MMC. When the card isn’t inserted or no-power supply to DVcc, penetrated current is flowed because SPDI pin becomes floating. In addition, current is flowed to the card because SPCS , SPCLK and SPDO pin output “1”. This register can avoid these matters.
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TMP92CZ26A (k) In UNIT receive mode, receives only 1 UNIT data by writing “1”. When reading receive data register (SPIRD) with the condition “1”, receives one time additionally. In sequential mode, receiving is kept sequentially until FIFO becomes full by writing “1”. During receiving, it is possible to change enable/disable. If writing “0”during receiving, receiving is stopped after finishing receiving the UNIT data in receiving.
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TMP92CZ26A Difference points between UNIT transmission and Sequential transmission UNIT transmit mode can be selected by writing SPICT= “0”. The transmit FIFO is invalid in UNIT transmit mode. The UNIT transmit starts when writing UNIT data with the condition SPICT= “1” or writing SPICT= “1” after writing 1UNIT data in the transmit buffer.
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TMP92CZ26A Difference points between UNIT receive and Sequential receive UNIT receive is the mode that receiving only 1 UNIT data. UNIT receive mode can be selected by writing SPICT= “0”. The receive FIFO is invalid in the UNIT receive mode. By writing SPICT= “1”, receives 1UNIT data, loads received data in receive data register (SPIRD) and then stop receiving. Reading (SPIRD) register should be executed after writing SPICT= “0”.
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TMP92CZ26A Transmit/Receive When transmitting or receiving, write = “1” Writing = “1” first, and SPICT= “1” and keep waiting state for starting UNIT receiving. When writing SPICT= “1”after = “1”, receiving does not start right away. This is because the data to transmit at the same time has not been prepared. Transmit/receive start when writing the data to (SPITD) register with the condition = “1”.
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TMP92CZ26A (3) Interrupt In INTC (interrupt controller), interrupt is divided roughly into 2 kinds; transmit interrupt (INTSPITX) and receive interrupt (INTSPIRX). Besides in this SPI circuit, there are 4 kinds of interrupts; 2 transmit interrupts 2 receive interrupts. ・ Transmit interrupt TEMP (Empty interrupt of transmit FIFO) and TEND (End interrupt of transmit). As for TEMP interrupt, the timing of generation differs according to transmit mode; UNIT/sequential.
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TMP92CZ26A (3-1) SPIST (SPI Status Register) SPIST shows 4 statuses.
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TMP92CZ26A (3-2) SPIIE(SPI Interrupt Enable Register) SPIIE register is for enable 4 interrupts. SPIIE Register 7 6 5 4 SPIIE bit Symbol (82CH) Read/Write 2 1 0 RFULIE TENDIE RENDIE R/W After Reset 0 Function 15 (82DH) 3 TEMPIE 14 13 12 0 0 TEMP RFUL TEND REND interrupt interrupt interrupt interrupt 0:enable 0:enable 0:enable 0:enable 1:disable 1:disable 1:disable 1:disable 11 0 10 9 8 bit Symbol Read/Write After Reset Function Figure 3.17.
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TMP92CZ26A (4) SPICR (SPI CRC Register) CRC result of Transmit/Receive data is set to SPICR register. SPICR Register SPICR (826H) bit Symbol 7 6 5 4 3 2 1 0 CRCD7 CRCD6 CRCD5 CRCD4 CRCD3 CRCD2 CRCD1 CRCD0 0 0 0 11 10 9 8 CRCD11 CRCD10 CRCD9 CRCD8 0 0 0 0 Read/Write R After Reset 0 0 0 0 0 CRC result register [7:0] 15 14 13 12 CRCD15 CRCD14 CRCD13 CRCD12 Function bit Symbol Read/Write R After Reset 0 0 0 0 CRC result register [15:8] Function Figure 3.
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TMP92CZ26A (5) SPITD (SPI Transmit Data Register) SPITD0, SPITD1 registers are for writing transmitted data.
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TMP92CZ26A (6) SPIRD (SPI Receive Data Register) SPIRD0, SPIRD1 registers are for reading received data.
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TMP92CZ26A • Note of FIFO buffer There are following notes in this SPIC. 1) Transmit ・ Data is overwritten if write data with condition transmit FIFO buffer is FULL. Interrupt and transmission are not executed normally because write-pointer in FIFO becomes abnormal condition. Therefore, manage number of writing by using software. ・ If transmit is sequential, writing the data to transmit FIFO every 16 bytes is always needed. If writing other than 16 bytes, TEMP interrupt does not generate normally.
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TMP92CZ26A 3.18 I2S (Inter-IC Sound) The TMP92CZ26A incorporates serial output circuitry that is compliant with the I2S format. This function enables the TMP92CZ26A to be used for digital audio systems by connecting an LSI for audio output such as a DA converter. The I2S unit has the following features: Table 3.18.
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TMP92CZ26A 3.18.1 Block Diagram The I2S unit contains two channels: channel 0 and channel 1. Each channel can be controlled and made to output independently. Figure 3.18.1 shows a block diagram for I2S channel 0.
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TMP92CZ26A 3.18.2 SFRs The I2S unit is provided with the following registers. These registers are connected to the CPU via a 32-bit data bus. The transmission buffers I2S0BUF and I2S1BUF must be accessed using 4-byte load instructions.
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TMP92CZ26A I2S1 Control Register I2S1CTL (1818H) 7 6 bit Symbol TXE1 Read/Write R/W After reset 0 5 4 3 2 1 0 *CNTE1 DIR1 BIT1 DTFMT11 DTFMT10 SYSCKE1 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 Transmission Counter control Function Output format 0: MSB 0: 8 bits 00: I S 1: LSB 1:16 bits 01: Left start bit 0: Stop 1: Start Bit length Transmission 0: Clear 2 0 System clock 0: Disable 11: Reserved 1: Enable 10: Right 1: Start 15 (1819H) 14 13 12 11 10 9 8 bit
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TMP92CZ26A 3.18.3 Description of Operation (1) Settings the transfer clock generator and Word Select signal In the I2S unit, the clock frequencies for the I2SnCKO and I2SnWS signals are generated using the system clock (fSYS) as a source clock. The system clock is divided by a prescaler and a dedicated clock generator to set the transfer clock and sampling frequency. The counters are started by setting I2SnCTL to “1” and are stopped and cleared by setting to “0”.
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TMP92CZ26A Left Data Right Data I2SnWS I2SnCKO I2S format I2SnDO Stereo LSB MSB LSB MSB Valid data Monaural LSB MSB LSB Valid Data LSB MSB MSB Valid Data Left justify I2SnDO Stereo LSB MSB MSB Valid Data Monaural MSB LSB Valid Data LSB MSB MSB Valid Data Right justify I2SnDO Stereo LSB MSB LSB Valid Data Monaural LSB MSB MSB LSB Valid Data LSB Valid Data Figure 3.18.
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TMP92CZ26A (2) Setting example for the clock generator (8-bit counter/6-bit counter) The clock generator generates the reference clock for setting the data transfer speed and sampling frequency.
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TMP92CZ26A Note 1: The value to be set in I2SnC must be 16 or larger (18 or larger for I2S transfer) when the data length is 8 bits and 32 or larger (34 or larger for I2S transfer) when the data length is 16 bits. Note 2: It is recommended that the value to be set in I2SnC be an even number. Although it is possible to set an odd number, the clock duty of the WS signal does not become 50%.
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TMP92CZ26A The following shows how written data is output under various conditions.
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TMP92CZ26A 3.18.4 Detailed Description of Operation (1) Connection example Figure 3.18.5 shows an example of connections between the TMP92CZ26A and an external LSI (DA converter) using channel 0. TMP92CZ26A (Transmit) (Receive) PF2/I2S0WS WS PF0/I2SCKO CK PF1/I2SDO DATA Example: DA converter Note: After reset, PF0 to PF2 are placed in a high-impedance state. Connect each pin with a pull-up or pull-down resistor as necessary. Figure 3.18.
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TMP92CZ26A FIFO write 1 2 3 4 31 32 33 I2SnWS pin I2SnCKO pin I2SnDO pin INTI2Sn Overall Timing Diagram I2SnWS pin 400kHz I2SnCKO pin I2SnDO pin LSB MSB LSB MSB LSB Bit15 Bit14 Bit0 Bit15 Bit14 Bit0 MSB Bit15 Detailed Timing Diagram Figure 3.18.6 Timing Diagrams (I2S FMT/Stereo/16bit/MSB first) (3) Considerations for using the I2S unit 1) INTI2Sn generation timing Every 4bytes data trance from FIFO buffer to shift register per one time.
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TMP92CZ26A immediately. At the same time, the read and write pointers of the FIFO, the data in the output shift register and the clock generator are all cleared. (However, when I2SnCTL=1, the clock generator is not cleared. To clear the clock generator, I2SnCTL must be set to “0”). Therefore, if transmission is stopped and then resumed, no data will be output.
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TMP92CZ26A 3.19 LCD Controller (LCDC) The TMP92CZ26A incorporates an LCD controller (LCDC) for controlling an LCD driver LSI (LCD module). This LCDC supports display sizes from 64 × 64 to 640 × 480 dots for monochrome, grayscale, and 4096-color display and from 64 × 64 to 320 × 320 dots for color display using 65536 or more colors. The supported LCD driver (LCD module) types are STN (Super Twisted Nematic) and digital RGB input TFT (Thin Film Transistor).
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TMP92CZ26A 3.19.1 LCDC Features according to LCD Driver Type Table 3.19.1 LCDC Features according to LCD Driver Type (This table assumes the connection with a TOSHIBA-made LCD driver.
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TMP92CZ26A 3.19.
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TMP92CZ26A LCD Control 0 Register 7 6 5 4 2 1 0 LCDCTL0 bit Symbol PIPE ALL0 FRMON – 3 DLS LCP0OC START (0285H) Read/Write R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 PIP Segment FR divide Always FR signal function data setting write “0” LCP0/Line 0:Disable 0: Normal 0: Disable 1:Enable 1: Always 1: Enable selection Function output 1: At valid data only 0:Line output “0” LCP0(Note LCDC 0: Always operation 0: Stop 1: Start LLOAD 1:LCP0 widt
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TMP92CZ26A LCD LHSYNC Pulse Register LCDHSP bit Symbol (028AH) Read/Write After reset 7 6 5 4 3 2 1 0 LH7 LH6 LH5 LH4 LH3 LH2 LH1 LH0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 LH15 LH14 LH13 LH12 LH11 LH10 LH9 LH8 0 0 0 0 0 0 0 0 W Function bit Symbol (028BH) LHSYNC period (bits 7–0) Read/Write After reset W Function LHSYNC period (bits 15-8) LCD V SYNC Pulse Register LCDVSP (028CH) bit Symbol 7 6 5 4 3 2 1 0 LVP7 LVP6 LVP5 LVP4 LVP3 LVP2 LV
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TMP92CZ26A 7 LCDHSDLY bit Symbol (028FH) Read/Write 6 5 4 3 2 1 0 HSD6 HSD5 HSD4 HSD3 HSD2 HSD1 HSD0 0 0 0 0 0 0 W After reset Function 0 LHSYNC delay (bits 6-0) 7 6 5 4 3 2 1 0 LDD6 LDD5 LDD4 LDD3 LDD2 LDD1 LDD0 0 0 0 LCDLDDLY bit Symbol PDT (0290H) Read/Write R/W After reset 0 W 0 0 0 0 LLOAD delay (bits 6-0) Data output timing Function 0: Sync with LLOAD 1: 1 clock later than LLOAD 7 LCDO0DLY bit Symbol (0291H) Read/Write 6 5 4 3 2 1
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TMP92CZ26A LCDHSW bit Symbol (0294H) Read/Write After reset 7 6 5 4 3 2 1 0 HSW7 HSW6 HSW5 HSW4 HSW3 HSW2 HSW1 HSW0 0 0 0 0 0 0 0 0 3 2 1 0 LDW3 LDW2 LDW1 LDW0 0 0 0 0 W Function LCDLDW bit Symbol (0295H) Read/Write After reset LHSYNC width (bits 7-0) 7 6 5 4 LDW7 LDW6 LDW5 LDW4 W 0 0 0 Function LCDHO0W bit Symbol (0296H) Read/Write After reset 7 6 5 4 3 2 1 0 O0W7 O0W6 O0W5 O0W4 O0W3 O0W2 O0W1 O0W0 0 0 0 0 0 0 0 0 W Fu
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TMP92CZ26A LCD Main Area Start Address Register LSAML (02A0H) 7 6 5 4 3 2 1 bit Symbol LMSA7 LMSA6 LMSA5 LMSA4 LMSA3 LMSA2 LMSA1 Read/Write R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 Function LSAMM (02A1H) LCD main area start address (A7-A1) 7 6 5 4 3 2 1 0 bit Symbol LMSA15 LMSA14 LMSA13 LMSA12 LMSA11 LMSA10 LMSA9 LMSA8 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 After reset Function LSAMH (02A2H) 0 LCD main
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TMP92CZ26A LCD Sub Area HOT Point Register (X-dir) LSAHX (02A8H) 7 6 5 4 3 2 1 0 bit Symbol SAHX7 SAHX6 SAHX5 SAHX4 SAHX3 SAHX2 SAHX1 SAHX0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 0 7 6 5 Function (02A9H) LCD sub area HOT point (7-0) 1 0 bit Symbol 4 3 2 SAHX9 SAHX8 Read/Write R/W R/W After reset 0 0 LCD sub area HOT Function point (9-8) LCD Sub Area HOT Point Register (Y-dir) LSAHY (02AAH) 7 6 5 4 3 2 1 0 bit
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TMP92CZ26A 3.19.3 Description of Operation 3.19.3.1 Outline After the required settings such as the operation mode, display data memory address, color mode, and LCD size are specified, the start register is set to start the LCDC operation. The LCDC issues a bus request to the CPU. When the bus is granted, the LCDC reads data of the display size from the display RAM, stores the data in the FIFO buffer in the LCDC, and then returns the bus to the CPU.
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TMP92CZ26A 3.19.3.3 Basic Operation The following diagram shows the basic timings of the waveforms generated by the LCDC and adjustable elements. The adjustable elements for each signal include enable time, phase, and delay time. The signals used and their connections and settings vary with the LCD driver type (STN/TFT) and specifications to be used.
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TMP92CZ26A 3.19.3.4 Reference Clock LCP0 LCP0 is used as the reference clock for all the signals in the LCDC. This section explains how to set the frequency (period) of the LCP0 signal. The LCP0 clock speed (LD bus transfer speed) is determined by selecting TFT or STN and setting LCDMODE0 and LCDMODE1. The clock speed should be selected to meet the characteristics of the LCD driver to be used.
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TMP92CZ26A LCP0 Setting Range Table Conditions fSYS : 60 MHz Display size (color) : up to 320 × 320 Display size (monochrome/grayscale) : up to 640 × 480 Note: This table shows the range of LCP0 settings that can be made under the conditions shown above. If the CPU clock speed, display size, or refresh rate is changed, the LCP0 range also changes.
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TMP92CZ26A Example 1: When fSYS = 10 MHz, STN mode, LCDMODE0 = 01 Internal reference clock LCP0 = fSYS / 8 = 10 MHz / 8 = 1.25 [MHz] LCP0 period = 1 / 1.25 [MHz] = 0.8 [μS] Example 2: when fSYS = 60 MHz, TFT mode, LCDMODE0 = 11 Internal reference clock LCP0 = fSYS / 16 = 60 MHz / 16 = 3.75 [MHz] LCP0 period = 1 / 3.
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TMP92CZ26A LCDCTL0 is used to control the output timing of the LCP0 signal. When =0, the LCP0 signal is always output. When =1, the LCP0 signal is output only when valid data is output.
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TMP92CZ26A 3.19.3.5 Refresh Rate The period of the horizontal synchronization signal LHSYNC is defined as the product of the value set in LCDHSP and the LCP0 clock period.
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TMP92CZ26A • Insertion of dummy clocks Note: At least two LCP0 pulses must be inserted. Reference LHSYNC (Delay=0) LVSYNC LHSYNC (with delay) LCP0 LD23-0 Vertical Front Porch Horizontal Front Porch Horizontal back Porch Vertical back Porch The above is a conceptual diagram showing the data (LD23-0), shift clock (LCP0), horizontal synchronization signal (LHSYNC), and vertical synchronization signal (LVSYNC) on the LCD panel.
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TMP92CZ26A • Setting method The front dummy LHSYNC (vertical front porch) not accompanied by valid data in the total of LHSYNC period in the LVSYNC period is defined by the value set in LCDPRVSP. Front dummy LHSYNC (vertical front porch) = The back dummy LHSYNC (vertical back porch) is defined as follows: ( + 1) − (valid LHSYNC: common size) − (front dummy LHSYNC: ) The vertical back porch must have a minimum of one dummy clock.
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TMP92CZ26A 3.19.3.6 Signal Settings Signal Name LCP0 signal LVSYNC signal Front dummy LHSYNC (Vertical front porch) Valid LHSYNC Back dummy LHSYNC (Common size) (Vertical back porch) LHSYNC signal LGOEn signal FR signal LLOAD signal LLOAD signal LCP0 signal LD23-LD0 signal LDINV signal The above diagram shows the typical timings of the signals controlled by the LCDC. This section explains how to control each of these signals.
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TMP92CZ26A 1. LVSYNC Signal The period of the vertical synchronization signal LVSYNC indicates the time for each screen update (refresh rate). The LVSYNC period is defined as an integral multiple of the period of the horizontal synchronization signal LHSYNC. The LVSYNC period is calculated as the product of the value set in LCDVSP and the LHSYNC period. The value to be set in LCDVSP should be “common size + number of dummy clocks” or larger for TFT and STN.
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TMP92CZ26A 2. LHSYNC Signal The period of the horizontal synchronization signal LHSYNC corresponds to one line of display. The LHSYNC period is defined as an integral multiple of the reference clock signal LCP0. The LHSYNC period is defined as the product of the value set in LCDHSP and the LCP0 clock period. The value to be set in LCDHSP should be “segment size + number of dummy clocks” or larger for TFT.
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TMP92CZ26A The enable width of the LHSYNC signal is set using LCDHSW. It can be specified in a range of 1 to 512 pulses of the LCP0 clock. The enable width is represented by the following equation: Enable width = + 1 Thus, when LCDHSW is set to “0”, the enable width is set as one pulse of the LCP0 clock.
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TMP92CZ26A As shown in the diagram below, delay time of 0 to 127 pulses of the LCP0 clock can be inserted in the LHSYNC signal.
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TMP92CZ26A 3. LLOAD Signal The LLOAD signal is used to control the timing for the LCD driver to receive display data. The period of the LLOAD signal synchronizes to one line of display. It is defined as an integral multiple of the reference clock LCP0.
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TMP92CZ26A The number of pulses in the front dummy LHSYNC (vertical front porch) is specified by LCDPRVSP. This delay time can be set in a range of 0 to 127 pulses of the LCP0 clock.
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TMP92CZ26A The enable width of the LLOAD signal is specified using LCDLDW. It can be set in a range of 0 to 1024 pulses of the LCP0 clock. The actual enable width is determined depending on the LCDLDDLY setting, as shown below.
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TMP92CZ26A As shown in the diagram below, delay time of 0 to 127 pulses of the LCP0 clock can be inserted in the LLOAD signal. Delay time = Signal Name LCP0 signal LLVSYNC signal LHSYNC signal (Internal reference signal) LLOAD signal Delay control Note: The delay time for the LLOAD signal is controlled based on LCDLDDLY=1. Therefore, even if the delay time is set to”0” with LCDLDDLY=0, the LLOAD signal is output with a delay of one LCP0 clock. Be careful about this point.
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TMP92CZ26A 4. LGOE0 to LGOE2 Signals The LCDC has three signals (LGOE0 to LGOE2) that can be controlled like the LHSYNC signal. For these signals, the enable width, delay time, and phase timing can be adjusted as shown below.
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TMP92CZ26A Signal Name LCP0 signal LVSYNC signal LHSYNC signal (Internal reference signal) LGOE0 signal Delay control 7 LCDO0DLY bit Symbol (0291H) Read/Write 6 5 4 3 2 1 0 OE0D6 OE0D5 OE0D4 OE0D3 OE0D2 OE0D1 OE0D0 0 0 0 0 0 0 W After reset Function 7 LCDO1DLY bit Symbol (0292H) 0 OE0 delay (bits 6-0) 6 5 4 3 2 1 0 OE1D6 OE1D5 OE1D4 OE1D3 OE1D2 OE1D1 OE1D0 0 0 0 Read/Write W After reset 0 0 0 Function 7 LCDO2DLY bit Symbol (0293H) Read/Write After reset Func
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TMP92CZ26A LGOEn signal LGOEnP=0 (Phase control) LGOEnP=1 LCD Control 2 Register LCDCTL2 (0287H) 7 6 5 bit Symbol LGOE2P LGOE1P LGOE0P Read/Write R/W R/W R/W After reset 0 0 0 Function LGOE2 LGOE1 LGOE0 phase phase phase 0: Rising 0: Rising 0: Rising 1: Falling 1: Falling 1: Falling 4 92CZ26A-537 3 2 1 0
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TMP92CZ26A 5. LFR Signal The LFR (frame) signal is used to control the direction of bias the LCD driver applies on liquid crystal cells. With small screens in monochrome mode, the polarity of the LFR signal is normally inverted in synchronization with each screen display. With large screens or when grayscale or color mode is used, the polarity is inverted at shorter intervals to adjust the display quality.
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TMP92CZ26A When LCDCTL0=1 and LCDCTL0=1, frame output is inverted at intervals set in LCDDVM0 and the LFR signal is inverted at intervals of “LCP0 × M”. The “M” value is specified in LCDDVM0. When ="1" LFR signal synchronous with front edge of LHSYNC signal. So, prohibit to set =1, always need to set =0.
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TMP92CZ26A LCD Control 0 Register 7 6 5 4 2 1 0 LCDCTL0 bit Symbol PIPE ALL0 FRMON – DLS LCP0OC START (0285H) Read/Write R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 3 0 0 PIP Segment Frame Always LFR signal LCP0 (Note) LCDC function data divide write “0” LCP0/line 0: Always operation setting setting selection output 0:Disable 0: Normal 1:Enable 1: Always 0: Disable output “0” 1: Enable Function 0 0:Line 1:LCP0 1: At valid data only 0 0: Stop 1
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TMP92CZ26A 6. LD Bus The data to be transferred to the LCD driver is output via a dedicated bus (LD23 to LD0). The output format can be selected according to the input method of the LCD driver to be used. The LCDC reads data of the size corresponding to the specified LCD size from the display RAM and transfers it to the external LCD driver via the data bus pin dedicated to the LCD.
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TMP92CZ26A • Memory Map Image and Data Output in Each Display Mode STN monochrome (1-pixel display data = 1-bit memory data) Display Memory Address 0 Address 1 Address 2 Address 3 LSB D0 0 MSB D31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 LD Bus Output 8-bit type LD0 0 → 8 … LD1 1 → 9 … LD2 2 → 10 … LD3 3 → 11 … LD4 4 → 12 … LD5 5 → 13 … LD6 6 → 14 … LD7 7 → 15 … Note: When setting 240 segment, 256 segment size of data is required.
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TMP92CZ26A STN 16-grayscale (1-pixel display data = 4-bit memory data) Display Memory Address 0 Address 1 Address 2 Address 3 LSB D0 0 MSB D31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Address 4 Address 5 Address 6 LSB D0 Address 7 MSB D31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 LD Bus Output 8-bit type LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 3-0 → 35-32 … 7-4 → 39-36 … 11-8 → 43-40 … 15-12 → 47-44 …
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TMP92CZ26A STN 64-grayscale (1-pixel display data = 6-bit memory data) Display Memory Address 0 Address 1 Address 2 Address 3 LSB D0 0 MSB D31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Address 4 Address 5 Address 6 Address 7 LSB D0 MSB D31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Address 8 Address 9 Address 10 LSB D0 Address 11 MSB D31 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81
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TMP92CZ26A STN 256-color (1-pixel display data = 8-bit memory data (R: 3 bits, G: 3 bits, B: 2 bits)) Display Memory Address 0 Address 1 Address 2 Address 3 LSB D0 0 MSB D31 1 R0 2 3 4 5 6 G0 7 B0 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R1 Address 4 G1 B1 R2 Address 5 G2 B2 R3 Address 6 G3 B3 Address 7 LSB D0 MSB D31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 R4 G4 B4 R5 G5 B5 R6 G6 B6 R7
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TMP92CZ26A STN 4096-color (12 bpp: R: 4 bits, G: 4 bits, B: 4 bits) Display Memory Address 0 Address 1 Address 2 Address 3 LSB D0 0 MSB D31 1 R0 2 3 4 5 6 G0 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 B0 Address 4 R1 G1 Address 5 B1 R2 Address 6 G2 Address 7 LSB D0 MSB D31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 B2 R3 G3 B3 R4 G4 B4 R5 LD Bus Output 8-bit type LD0 3-0(R0) → 35-32(B2)… LD1 7-4(G0
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TMP92CZ26A TFT 256-color (1-pixel display data = 8-bit memory data (R: 3 bits, G: 3 bits, B: 2 bits) Display Memory Address 0 Address 1 Address 2 Address 3 LSB D0 0 MSB D31 1 R0 2 3 4 5 6 G0 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 B0 R1 Address 4 G1 B1 R2 Address 5 G2 B2 R3 Address 6 G3 B3 Address 7 LSB D0 MSB D31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 R4 G4 12bit (TFT) LD0 0(R0) LD1 1(R0)
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TMP92CZ26A TFT 4096-color (1-pixel display data = 12-bit memory data (R: 4 bits, G: 4 bits, B: 4 bits) Display Memory Address 0 Address 1 Address 2 Address 3 LSB D0 0 MSB D31 1 2 3 R0 4 5 6 G0 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 B0 Address 4 R1 G1 Address 5 B1 R2 Address 6 G2 Address 7 LSB D0 MSB D31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 B2 R3 G3 B3 R4 G4 B4 R5 12-bit TFT LD0 0(R0) → 12
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TMP92CZ26A TFT 65536-color (16 bpp: R: 5 bits, G: 6 bits, B: 5 bits) Display Memory Address 0 Address 1 Address 2 Address 3 LSB D0 0 MSB D31 1 2 3 4 5 6 R0 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 G0 Address 4 B0 R1 Address 5 G1 Address 6 B1 Address 7 LSB D0 MSB D31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 R2 G2 B2 R3 G3 B3 16-bit TFT LD0 0(R0) → 16(R1) … LD1 1(R0) → 17(R1) … LD2 2(R0) → 18(R1) …
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TMP92CZ26A TFT 262144-/16777216-color (24 bpp: R: 8 bits, G: 8 bits, B: 8 bits) Display Memory Address 0 Address 1 Address 2 Address 3 LSB D0 0 MSB D31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 Address 4 G0 B0 Address 5 R1 Address 6 Address 7 LSB D0 MSB D31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 G2 B2 24-bit TFT LD18 0(R0) → 24(R1) … LD19 1(R0) → 25(R1) … LD0 2(R0) → 26(R1) … LD1 3(R0
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TMP92CZ26A 7. LDIV Signal The and bits of the LCDMODE1 register are used to control the LDIV signal as well as data output. The LDIV signal indicates the inversion of all the LD bus signals. When LCDMODE1=1, all display data is forcefully inverted and the LDIV signal is also driven high. When LCDMODE1=1, the data that has just been transferred and the data to be transferred next are compared.
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TMP92CZ26A 3.19.4 Interrupt Function The LCDC has two types of interrupts. One is generated synchronous with the LLOAD signal and the other is generated synchronous with the LLOAD signal that is output immediately after the LVSYNC signal. LCDMODE1 is used to switch between these two types of interrupts.
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TMP92CZ26A 3.19.5 Special Functions 3.19.5.1 PIP (Picture in Picture) Function The TMP92CZ26A includes a PIP (Picture in Picture) function that allows a different screen to be displayed over the screen currently being displayed on the LCD. The PIP function manages the address space of display memory by dividing it into “main screen” and “sub screen”. For the main screen, the display size and start address are specified as in the case of the normal screen display.
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TMP92CZ26A The table below shows the HOT point locations that can be specified.
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TMP92CZ26A LCD Main Area Start Address Register LSAML (02A0H) 7 6 5 4 3 2 1 bit Symbol LMSA7 LMSA6 LMSA5 LMSA4 LMSA3 LMSA2 LMSA1 Read/Write R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 Function LSAMM (02A1H) LCD main area start address (A7-A0) 7 6 5 4 3 2 1 0 bit Symbol LMSA15 LMSA14 LMSA13 LMSA12 LMSA11 LMSA10 LMSA9 LMSA8 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 0 Function LSAMH (02A2H) 0 LCD main
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TMP92CZ26A LCD Sub Area HOT Point Register (X-dir) LSAHX (02A8H) 7 6 5 4 3 2 1 0 bit Symbol SAH7 SAH6 SAH5 SAH4 SAH3 SAH2 SAH1 SAH0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 0 7 6 5 Function (02A9H) LCD sub area HOT point (7-0) 1 0 bit Symbol 4 SAH9 SAH8 Read/Write R/W R/W After reset 0 0 Function 3 2 LCD sub area HOT point (9-8) LCD Sub Area HOT Point Register (Y-dir) LSAHY (02AAH) 7 6 5 4 3 2 1 0 bit Symbol SAHY7
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TMP92CZ26A LCD Sub Area Display Common Size Register LSACS (02AEH) 7 6 5 4 3 2 1 0 bit Symbol SAC7 SAC6 SAC5 SAC4 SAC3 SAC2 SAC1 SAC0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 0 2 1 Function LCD sub area common size (7-0) 7 (02AFH) 6 5 4 3 0 bit Symbol SAC8 Read/Write R/W After reset 0 Function LCD sub area common size (8) Note: The common size should be set in units of 1 line.
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TMP92CZ26A 3.19.5.2 Display Data Rotation Function When display RAM data is output to the LCD driver (LCDD), the data output direction can be automatically rotated by hardware to meet the specifications of the LCDD (or LCD module) to be used. Table 3.19.
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TMP92CZ26A the need to rewrite the display RAM data. 2. 90-Degree Rotation Function Display RAM Image (QVGA 320×240) QVGA (320×240) Portrait-type QVGA (240×320) (when this function is used) The display RAM image above shows typical data of QVGA size (320 segments × 240 commons: landscape type). If the LCDD to be used is of landscape type, the data can be written to the LCDD without any problem.
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TMP92CZ26A 3. Setting Method The bits in the LCDMODE1 register are used to set the display data rotation function.
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TMP92CZ26A 3.19.5.3 Considerations for Using the LCDC 1． If the operation mode is changed while the LCDC is operating, a maximum of one frame may not be displayed properly. Although this degree of disturbance does not normally pose any problem (e.g. no response on LCD, display not visible to human eyes), the actual operation largely depends on the conditions such as the LCD driver, LCD panel, and frame frequency to be used.
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TMP92CZ26A 3.19.6 Setting Example • STN CO M001 VDD O001 SCP LP SEG240 COM240 SEG001 O 240 O001 240CO M × 240SEG LCD (M onochrom e Panel) VSS VDD VSS T6C13B (240-colum n D river) Note: The LCD drive power for LCD display must be supplied from an external circuit. Figure 3.19.
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TMP92CZ26A • TFT JB T 6L78-AS (162-gate D riv e r) 92C Z26 VDD VD D U /D T E ST 1 T E ST 2 V SS V SS LG O E 2-0 G1 G1 160 SE G × 3(R G B )× 162C O M LC D O E3-1 G 162 SC160 SB160 SA160 SC81 SB81 SA81 SC80 SB80 SA80 SC1 SB1 SA1 CPV DO/I D O /I SC80 SB80 SA80 SC1 SB1 DC1-0 DB1-0 DA1-0 VSS U/D VDD DC1-0 DB-1-0 DA1-0 VSS D A5-2 D B5-2 D C 5-2 Control Signal D15∼D0 D O /I D I/O D A5-0 D C 5-0 Axx∼Axx C PH LO AD D B5-0 U/D VDD C ontrol S ignal D 15∼ D 0 A 0∼ A 23
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TMP92CZ26A 3.20 Touch Screen Interface (TSI) The TMP92CZ26A has an interface for 4-terminal resistor network touch-screen. This interface supports two procedures: an X/Y position measurement and touch detection. Each procedure is performed by setting the TSI control register (TSICR0 and TSICR1) and using an internal AD converter. 3.20.1 Touch-Screen Interface Module Internal/External Connection TMP92CZ26A YMY X+ Touch Screen MX X- PY PX Y+ External Capacitors Figure 3.20.
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TMP92CZ26A 3.20.
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TMP92CZ26A 3.20.3 Touch detection procedure A Touch detection procedure shows procedure until a pen is touched by the screen and it is detected. By touching, TSI generates interrupt (INT4) and this procedure will terminate. After an X/Y position measuring procedure is terminated, return to this procedure and wait for next touch. When touch is waiting, set SPY-switch to ON, and set other 3 switches (SMY, SPX and SMX) to OFF. The pull-down resistor that is connected to P96/INT4/PX pin is set to ON.
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TMP92CZ26A P96/INT4 pin Reset the counter for de-bounce time Start the counter for de-bounce time de-bounce time de-bounce time de-bounce time INT4 INT4 is generated by matching counter and specified de-bounce time. After pen is de-touched, INT4 can be issued again. INT4 isn’t generated by matching counter and specified de-bounce time because of it is an edge-type interrupt. Figure 3.20.
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TMP92CZ26A 3.20.4 X/Y position measuring procedure In the INT4 routine, execute an X/Y position measuring procedure like below. At first, set both SPX, SMX-switches to ON, and set SPY, SMY-switches to OFF. By this setting, analog-voltage which shows the X-position will be inputted to PG3/MY/AN3 pin. The X-position can be measured by converting this voltage to digital code with AD converter.
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TMP92CZ26A 3.20.5 Flow chart for TSI (1) Touch Detection Procedure (2) X/Y Position Measurement Procedure Main Routine: INT4 Routine: TSICR0←98H TSICR1←XXH (voluntary) (a) Execute Main Routine ･TSICR0←C5H ･AD conversion for AN3 ･Store the result (b) ･TSICR0←CAH ･AD conversion for AN2 ･Store the result (c) Execute an operation By using X/Y-position Yes Still touched? TSICR0 = 1? No Return to Main Routine Figure 3.20.
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TMP92CZ26A (a) Main routine (condition of waiting INT4 interrupt) (p9fc), = “1” : Set P96 to int4/PX, set P97 to PY (inte34) : Set interrupt level of INT4 (tsicr0)=98h : Pull-down resistor on, SPY on, Interrupt-set ei : Enable interrupt TMP92CZ26A Touch screen control AVCC PXEN ON SPY SPX PYEN MXEN MYEN Y+ Touch Screen (PX/P96/INT4) INT4 ON TSI7 X+ (MY/PG3) PXD (typ.
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TMP92CZ26A (b) X position measurement (Start AD conversion) (tsicr0)=c5h : Set SMX, SPX to ON. Set the input gate of P97, P96 to OFF. (admod1)=b0h : Set to AN3. (admod0)=08h : Start AD conversion. TMP92CZ26A Touch screen control AVCC PXEN ON SPX SPY Dec. PYEN MXEN (PY/P97) INT4 Touch Screen (PX/P96/INT4) X- TSI7 X+ (MY/PG3) PXD (typ.
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TMP92CZ26A (c) Y position measurement(Start AD conversion) (tsicr0)=cah : (admod1)=a0h : Set SMX, SPX to ON. Set the input gate of P97, P96 to OFF. Set to AN2. (admod0)=08h : Start AD conversion. TMP92CZ26A Touch screen control AVCC PXEN ON SPY Dec. SPX PYEN MXEN (PY/P97) Touch Screen INT4 (PX/P96/INT4) TSI7 X- X+ (MY/PG3) PXD (typ.
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TMP92CZ26A 3.20.6 1. Note De-bounce circuit The system clock of CPU is used in de-bounce circuit. Therefore, de-bounce circuit is not operated when clock is not supplied to CPU (IDLE1, STOP mode or PCM mode). And, an interrupt which through the de-bounce circuit is not generated. When started from IDLE1, STOP or PCM mode by using TSI, set the de-bounce circuit to disable before a condition become to HALT or PCM mode. (TSICR1="0") 2.
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TMP92CZ26A 3.21 Real time clock (RTC) 3.21.1 Function description for RTC 1) Clock function (hour, minute, second) 2) Calendar function (month and day, day of the week, and leap year) 3) 24 or 12-hour (AM/PM) clock function 4) +/- 30 second adjustment function (by software) 5) Alarm function (Alarm output) 6) Alarm interrupt generate 3.21.
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TMP92CZ26A 3.21.3 Control registers Table 3.21.
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TMP92CZ26A 3.21.4 Detailed explanation of control register RTC is not initialized by reset. Therefore, all registers must be initialized at the beginning of the program. (1) Second column register (for PAGE0 only) 7 SECR (1320H) Bit symbol 6 5 4 SE6 SE5 SE4 Read/Write 2 1 0 SE3 SE2 SE1 SE0 4 sec. column 2 sec. column 1 sec. column R/W After reset Function 3 Undefined "0" is read. 40 sec. column 20 sec. column 10 sec. column 8 sec.
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TMP92CZ26A (2) Minute column register (for PAGE0/1) 7 MINR (1321H) Bit symbol 6 5 4 MI6 MI5 MI4 Read/Write 2 1 0 MI3 MI2 MI1 MI0 4 min, column 2 min, column 1 min, column R/W After reset Function 3 Undefined "0" is read.
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TMP92CZ26A (3) Hour column register (for PAGE0/1) 1. In case of 24-hour clock mode (MONTHR= “1”) 7 HOURR (1322H) 6 Bit symbol 5 4 3 HO5 HO4 HO3 Read/Write 2 1 0 HO2 HO1 HO0 2 hour column 1 hour column R/W After reset Undefined Function "0" is read.
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TMP92CZ26A (4) Day of the week column register (for PAGE0/1) 7 DAYR (1323H) 6 5 4 3 Bit symbol 2 1 0 WE2 WE1 WE0 Read/Write R/W After reset Undefined Function "0" is read. W2 W1 W0 0 0 0 Sunday 0 0 1 Monday 0 1 0 Tuesday 0 1 1 Wednesday 1 0 0 Thursday 1 0 1 Friday 1 1 0 Saturday Note: Do not set the data other than showing above.
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TMP92CZ26A (6) Month column register (for PAGE0 only) 7 MONTHR (1325H) 6 5 Bit symbol 4 3 2 1 0 MO4 MO4 MO2 MO1 MO0 2 months 1 month Read/Write R/W After reset Undefined Function "0" is read.
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TMP92CZ26A (8) Year column register (for PAGE0 only) YEARR (1326H) Bit symbol 7 6 5 4 YE7 YE6 YE5 YE4 Read/Write 2 1 0 YE3 YE2 YE1 YE0 4 Years 2 Years 1 Year R/W After reset Function 3 Undefined 80 Years 40 Years 20 Years 10 Years 8 Years 1 0 0 1 1 0 0 1 99 years 0 0 0 0 0 0 0 0 00 years 0 0 0 0 0 0 0 1 01 years 0 0 0 0 0 0 1 0 02 years 0 0 0 0 0 0 1 1 03 years 0 0 0 0 0 1 0 0 04 years 0 0 0 0 0 1 0 1 05 years 0 0
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TMP92CZ26A (10) PAGE register (for PAGE0/1) 7 PAGER (1327H) 6 5 4 3 2 ENATMR 1 Bit symbol INTENA ADJUST Read/Write R/W W R/W R/W After reset 0 Undefined Undefined Undefined Read-modify Function write instruction are prohibited Note: (Note) Interrupt 1: Adjust “0” is read. 1: Enable ENAALM 0 TIMER ALARM 1: Enable 1: Enable 0: Disable 0: Disable PAGE “0” is read. PAGE selection 0: Disable Pleas keep the setting order below and don’t set same time.
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TMP92CZ26A 3.21.5 Operational description (1) Reading timer data There is the case, which reads wrong data when carry of the inside counter happens during the operation which clock data reads. Therefore please read two times with the following way for reading correct data. Start PAGER = “0” , Select PAGE0 Read the clock data (1st) Read the clock data (2nd) NO 1st data = 2nd data YES END Figure 3.21.
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TMP92CZ26A (2) Timing of INTRTC and Clock data When time is read by interrupt, read clock data within 0.5s(s) after generating interrupt. This is because count up of clock data occurs by rising edge of 1Hz pulse cycle. ALARM INTRTC 1s counter (Internal signal) 56 57 58 59 0 1 2 1s count UP (Internal signal) Figure 3.21.
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TMP92CZ26A (3) Writing timer data When there is carry on the way of write operation, expecting data can not be wrote exactly. Therefore, in order to write in data exactly please follow the below way. 1. Resetting a divider In RTC inside, there are 15-stage dividers, which generates 1Hz clock from 32,768 KHz. Carry of a timer is not done for one second when reset this divider. So write in data at this interval.
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TMP92CZ26A 2. Disabling the timer Carry of a timer is prohibited when write “0” to PAGER and can prevent malfunction by 1s Carry hold circuit. During a timer prohibited, 1s Carry hold circuit holds one sec. carry signal, which is generated from divider. After becoming timer enable state, output the carry signal to timer and revise time and continue operation. However, timer is late when timer-disabling state continues for one second or more.
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TMP92CZ26A 3.21.6 Explanation of the interrupt signal and alarm signal Can use alarm function by setting of register of PAGE1 and output either of three signals from ALARM pin as follows by write “1” to PAGER. INTRTC outputs 1shot pulse when the falling edge is detected. RTC is not initializes by RESET. Therefore, when clock or alarm function is used, clear interrupt request flag in INTC (interrupt controller). (1) In accordance of alarm register and the timer, output “0”. (2) Output clock of 1Hz.
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TMP92CZ26A (2) When output clock of 1Hz RTC outputs clock of 1Hz to ALARM pin by setting up PAGER= “0”, RESTR= “0”, = “1”. And RTC generates INTRC interrupt by falling edge of the clock. (3) When output clock of 16Hz RTC outputs clock of 16Hz to ALARM pin by setting up PAGER= “0”, RESTR= “1”, = “0”. And RTC generates INTRC interrupt by falling edge of the clock.
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TMP92CZ26A 3.22 Melody / Alarm generator (MLD) TMP92CZ26A contains melody function and alarm function, both of which are output from the MLDALM pin. Five kind of fixed cycles interrupt is generate by using 15bit counter, which is used for alarm generator. Features are as follows. 1) Melody generator The Melody function generates signals of any frequency (4Hz- 5461Hz) based on low-speed clock (32.768 KHz) and outputs the signals from the MLDALM pin.
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TMP92CZ26A 3.22.
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TMP92CZ26A 3.22.
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TMP92CZ26A 3.22.3 Operational Description 3.22.3.1 Melody generator The Melody function generates signals of any frequency (4Hz-5461Hz) based on low-speed clock (32.768KHz) and outputs the signals from the MLDALM pin. By connecting a loud speaker outside, Melody tone can easily sound. (Operation) At first, MELALMC have to be set as “1” in order to select melody waveform as output waveform from MLDALM. Then melody output frequency has to be set to 12-bit register MELFH, MELFL.
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TMP92CZ26A 3.22.3.2 Alarm generator The Alarm function generates eight kinds of alarm waveform having a modulation frequency 4096Hz determined by the low-speed clock (32.768 KHz). And this waveform is reversible by setting a value to a register. By connecting a loud speaker outside, Alarm tone can easily sound. Five kind of fixed cycles (1Hz, 2Hz, 64Hz, 512Hz, 8192Hz) interrupt be generate by using a counter which is used for alarm generator.
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TMP92CZ26A Example: Waveform of alarm pattern for each setting value: not invert) AL1 pattern (Continuous output) Modulation frequency (4096 Hz) 1 2 8 1 AL2 pattern (8 times/1 sec) 31.25 ms 1秒 1 AL3 pattern (once) 500 ms 1 2 1 AL4 pattern (Twice/1 sec) 62.5 ms 1 1 sec 2 3 1 AL5 pattern (3 times/1 sec) 62.5 ms AL6 pattern (1 times) 1 sec 1 62.5 ms AL7 pattern (Twice) 1 2 62.
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TMP92CZ26A 3.23 Analog-Digital Converter (ADC) This LSI has a 6-channel, multiplexed-input, 10-bit successive-approximation Analog-Digital converter (ADC). Figure 3.23.1 shows a block diagram of the AD converter. The 6-analog input channels (AN0-AN5) can be used as general-purpose inputs. Note1: Ensure that the AD converter has halted before executing HALT instruction to place the TMP92CZ26A in IDLE2, IDLE1, STOP or PCM mode to reduce power consumption current.
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TMP92CZ26A 3.23.1 Control register The AD converter has 6-mode control registers (ADMOD0, ADMOD1, ADMOD2, ADMOD3, ADMOD4 and ADMOD5) and 6-conversion result high/low register pairs (ADREG0H/L ∼ ADREG5H/L). The results of high-priority AD conversion are stored in the ADREGSPH/L. Figure 3.23.2 to Figure 3.23.11 show the registers available in the AD converter.
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TMP92CZ26A AD Mode Control Register 1 (Normal conversion control) ADMOD1 (12B9H) bit Symbol 7 6 5 4 3 2 1 0 DACON ADCH2 ADCH1 ADCH0 LAT ITM REPEAT SCAN 0 0 0 0 Read/Write After reset Function R/W DAC and Analog input channel select VREF application control 0 Latency 0: No Wait 1:Start after reading conversion result store Register of last channel 0 0 0 Interrupt specification when conversion channel fixed repeat mode Repeat mode specification 0: Single conversion 1: Repeat con
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TMP92CZ26A AD Mode Control Register 2 (High-priority conversion control) ADMOD2 (12BAH) 7 6 bit Symbol HEOS HBUSY Read/Write R R 0 0 After reset Function 5 4 conversion sequence or before starting 1: Complete conversion sequence 2 HADS HHTRGE 1 0 HTSEL1 HTSEL0 0 0 R/W 0 High-priority High-priority AD conversion AD conversion sequence BUSY Flag FLAG 0: During 3 0 Start High-priority AD conversion 0: Don’t Care 1: Start AD conversion 0:Stop conversion 1:During conversion High-pr
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TMP92CZ26A AD Mode Control Register 4 (AD Monitor function control) ADMOD4 (12BCH) 7 6 5 4 3 2 1 0 bit Symbol CMEN1 CMEN0 CMP1C CMP0C IRQEN1 IRQEN0 CMPINT1 CMPINT0 Read/Write R/W R/W R R After reset 0 0 0 0 Function R/W 0 0 0 0 AD Monitor AD Monitor Generation Generation AD monitor AD monitor Status of Status of function1 function0 condition of condition of function function AD monitor AD monitor 0: Disable 0: Disable AD monitor AD monitor interrupt 1 in
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TMP92CZ26A AD Conversion Result Register 0 Low ADREG0L (12A0H) bit Symbol 7 6 ADR01 ADR00 Read/Write After reset Function 5 4 3 2 R 0 0 1 0 OVR0 ADR0RF R R 0 0 Overrun flag Store Lower 2 bits of AN0 AD conversion 0:No generate 1: Generate result AD conversion result store flag 1: Stored AD Conversion Result Register 0 High bit Symbol ADREG0H (12A1H) 7 6 5 4 3 2 1 0 ADR09 ADR08 ADR07 ADR06 ADR05 ADR04 ADR03 ADR02 0 0 0 0 1 0 OVR1 ADR1RF R R Read/Write Aft
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TMP92CZ26A AD Conversion Result Register 2 Low ADREG2L (12A4H) bit Symbol 7 6 ADR21 ADR20 Read/Write After reset Function 5 4 3 2 R 0 0 1 0 OVR2 ADR2RF R R 0 0 Overrun flag AD conversion result store 0:No generate flag 1: Generate 1: Stored Store Lower 2 bits of AN2 AD conversion result AD Conversion Result Register 1 High ADREG2H (12A5H) bit Symbol 7 6 5 4 ADR29 ADR28 ADR27 ADR26 Read/Write After reset 3 2 1 0 ADR25 ADR24 ADR23 ADR22 0 0 0 0 R 0 0 0 Functio
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TMP92CZ26A AD Conversion Result Register 4 Low ADREG4L (12A8H) bit Symbol 7 6 ADR41 ADR40 Read/Write After reset Function 5 4 3 2 R 0 0 1 0 OVR4 ADR4RF R R 0 0 Overrun flag AD conversion result store 0:No generate flag 1: Generate 1: Stored Store Lower 2 bits of AN4 AD conversion result AD Conversion Result Register 4 High ADREG4H (12A9H) bit Symbol 7 6 5 4 ADR49 ADR48 ADR47 ADR46 Read/Write After reset 3 2 1 0 ADR45 ADR44 ADR43 ADR42 0 0 0 0 R 0 0 0 Functio
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TMP92CZ26A High-priority AD Conversion Result Register SP Low ADREGSPL (12B0H) bit Symbol 7 6 ADRSP1 ADRSP0 Read/Write After reset Function 5 4 3 2 R 0 0 1 0 OVSRP ADRSPRF R R 0 0 Overrun flag AD conversion result store 0:No generate flag 1: Generate 1: Stored Store Lower 2 bits of an AD conversion result High-priority AD Conversion Result Register SP High ADREGSPH (12B1H) bit Symbol 7 6 5 4 3 2 1 0 ADRSP9 ADRSP8 ADRSP7 ADRSP6 ADRSP5 ADRSP4 ADRSP3 ADRSP2 0 0 0 0
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TMP92CZ26A AD Conversion Result Compare Criterion Register 0 Low ADCM0REGL (12B4H) bit Symbol 7 6 ADR21 ADR20 Read/Write After reset Function 5 4 3 2 1 0 R/W 0 0 Store Lower 2 bits of an AD conversion result compare criterion AD Conversion Result Compare Criterion Register 0 High ADCM0REGH (12B5H) bit Symbol 7 6 5 4 ADR29 ADR28 ADR27 ADR26 Read/Write After reset 3 2 1 0 ADR25 ADR24 ADR23 ADR22 0 0 0 0 R/W 0 0 Function 0 0 Store Upper 8 bits of an AD conversion res
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TMP92CZ26A AD Conversion Clock Setting Register 7 ADCCLK (12BFH) 3 2 1 0 bit Symbol 6 5 4 − ADCLK2 ADCLK1 ADCLK0 Read/Write R/W R/W R/W R/W After reset 0 Always write “0” Function 0 0 0 Select clock for AD conversion 000 : Reserved 100 : fIO/4 101 : fIO/5 001 : fIO/1 110 : fIO/6 010 : fIO/2 011 : fIO/3 111 : fIO/7 Note1: AD conversion is executed at the clock frequency selected in the above register.
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TMP92CZ26A 3.23.2 Operation 3.23.2.1 Analog Reference Voltages The VREFH and VREFL pins provide the analog reference voltages for the ADC. 3.23.2.2 Analog Input Channel(s) selection The Analog input channels used for AD conversion are selected as follows: (1) Normal AD conversion • Analog Input Channel Fixed mode (ADMOD1 = “0”) Setting ADMOD1 selects one of the input pins AN0 to AN5 as the input channel.
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TMP92CZ26A 3.23.2.3 Starting an AD Conversion The ADC supports two types of AD conversion: normal AD conversion and high-priority AD conversion. The ADC initiates a normal AD conversion by software when the ADMOD0 is set to “1”. It initiates a high-priority AD conversion by software when the ADMOD2 is set to “1”. For a normal AD conversion, ADMOD1 select one of four conversion modes. For a high-priority AD conversion, the ADC only supports Fixed-Channel Single Conversion mode.
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TMP92CZ26A 3.23.2.4 AD Conversion Modes and AD Conversion-End Interrupts The ADC supports the following four conversion modes. For a normal AD conversion, ADMOD0<1:0> select one of the four conversion modes. For a high-priority AD conversion, the ADC only supports Channel Fixed Single Conversion mode. a. Channel Fixed Single Conversion mode b. Channel Scan Single Conversion mode c. Channel Fixed Repeat Conversion mode d.
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TMP92CZ26A If ADMOD1 is set to “1”, the ADC generates an interrupt after every four conversions. The results of conversions are sequentially stored in the ADREG0H/L to ADREG3H/L registers, in that order. The ADMOD0 is set to “1” when the ADC stores the results in the ADREG3H/L. The next conversion results are again stored in the ADREG0, and so on. The ADMOD0 is cleared to “0” by reading this bit only. d.
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TMP92CZ26A Interrupt Generation Timing and Flag Setting in Each AD Conversion Mode Conversion mode Interrupt Generation Timing EOS set timing (Note) ADMOD1 ITM REPEAT SCAN − 0 0 1 0 Channel Fixed Single Conversion Mode After a conversion After a conversion Channel Fixed Repeat Conversion Mode After every conversion After every conversion After every four conversions After every four conversions 1 Channel Scan Single Conversion Mode After a scan conversion sequence After a scan convers
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TMP92CZ26A 3.23.2.5 High-Priority Conversion Mode The ADC can perform a high-priority AD conversion while it is performing a normal AD conversion sequence. A high-priority AD conversion can be started at software by setting the ADMOD2 to “1”. It is also triggered by a hardware trigger if so enabled using ADMOD2.
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TMP92CZ26A 3.23.2.8 Storing and Reading the AD Conversion Result Conversion results are stored into AD conversion result high/low register (ADREG0H/L to ADREG5H/L). In Channel Fixed Repeat Conversion mode, conversion results are stored into the ADREG0H/L to ADREG3H/L sequentially. In other modes, the AD conversion result of channel AN0, AN1, AN2, AN3, AN4, and AN5 is stored in ADREG0H/L, ADREG1H/L, ADREG2H/L, ADREG3H/L, ADREG4H/L, and ADREG5H/L respectively. Table 3.23.
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TMP92CZ26A Table 3.23.
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TMP92CZ26A Setting example: 1. Convert the analog input voltage on the AN3 pin and write the result to memory address 2800H using the AD interrupt(INTAD) processing routine. Main routine 7 6 5 4 3 2 1 0 INTEAD ← 1 1 0 0 ← 1 1 0 0 − 0 − 1 − 1 Enable INTAD and set it to interrupt level 4. ADMOD1 − 0 ← X X 0 0 0 Interrupt routine processing example 0 0 1 Start conversion in channel fixed single conversion mode. ADMOD0 ← ADREG3 WA Set pin AN3 to be the analog input channel.
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TMP92CZ26A 3.24 Watchdog Timer (Runaway detection timer) The TMP92CZ26A contains a watchdog timer of runaway detecting. The watchdog timer (WDT) is used to return the CPU to the normal state when it detects that the CPU has started to malfunction (runaway) due to causes such as noise. When the watchdog timer detects a malfunction, it generates a non-maskable interrupt INTWD to notify the CPU of the malfunction. Connecting the watchdog timer output to the reset pin internally forces a reset.
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TMP92CZ26A 3.24.2 Operation The watchdog timer generates an INTWD interrupt when the detection time set in the WDMOD has elapsed. The watchdog timer must be cleared “0” in software before an INTWD interrupt will be generated. If the CPU malfunctions (e.g., if runaway occurs) due to causes such as noise, but does not execute the instruction used to clear the binary counter, the binary counter will overflow and an INTWD interrupt will be generated.
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TMP92CZ26A 3.24.3 Control Registers The watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR. (1) Watchdog timer mode registers (WDMOD) 1. Setting the detection time for the watchdog timer in This 2-bit register is used for setting the watchdog timer interrupt time used when detecting runaway. On a reset this register is initialized to WDMOD = 00. The detection time for WDT is 215/fIO [s]. (The number of system clocks is approximately 65, 536.) 2.
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TMP92CZ26A WDMOD (1300H) Bit symbol 7 6 5 WDTE WDTP1 WDTP0 Read/Write After reset Function 4 3 2 1 0 I2WDT RESCR − R/W 1 0 R/W 0 0 WDT control Select detecting time 1: Enable IDLE2 15 0: Stop 17 1: Operate 00: 2 /fIO 01: 2 /fIO 19 10: 2 /fIO 21 0 1: Internally connects WDT out to the reset pin 0 Always write “0” 11: 2 /fIO Watchdog timer out control 0 − 1 Connects WDT out to a reset IDLE2 control 0 Stop 1 Operation Watchdog timer detection time 00 2 /fIO (Approximat
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TMP92CZ26A 3.25 Power Management Circuit (PMC) The TMP92CZ26A incorporates a power management circuit (PMC) for managing power supply in standby state as protective measures against leak current in fine-process products. The following six power supply rails are available. : AVCC & AVSS (for ADC) ･Analog power supply : DVCC3A, 3B & DVSSCOM (for general pins) ･3V-A, 3V-B digital I/O power supply ･1.5V-A digital internal power supply : DVCC1A & DVSSCOM (for general circuits) ･1.
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TMP92CZ26A 3.25.1 SFR 7 PMCCTL (02F0H) 2 1 0 bit symbol PCM_ON 6 5 4 3 − WUTM1 WUTM0 Read/Write R/W W R/W R/W 0 0 0 0 Data − After system reset After hot reset retained Data Data retained retained Power Always Warm-up time Cut Mode write “0” 00: 29 (15.625 ms) 0: Disable Always 10: 211 (62.5 ms) 1: Enable read as “0” 11: 212 (125 ms) Function 01: 210 (31.
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TMP92CZ26A 3.25.2 Detailed Description of Operation This section explains the procedures for entering and exiting the Power Cut Mode. • Entering the Power Cut Mode When to enter the Power Cut Mode, the CPU needs to be operating in the internal RAM. Low frequency clock (XT) must be enable condition. It is also necessary to disable interrupt requests, stop DMA operations, WDT and AD converter. Next, set the output pins to function as ports through the Pn, PnCR and PnDR registers.
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TMP92CZ26A 1. Prepare to shift Power Cut Mode (1) Set the warm-up time: PMCCTL After wake-up interruption, internal wake-up timer count setting register value:, and after about 77us, external PWE terminal change from low level to high level. Additionally after more about 92us, internal reset signal will be released.
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TMP92CZ26A • Exiting the Power Cut Mode The Power Cut Mode can be exited by external or internal interruption. (It inhibits to exit the Power Cut Mode by reset when DVCC1A is cut off. Reset must be asserted after supplying power to DVCC1A and waiting for its voltage to fully stabilize.) The interrupts that can be used to exit the Power Cut Mode are RTC interrupt, INT0 to INT7 (TSI interrupt) and INTKEY interrupt. Table 3.25.
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TMP92CZ26A 3.25.3 Detailed Description of Timing 1. A maximum of 3 clocks (92 μs) are needed for entering PCM. CPU state transition Normal 2. A maximum of 2.5 clocks (77 μs) are needed from interrupt request. Power Cut Mode (PCM) 3. A minimum of 1 clock (31 μs) is needed for entering PCM again. Warm-up 3CLK Normal XT2 PMCCTL PWE pin INTRTC INT0-7, INTKEY Interrupt enabled period Internal HOT_RESET Drive register active period Port state 5. The drive register setting is 1.
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TMP92CZ26A Regulator Regulator 1.5V 3.0V SW en Delay Circuit SW en SW en 0 S 1 TMP92CZ26A AVCC DVCC-1C DVCC-1A DVCC-1B DVCC-3A,3B Power On RTC CPU ADC AVSS Other Logic High_OSC DVSS-1C RESET LOW_OSC RAM16kB PMC DVSS-COM XT1 XT2 Power management I/O signal (PWE) External interrupt INT0-7 (INT4 also supports TSI.) INTKEY Main Power Figure3.25.2 Example External Circuitry for Using the PMC Figure3.25.2 shows an example of external circuitry for using the PMC.
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TMP92CZ26A 3.25.4 Notes of Power sequence • Power ON/Power OFF Sequence (Initial Power ON/Complete Power OFF) In the power ON sequence (initial power ON), power must be supplied to internal circuits first and then to external circuits, as shown below. In the power OFF sequence (complete power OFF), power must be turned off from external circuits so that internal circuits are turned off last.
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TMP92CZ26A 3.25.
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TMP92CZ26A 3.26 Multiply and Accumulate Calculation Unit (MAC) The TMP92CZ26A includes a multiply-accumulate unit (MAC) capable of 32-bit × 32-bit + 64-bit arithmetic operations at high speed. The MAC has the following features: ・One-cycle execution for all MAC operations (excluding register access time) ・Three operation modes : 1) 64-bit + 32-bit × 32-bit 2) 64-bit − 32-bit × 32-bit 3) 32-bit × 32-bit − 64-bit ・Support for signed/unsigned operations ・Support for integer operations only 3.26.
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TMP92CZ26A 3.26.1.2 Data Registers The data registers are arranged as shown below. Data Registers Bits<63:56> Bits<55:48> Bits<47:40> Bits<39:32> Bits<31:24> Bits<23:16> Bits<15:8> Bits<7:0> (1BE3H) (1BE2H) (1BE1H) (1BE0H) (1BE7H) (1BE6H) (1BE5H) (1BE4H) (1BEBH) (1BEAH) (1BE9H) Multiplier A MACMA Register Multiplier B MACMB Register MAC MACORH Register (1BEFH) (1BEEH) (1BEDH) (1BECH) MACORL (1BE8H) Note 1: After reset, all the registers are cleared to “0”.
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TMP92CZ26A 3.26.2 Description of Operation (1) Calculation mode The MAC has the following three types of calculation mode. The calculation mode to be used is specified in MACCR. MACCR is used to select unsigned or signed mode. The operation of each calculation mode is explained below. (a) 64 + 32 × 32 mode In this mode, the contents of the MACMA register and the MACMB register are multiplied and the result is added to the contents of the MACOR register.
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TMP92CZ26A (d) Sign mode Both multiply-accumulate and multiply-subtract operations can be executed in unsigned or signed mode. In signed mode, the MACMA, MACMB, and MACOR registers become signed registers, and the most significant bit is treated as the sign bit and the data set in each register is treated as a two’s complement value. Table 3.26.1 shows the range of values that can be represented in each sign mode. Table 3.26.
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TMP92CZ26A 3.26.3 Operation Examples (1) Unsigned multiply-accumulate operation The following shows a setting example for calculating “33333333 + 11111111 × 22222222”: ld (MACCR), 0x08 ld xde, 0x00000000 ld xhl, 0x33333333 ; Unsigned multiply-accumulate mode Start calculation by write to MACMB. ld xix, 0x11111111 ld xiy, 0x22222222 ld (MACORL), xhl ; Write 33333333 to MACORL. ld (MACORH), xde ; Clear MACORH. ld (MACMA), xix ; Write 11111111 to MACMA.
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TMP92CZ26A 3.27 Debug Mode The TMP92CZ26A includes a debug support unit (DSU) for enabling on-board debugging. The DSU has 9 debug pins for interfacing with an external emulator via a DSU connector to be mounted on the target board and a DSU connecting cable. For details about debugging, please refer to the instruction manual of the emulation pod to be used. This section provides product-specific explanations related to debug mode.
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TMP92CZ26A (3) Limitations in debug mode Debug mode has the following limitations: 1) Target reset While debugging is being performed, the system reset ( RESET pin) of the target (microcontroller) must not be used to reset the controller and microcontroller. Instead, reset should be performed from the controller. (For details, please refer to the instruction manual of the emulation pod to be used.
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TMP92CZ26A 2) Pins In debug mode, a total of 9 pins (PZ0 to PZ7 in Port Z and PU7 in Port U) are used to connect the TMP92CZ26A with an emulator via a DSU probe for communicating with the controller. For this reason, these 9 pins cannot be debugged. Therefore, if the port control register of each pin is changed in debug mode, the register contents are changed but the function of each pin remains the same.
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TMP92CZ26A Port U Register PU (00A4H) PUCR (00A6H) Bit Symbol 7 6 5 4 PU7 PU6 PU5 PU4 3 2 1 0 PU3 PU2 PU1 PU0 Read/Write R/W After reset External pin data (Output latch is reset to “0”.
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TMP92CZ26A 3) Boot function In this LSI, we support boot function, however, this boot function is not available in debug mode. (It is inhibit to set DBGE =“0”, AM0=“1” and AM1=“1” at the same time.) 4) PMC function In debug mode, the PMC function for cutting off the power supply to internal circuitry and reducing standby current is not also available.
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TMP92CZ26A 5) Data bus occupancy The TMP92CZ26A includes three controllers (LCD controller, SDRAM controller and DMAC) that function as bus masters apart from the CPU. Therefore, it is necessary to estimate the bus occupancy time of each bus master and control each function accordingly to ensure proper operation of each function. (For details, please refer to the chapter on the DMA controller.
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TMP92CZ26A Setup time 1 LHSYNC LCP0 LD-bus LCD DMA operation 1 3 Setup time 2 HDMA operation 1 (Worst case) 2 Steal operation (Worst case) 1 LCD DMA operation 2 HDMA operation 2 Figure 3.27.2 Example of Data Bus Occupancy Timing in Debug Mode Figure 3.27.2 shows an example of data bus occupancy timing in debug mode.
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TMP92CZ26A 4. Electrical Characteristics (Tentative) 4.1 Maximum Ratings Symbol Contents Rating DVCC3A -0.3 to 3.9 DVCC3B DVCC1A DVCC1B Unit Power Supply Voltage V -0.3 to 3.0 DVCC1C AVCC -0.3 to 3.9 VIN Input Voltage -0.3 ∼DVCC3A/3B+0.3 (Note1) V -0.3 to AVCC + 0.
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TMP92CZ26A 4.2 DC Electrical Characteristics Symbol Parameter Min Typ. Max Unit 3.0 3.3 3.6 V Condition General I/O DVCC 3A Power Supply Voltage (DVCC=AVCC) (DVSSCOM=AVSS=0V) DVCC 1A DVCC 1B DVCC 1C X1=6 to 10MHz Internal Power A CPU CLK XT1=30 (60MHz) to 34KHz CPU CLK Internal Power B 1.4 1.5 1.6 − 0.3×DVCC3A – 0.
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TMP92CZ26A Symbol Parameter Min Typ. Max Unit Condition – DVCC3A + 0.3 – DVCC3B + 0.3 – DVCC3A + 0.3 3.0≦DVCC3A≦3.6 – DVCC3A + 0.3 3.0≦DVCC3A≦3.6 0.9×DVCC1C – DVCC1C + 0.3 1.4≦DVCC1C≦1.6 0.85× – DVCC3A + 0.3 3.0≦DVCC3A≦3.6 Input High Voltage for D0 to D7 P10 to P17 (D8 to 15), P60 to P67 P71 to P76, P90 VIH0 PC4 to PC7, PF0 to PF5 PG0 to PG5, PJ5 to PJ6 0.7 × DVCC3A 3.0≦DVCC3A≦3.
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TMP92CZ26A Symbol VOL1 Parameter Output Low Voltage1 P90 to P92, PC0 to PC3, PC7 PF0 to PF5, PK1 to PK7 PM1 to PM2, PM7 PN0 to PN7, PP1 to PP7 PV0 to PV7, PW0 to PW7, PX5, PX7 VOL2 Output Low Voltage2 Except VOL1 output pin VOH1 Output High Voltage1 P90 to P92, PC0 to PC3, PC7 PF0 to PF7, PK1 to PK7 PM1 to PM2, PM7 PN0 to PN7, PP1 to PP7 PV0 to PV7, PW0 to PW7 PX5, PX7 VOH2 VOL(T) VOH(T) ILI ILO RRST CIO VTH Output High Voltage2 Except VOL1 output pin Output Low Voltage for P96(PX), P97(PY)-pins O
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TMP92CZ26A Symbol Parameter NORMAL (note2) Min Typ. Max − 15 45 0.5 28 12 34 0.4 21 30 60 1 45 23 45 0.8 34 mA 12 45 μA 200 3200 PLL_OFF fSYS =10MHz 35 Ta ≦ 70℃ 30 Ta ≦ 50℃ 50 Ta ≦ 70℃ − IDLE2 NORMAL (note2) − − IDLE2 − IDLE1 Unit Condition DVCC3A,3B = 3.6V PLL_ON fSYS=80MHz Power Cut Mode (WITH PMC function ) DVCC3A,3B = 3.6V PLL_ON fSYS=60MHz − Ta ≦ 50℃ 35 μA 35 Ta ≦ 70℃ 30 Ta ≦ 50℃ 800 Ta ≦ 70℃ 600 Ta ≦ 50℃ 6 − DVCC1A,1B,1C = 1.6V DVCC3A,3B = 3.
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TMP92CZ26A 4.3 AC Characteristics The Following all AC regulation is the measurement result in following condition, if unless otherwise noted. AC measuring condition Clock of top column in above table shows system clock frequency, and “T” shows system clock period [ns]. • • Output level: High = 0.7×3AVCC, Low = 0.3×3AVCC • Input level: High = 0.9×3AVCC, Low = 0.1×3AVCC Note: In table, “Variable” shows the regulation at DVCC3A=3.0V~3.6V, DVCC1A=DVCC1B=DVCC1C=1.4~1.6V. 4.3.
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TMP92CZ26A Write cycle No. Parameter Symbol Variable Min 16-1 D0 ~ D15 valid → WR xx rising at 0 waits D0 ~ D15 valid 16-2 → WR xx rising at 2 waits/4 waits 17-1 WR xx low width at 0 waits 17-2 WR xx low width at 2 waits/4 waits 18 A0 ~ A23 valid → WR falling 80MHz 60MHz 1.0T − 10.0 − tDW 1.0T − 6.0 6.5 − tDW4 3.0T − 10.0 − 39.8 tDW6 5.0T − 6.0 56.5 − tWW 1.0T − 7.0 − 9.6 tWW 1.0T − 4.0 8.5 − tDW 6.6 tWW4 3.0T − 7.0 − 42.8 tWW6 5.0T − 4.0 58.5 − tAW 0.5T − 5.
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TMP92CZ26A (1) Read cycle (0 waits) tOSC X1 tCYC tCL tCH SDCLK tTK tKT WAIT A0~A23 tAD CSn tHA R/ W tAR tRK tHR RD tRRH tRR tRD D0~D15 Data input tSBA SRxxB SRWR Note1: The phase relation between X1 input signal and the other signals is undefined. Note2: The above timing chart show an example of basic bus timing. The CSn , R/ W , RD , WRxx , SRxxB , SRWR pins timing can be adjusted by memory controller timing adjust function.
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TMP92CZ26A (2) Write cycle (0 waits) tOSC X1 tCYC tCL tCH SDCLK tTK tKT WAIT A0~A23 CSn R/ W tAW tWA tWK WRxx tWW tDW D0~D15 tSWR tWD Data output tRDO RD tSDH tSBW SRxxB tSDS tSAS tSWP SRWR Note1: The phase relation between X1 input signal and the other signals is undefined. Note2: The above timing chart show an example of basic bus timing. The CSn , R/ W , RD , WRxx , SRxxB , SRWR pins timing can be adjusted by memory controller timing adjust function.
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TMP92CZ26A (3) Read cycle (1 wait) SDCLK WAIT A0~A23 tAD3 CSn R/ W RD tRR3 tRD3 D0~D15 Data input (4) Write cycle (1 wait) SDCLK WAIT A0~A23 CSn R/ W WRxx tWW3 tDW3 D0~D15 Data output tRDO RD 92CZ26A-649
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TMP92CZ26A 4.3.2 Page ROM Read Cycle (1) 3-2-2-2 mode Variable Parameter Symbol 80 MHz 60 MHz Min 1 System clock period ( = T) 2 A0, A1 tCYC → D0 ~ D15 input 12.5 266.6 12.5 tAD2 2.0T − 18 7 15.2 19.5 31.8 13 24 3 A2 ~ A23 → D0 ~ D15 input tAD3 3.0T − 18 4 RD falling → D0 ~ D15 input tRD3 2.5T − 18 16.
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TMP92CZ26A 4.3.3 SDRAM controller AC Characteristics Variable Parameter Symbol 80 MHz 60 MHz Min 1 2 Ref/Active to ref/active command period =000 Active to precharge command period =000 tRC =110 Active to read/write command delay time T 12.5 16.6 7T 87.5 116.2 2T tRAS =110 25.0 33.2 7T 12210 87.5 116.2 16.6 T 12.5 =1 2T 25.0 33.2 Precharge to active 4 command period =0 T 12.5 16.6 2T 25.0 33.
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TMP92CZ26A (1) SDRAM read timing (1Word length read mode, =1) tCK SDCLK tCH tRCD tCL tRAS tRP SDxxDQM tCMS tCMS tCMH SDCS tCMH SDRAS tRRD SDCAS SDWE tAS A0~A9 tAH Row Column tAS A10 Row A11~A15 Row tAH tAC D0~D15 tOH Data input 92CZ26A-652
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TMP92CZ26A (2) SDRAM write timing (Single write mode, =1) tCK SDCLK tCH tRCD tCMS tCL tWR SDxxDQM tCMS tRRD SDCS tCMH SDRAS tCMH SDCAS tRAS SDWE tAS A0~A9 tAH Row Column tAS A10 Row A11~A15 Row tAH tDS D0~D15 tDH Data output 92CZ26A-653 tRP
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TMP92CZ26A (3) SDRAM burst read timing (Start burst cycle) tCK SDCLK tCMS SDxxDQM tMRD tRCD SDCS tCMS tCMH SDRAS tCMS tCMH SDCAS tCMH SDWE tAH tAS A0~A9 027 tAS Row Column Row A10 A11~A15 tAH tAS 0 Row tAC D0~D15 tAC Data input tOH 92CZ26A-654 tAC Data input tOH Data input
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TMP92CZ26A (4) SDRAM burst read timing (End burst timing) tCK SDCLK tCMH tCMS tRP SDxxDQM tCMS tCMS tCMH tCMH SDCS SDRAS SDCAS SDWE A0~A9 Column tAS A10 A11~A15 Row tAC D0~D15 Data input tOH Data input tOH 92CZ26A-655
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TMP92CZ26A (5) SDRAM initializes timing tCK SDCLK tRC SDxxDQM tCMS SDCS SDRAS tCMS tCMH tCMS tCMH tCMH tCMS SDCAS tCMH SDWE A0~A9 220 tAS tAH A10 A11~A15 0 92CZ26A-656
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TMP92CZ26A (6) SDRAM refreshes timing tCK SDCLK tRC SDxxDQM tCMS tCMH SDCS SDRAS SDCAS SDWE (7) SDRAM self refresh timing tCK SDCLK tCKS tCKS SDCKE SDxxDQM tCMS tCMH SDCS SDRAS SDCAS SDWE 92CZ26A-657 tRC
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TMP92CZ26A 4.3.4 NAND Flash Controller AC Characteristics 80 MHz 60 MHz Variable No. Symbol Parameter Min Max (n=3) (n=3) (m=3) (m=3) 1 tNC Access cycle (2 + n + m ) T 100 132 2 tRP NDRE low level width (1.5+ n) T − 12 45 63 3 tREA NDRE data access time 41 60 4 tOH Read data hold time 0 0 0 5 tWP NDWE low level width (1.0 + n) T − 20 30 47 6 tDS Write data setup time (1.0 + n) T − 20 30 47 7 tDH Write data hold time (0.5 + m) T − 2 42 56 (1.
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TMP92CZ26A 4.3.5 Serial channel timing (1) SCLK input mode (I/O interface mode) Parameter Variable Symbol 80 MHz 60 MHz Unit Min Max SCLK cycle tSCY 16T 200 266 Output data → SCLK rising/ falling tOSS tSCY/2 − 4T − 30 20 36.
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TMP92CZ26A 4.3.6 Timer input pulse (TA0IN, TA2IN, TB0IN0, TB1IN0) Parameter Variable Symbol Min 80 MHz 60 MHz Unit Max Clock cycle tVCK 8T+100 200 234 Low level pulse width tVCKL 4T + 40 90 107 High level pulse width tVCKH 4T + 40 90 107 4.3.7 Interrupt Operation Parameter Variable Symbol Min 80 MHz 60 MHz Unit Max INT0~INT7 low width tINTAL 2T + 40 65 74 INT0~INT7 high width tINTAH 2T + 40 65 74 4.3.8 USB Timing (Full-speed) VCC = 3.3 ± 0.
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TMP92CZ26A 4.3.9 LCD Controller Parameter Variable Symbol Min LCP0 clock period Max 80 MHz 60 MHz (n=0) (n=0) tCW 2T(n+1) 25 33.3 LCP0 high width (Include phase inversion) tCWH T(n+1) − 5 7.5 11.6 LCP0 low width (Include phase inversion) tCWL T(n+1) − 5 7.5 11.6 Data valid → LCP0 falling (Include phase inversion) tDSU T(n+1) − 7.5 5 9.1 LCP0 falling → Data hold (Include phase inversion) tDHD T(n+1) − 7.5 5 9.
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TMP92CZ26A I2S Timing 4.3.10 Parameter Variable Symbol Min 80 MHz 60 MHz Unit Max I2SCKO clock period tCR tIC 100 100 I2SCKO high width tHB 0.5 tCR − 15 35 35 I2SCKO low width tLB 0.5 tCR − 15 35 35 I2SDO, I2SWS setup time tSD 0.5 tCR − 15 35 35 I2SDO, I2SWS hold time tHD 0.5 tCR − 8 42 42 ns tCR tLB tHB I2SCKO tHD tSD tHD I2SDO I2SWS Note: The Maximum operation frequency of I2SCKO in I2S circuit is 10MHz. Don’t set I2SCKO to value more than 10MHz.
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TMP92CZ26A 4.3.11 SPI Controller Parameter Variable Symbol Min SPCLK frequency ( = 1/S) 80MHz 60 MHz Unit Max fPP 20 20 15 SPCLK rising time tr 6 6 6 SPCLK falling time tf 6 6 6 SPCLK low width tWL 0.5S − 6 19 28 SPCLK high width tWH 0.5S − 6 19 28 Output data valid → SPCLK rising tODS 0.5S − 18 7 15 SPCLK rising/ falling → Output data hold tODH 0.5S − 10 15 23.
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TMP92CZ26A 4.4 AD Conversion Characteristics Parameter Symbol Condition Min Typ. Max Analog reference voltage (+) VREFH AVCC − 0.2 AVCC AVCC Analog reference voltage (−) VREFL DVSS DVSS DVSS + 0.2 AD converter power supply voltage AVCC DVCC3A/3B DVCC3A/3B DVCC3A/3B AD converter ground AVSS DVSS DVSS Analog input voltage AVIN VREFL Analog current for reference voltage analog Total error (Quantize error of ±0.5 LSB is included) Unit V DVSS VREFH IREFON = 1 0.
PAGE 668
TMP92CZ26A 5. Table of Special function registers (SFRs) The SFRs include the I/O ports and peripheral control registers allocated to the 8-Kbyte address space from 000000H to 001FF0H.
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TMP92CZ26A Table 5.
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TMP92CZ26A [1] Port (2/2) Address Name 0080H Address Name Address 0090H PGDR Name Address 00A0H PT 00B0H PX Name 1H P1DR 1H 1H 1H 2H 2H 2H PTCR 2H PXCR 3H 3H PJDR 3H PTFC 3H PXFC 4H P4DR 4H PKDR 4H PU 4H 5H P5DR 5H PLDR 5H 5H 6H P6DR 6H PMDR 6H PUCR 6H 7H P7DR 7H PNDR 7H PUFC 7H 8H P8DR 8H PPDR 8H PV 8H 9H P9DR 9H PRDR 9H PVFC2 9H AH PADR AH PZDR AH PVCR AH BH BH PTDR BH PVFC BH CH PCDR CH PUDR CH PW CH DH DH PVDR DH DH EH EH PWDR EH PWCR EH
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TMP92CZ26A [2] INTC Address Name 00D0H INTE12 1H INTE34 Address Name Address 00E0H INTESBIADM Name 00F0H INTE0 1H INTESPI 1H INTETC01 Address Name 0100H DMA0V 1H DMA1V /INTEDMA01 2H INTE56 2H Reserved 2H INTETC23 2H DMA2V /INTEDMA23 3H INTE7 3H INTEUSB 3H INTETC45 3H DMA3V /INTEDMA45 4H INTETA01 4H Reserved 4H INTETC67 4H DMA4V 5H INTETA23 5H INTEALM 5H SIMC 5H DMA5V 6H INTETA45 6H Reserved 6H IIMC0 6H DMA6V 7H INTETA67 7H 7H INTWDT 7H DMA7V 8H INTETB0 8H INTERTC 8H
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TMP92CZ26A [5] SDRAMC Address Name 0250H SDACR 1H SDCISR 2H SDRCR 3H SDCMM 4H SDBLS 5H 6H 7H 8H 9H AH BH CH DH EH FH [6] LCDC Address [7] PMC Name Address Name Address Name Address 0280H LCDMODE0 0290H LCDHSDLY 02A0H LSAML 1H LCDMODE1 1H LCDO0DLY 1H LSAMM 1H 2H 2H LCDO1DLY 2H LSAMH 2H 3H LCDDVM0 3H LCDO2DLY 3H 3H 4H LCDSIZE 4H LCDHSW 4H LSASL 4H 5H LCDCTL0 5H LCDLDW 5H LSASM 5H 6H LCDCTL1 6H LCDHO0W 6H LSASH 6H 7H LCDCTL2 7H LCDHO1W 7H 7H 8H LCDDVM1 8H LCDHO2SW 8H
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TMP92CZ26A [8] USBC (1/2) Address Name 0500H Descriptor to RAM 067FH (384 byte) Address Name 07B0H Address Name Address Name Address Name 0780H ENDPOINT0 0790H EP0_STATUS 07A0H 1H ENDPOINT1 1H EP1_STATUS 1H EP1_SIZE_L_B 2H ENDPOINT2 2H EP2_STATUS 2H EP2_SIZE_L_B 3H ENDPOINT3 3H EP3_STATUS 3H EP3_SIZE_L_B 4H 4H 4H 5H 5H 5H 6H 6H 6H 7H 7H 7H 8H 8H EP0_SIZE_L_A 8H 9H EP1_MODE 9H EP1_SIZE_L_A 9H EP1_SIZE_H_A AH EP2_MODE AH EP2_SIZE_L_A AH EP2_SIZE_H_A BH EP3_MODE
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TMP92CZ26A [8] USBC (2/2) Address Name 07E0H Port Status 1H FRAME_L Address Name 07F0H USBINTFR1 1H USBINTFR2 2H FRAME_H 2H USBINTFR3 3H ADDRESS 3H USBINTFR4 4H 4H USBINTMR1 5H 5H USBINTMR2 6H USBREADY 6H USBINTMR3 7H 7H USBINTMR4 8H Set Descriptor STALL 8H USBCR1 9H 9H AH AH BH BH CH CH DH DH EH EH FH FH Note: Do not access no allocated name address.
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TMP92CZ26A [9] SPIC Address Name Address Name 0820H SPIMD 0830H SPITD0 1H SPIMD 1H SPITD0 2H SPICT 2H SPITD1 3H SPICT 3H SPITD1 4H SPIST 4H SPIRD0 5H SPIST 5H SPIRD0 6H SPICR 6H SPIRD1 7H SPICR 7H SPIRD1 8H 8H 9H 9H AH AH BH BH CH SPIIE CH DH SPIIE DH EH EH FH FH [10] MMU Address Name Address Name Address Name 08A0H LOCALESX Address Name 0880H LOCALPX 0890H LOCALRX 08B0H LOCALOSX 1H LOCALPX 1H LOCALRX 1H LOCALESX 1H LOCALOSX 2H LOCALPY 2H LOCALRY 2H LOCA
PAGE 676
TMP92CZ26A [11] NAND-Flash controller Address Name 08C0H NDFMCR0 Address Name Address Name 08D0H NDRSCA0 1FF0H NDFDTR0 1H NDFMCR0 1H NDRSCA0 1H NDFDTR0 2H NDFMCR1 2H NDRSCD0 2H NDFDTR1 3H NDFMCR1 3H 3H NDFDTR1 4H NDECCRD0 4H NDRSCA1 4H 5H NDECCRD0 5H NDRSCA1 5H 6H NDECCRD1 6H NDRSCD1 6H 7H NDECCRD1 7H 7H 8H NDECCRD2 8H NDRSCA2 8H 9H NDECCRD2 9H NDRSCA2 9H AH NDECCRD3 AH NDRSCD2 AH BH NDECCRD3 BH BH CH NDECCRD4 CH NDRSCA3 CH DH NDECCRD4 DH NDRSCA3 DH EH EH ND
PAGE 677
TMP92CZ26A [12] DMAC Address Name Address Name Address Name Address Name 0900H HDMAS0 0910H HDMAS1 0920H HDMAS2 0930H HDMAS3 1H HDMAS0 1H HDMAS1 1H HDMAS2 1H HDMAS3 2H HDMAS0 2H HDMAS1 2H HDMAS2 2H HDMAS3 3H 3H 3H 3H 4H HDMAD0 4H HDMAD1 4H HDMAD2 4H HDMAD3 5H HDMAD0 5H HDMAD1 5H HDMAD2 5H HDMAD3 6H HDMAD0 6H HDMAD1 6H HDMAD2 6H HDMAD3 7H 7H 7H 7H 8H HDMACA0 8H HDMACA1 8H HDMACA2 8H HDMACA3 9H HDMACA0 9H HDMACA1 9H HDMACA2 9H HDMACA3 AH HDMACB0 AH HDMACB1 AH
PAGE 678
TMP92CZ26A [13] CGEAR, PLL Address Name 10E0H SYSCR0 [14] 8-bit timer Address Name Address 1100H TA01RUN Name 1110H TA45RUN 1H SYSCR1 1H 2H SYSCR2 2H TA0REG 1H 2H TA4REG 3H EMCCR0 3H TA1REG 3H TA5REG 4H EMCCR1 4H TA01MOD 4H TA45MOD 5H EMCCR2 5H TA1FFCR 5H TA5FFCR 6H Reserved 6H 6H 7H 7H 7H 8H PLLCR0 8H TA23RUN 8H TA67RUN 9H PLLCR1 9H 9H AH AH TA2REG AH TA6REG BH BH TA3REG BH TA7REG CH CH TA23MOD CH TA67MOD DH DH TA3FFCR DH TA7FFCR EH EH EH FH FH FH [15]
PAGE 679
TMP92CZ26A [18] 10-bit ADC Address Name [19] WDT Address Name Address 12A0H ADREG0L 12B0H ADREGSPL 1H ADREG0H 1H ADREGSPH 2H ADREG1L 2H Reserved 2H 3H ADREG1H 3H Reserved 3H 1H WDCR 4H ADREG2L 4H ADCM0REGL 4H 5H ADREG2H 5H ADCM0REGH 5H 6H ADREG3L 6H ADCM1REGL 6H 7H ADREG3H 7H ADCM1REGH 7H 8H ADREG4L 8H ADMOD0 8H 9H ADREG4H 9H ADMOD1 9H AH ADREG5L AH ADMOD2 AH BH ADREG5H BH ADMOD3 BH CH Reserved CH ADMOD4 CH DH Reserved DH ADMOD5 DH EH Reserved EH EH FH Reser
PAGE 680
TMP92CZ26A [22] I2S Address [23] MAC Name 1800H I2S0BUF Address Name Address 1810H I2S1BUF Name Address 1BE0H MACMA 1BF0H 1H 1H 1H MACMA 1H 2H 2H 2H MACMA 2H 3H 3H 3H MACMA 3H 4H 4H 4H MACMB 4H 5H 5H 5H MACMB 5H 6H 6H 6H MACMB 6H 7H 7H 7H MACMB 7H 8H I2S0CTL 8H I2S1CTL 8H MACORL 8H 9H I2S0CTL 9H I2S1CTL 9H MACORL 9H AH I2S0C AH I2S1C AH MACORL AH Name BH I2S0C BH I2S1C BH MACORL BH CH CH CH MACORH CH MACCR DH DH DH MACORH DH EH EH EH MACORH
PAGE 681
TMP92CZ26A (1) I/O ports (1/11) Symbol Name Address P1 PORT1 0004H P4 PORT4 0010H P5 PORT5 0014H P6 PORT6 0018H P7 PORT7 001CH P8 PORT8 0020H P9 PORT9 0024H PA PORTA 0028H PC PORTC 0030H PF PORTF 003CH 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 R/W Data from external port (Output latch register is cleared to “0”) P47 P46 P45 P44 P43 P42 P41 P40 R/W 0 0 0 0 0 0 0 0 P57 P56 P55 P54 P53 P52 P51 P50 R/W 0 0 0 0 0 0 0 0 P67 P66 P65 P64 P63 P62 P61 P60 R/W Dat
PAGE 682
TMP92CZ26A (1) I/O ports (2/11) Symbol Name Address PR PORTR 0064H PT PORTT 00A0H PU PORTU 00A4H 7 PT7 PV PORTV 00A8H PW PORTW 00ACH PX PORTX 00B0H PZ PORTZ 0068H 6 PT6 5 PT5 4 PT4 3 2 1 0 PR3 PR2 PR1 PR0 R/W Data from external port (Output latch register is cleared to “0”) PT3 PT2 PT1 PT0 R/W Data from external port (Output latch register is cleared to “0”) PU7 PU6 PU5 PU4 PU3 PU2 PU1 R/W Data from external port (Output latch register is cleared to “0”) PV7 PV6 PV4
PAGE 683
TMP92CZ26A (1) I/O ports (3/11) Symbol P1CR Name PORT1 control register Address 0006H (Prohibit RMW) P1FC PORT1 function register 0007H (Prohibit RMW) P4FC PORT4 function register 0013H (Prohibit RMW) 7 6 5 4 3 2 1 0 P17C P16C P15C P14C P13C P12C P11C P10C 0 0 0 0 0: Input 0 1:Output 0 0 0 W P47F P46F P45F P44F P5FC 0017H (Prohibit RMW) 0/1 0/1 0/1 P57F P56F P55F 0/1 P6CR 001AH (Prohibit RMW) 0/1 0/1 0/1 P67C P66C P65C P6FC 0 0 0/1 P7CR 001EH con
PAGE 684
TMP92CZ26A (1) I/O ports (4/11) Symbol Name Address 7 6 5 4 3 2 1 0 P87F P86F P85F P84F P83F P82F P81F P80F 0 0: Port 1: 1: 1: CSZC 0 0: Port 1: CSZB 0 0: Port 1: CS3 , 0 0: Port, W P8FC PORT8 function register 0023H (Prohibit RMW) 0 0: Port 0 0: Port CSXA CSZA 0 0: Port 1: CS1 0 0: Port 1: CS0 1: CS2 , SDCS P87F2 P86F2 P84F2 W P8FC2 PORT8 function fegister2 0021H (Prohibit RMW) 0 0: CSXB 1: ND1CE P82F2 0 0: CSZD 1: ND0CE 0 0: Port, CS3 1: CSXA 0
PAGE 685
TMP92CZ26A (1) I/O ports (5/11) Symbol PAFC Name PORTA function register Address 002BH (Prohibit RMW) 7 6 5 4 3 2 1 0 PA7F PA6F PA5F PA4F PA3F PA2F PA1F PA0F 0 0 0 0 0 0 0 0 PC1C PC0C W 0: Key-in disable PC7C PC6C PC5C 1: Key-in enable PC4C PC3C PC2C W PCCR PORTC control register 0 0032H (Prohibit RMW) 0 0: Input 0: Input port, port, 1: Output EA28 port, 1: Output KO output port (Open -drain) PC7F PC6F 0 0: Input port, EA27 1: Output port PC5F 0 0: Input port,
PAGE 686
TMP92CZ26A (1) I/O ports (6/11) Symbol Name Address 7 6 5 4 3 2 1 0 PF2F PF1F PF0F PG3F W PGFC PORTG function register 0043H 0 (Prohibit RMW) 0:Input port, AN3 1: ADTRG PJCR PORTJ control register PJ6C 004EH (Prohibit RMW) 0 0:Input PF7F PJFC PORTJ function register 004FH (Prohibit RMW) PKFC PLFC PMFC PORTL function register PORTM function register PF6F 0 1: Output PF5F PF4F 0 0 0 0 0 0 0 0 0: Port 0: Port 0: Port 0: Port 0: Port 0: Port 0: Port 0: Port 1
PAGE 687
TMP92CZ26A (1) I/O ports (7/11) Symbol PNCR Name PORTN control register Address 005EH (Prohibit RMW) 7 6 5 4 3 2 1 0 PN7C PN6C PN5C PN4C PN3C PN2C PN1C PN0C 0 0 0 0 0 0 0 0 PN3F PN2F PN1F PN0F 0 0 0 0 W 0: Input 1: Output PNFC PORTN function register 005FH (Prohibit RMW) PN7F PN6F PN5F PN4F W 0 0 0 0 0:CMOS output 1:Open-Drain output PP5C PPCR PORTP control register PP4C PP3C 0062H PP2C PP1C 0 0 PP2F PP1F W (Prohibit RMW) 0 0 0 0: Input 1: Outpu
PAGE 688
TMP92CZ26A (1) I/O ports (8/11) Symbol PUCR Name PORTU control register Address 00A6H (Prohibit RMW) 7 6 5 4 3 2 1 0 PU7C PU6C PU5C PU4C PU3C PU2C PU1C PU0C 0 0 0 0 0 0 PU7F PU6F PU5F 0 1: Output PU3F PU2F PU1F PU0F W 0 0: Input PU4F W PUFC PORTU function register 00A7H (Prohibit RMW) 0 0 0 0 0 0 0: Port 0: Port 0: Port 0: Port 0 0: Port 0 0: Port 0: Port 0: Port 1: LD23 1: LD22 1: LD21@ 1: LD20 1: LD19 1: LD18 1: LD17 1: LD16 =1 PV7C PVCR
PAGE 689
TMP92CZ26A (1) I/O ports (9/11) Symbol Name Address P1DR PORT1 drive register P2DR PORT2 drive register P3DR PORT3 drive register 0083H P4DR PORT4 drive register 0084H P5DR PORT5 drive register 0085H P6DR PORT6 drive register 0086H P7DR PORT7 drive register 0087H P8DR PORT8 drive register 0088H P9DR PORT9 drive register 0089H PADR PORTA drive register 008AH 0081H 7 6 5 P17D P16D P15D 1 P27D 0082H 1 P37D 4 3 2 1 P14D P13D P12D P11D R/W 1 1 1 1 1 1 Input/Output bu
PAGE 690
TMP92CZ26A (1) I/O ports (10/11) Symbol PGDR Name PORTG drive register Address 7 6 PJDR 4 3 2 PG3D PG2D 1 0 R/W 1 0090H 1 Input/Output buffer drive register for standby mode PJ7D PORTJ drive register 5 0093H PJ6D PJ5D PJ4D PJ3D PJ2D PJ1D PJ0D 1 1 1 1 R/W 1 1 1 1 Input/Output buffer drive register for standby mode PK7D PK6D PK5D PK4D 1 1 1 1 PORTK PKDR drive register PK3D PK2D PK1D PK0D 1 1 1 1 R/W 0094H Input/Output buffer drive register for standby m
PAGE 691
TMP92CZ26A (1) I/O ports (11/11) Symbol PWDR Name PORTW drive register Address 009EH 7 6 5 4 3 2 1 0 PW7D PW6D PW5D PW4D PW3D PW2D PW1D PW0D 1 1 1 1 R/W 1 1 1 1 Input/Output buffer drive register for standby mode PX7D drive register PX4D 1 1 R/W PORTX PXDR PX5D 009FH 1 Input/Output buffer drive register for standby mode PZ7D PZDR PORTZ drive register PZ6D PZ5D PZ4D PZ3D PZ2D PZ1D PZ0D 1 1 1 1 R/W 009AH 1 1 1 1 Input/Output buffer drive register for st
PAGE 692
TMP92CZ26A (2) Interrupt control (1/4) Symbol Name Address 7 6 5 4 3 2 − INTE0 INT0 enable 00F0H − − − − − − I0C I0M2 00D0H I2C R 0 0 INT3 & INT4 enable 00D1H I4C R 0 0 I2M2 I2M1 R/W 0 0 I4M2 I2M0 0 I1C R 0 I1M2 0 INT5 & INT6 enable 00D2H I6C R 0 I6M2 I4M0 0 I3C R 0 I3M2 0 I6M0 0 I5C R 0 I5M2 0 − INTE7 INTETA01 INTETA23 INTETA45 INTETA67 INTETB0 INT7 enable INTTA0 & INTTA1 enable INTTA2 & INTTA3 enable 00D3H 00D4H 00D5H INTTA4 & INTTA5 enable 00D6H IN
PAGE 693
TMP92CZ26A (2) Interrupt control (2/4) Symbol Name Address 7 6 5 4 3 2 − INTEUSB INTUSB enable 00E3H − − − − − Always write “0” − IUSBC R 0 − INTEALM INTERTC INTEKEY INTELCD INTEI2S01 INTENDFC INTEP0 INTEAD INTALM enable INTRTC enable INTKEY enable INTLCD enable 00E5H 00E8H 00E9H 00EAH INTI2S0 & INTI2S1 enable 00EBH INTRSC & INTRDY enable 00ECH INTP0 enable 00EEH INTAD & INTADHP enable 00EFH − − − − − − − − II2S1C R 0 IRSCC R 0 − − IADHPC R 0 − 1 0 IUSBM1 R/
PAGE 694
TMP92CZ26A (2) Interrupt control (3/4) Symbol Name 7 Address INTTC0/INTDMA0 & INTETC01 INTTC1/INTDMA1 00F1H /INTEDMA01 enable 6 0 INTTC2/INTDMA2 & INTETC23 INTTC3/INTDMA3 00F2H /INTEDMA23 enable 4 3 0 0 0 0 0 0 SIMC IIMC0 SIO interrupt mode control 00F4H 0 0 0 0 0 enable 0 INTCLR ITC6C R ITC6M2 ITC6M1 R/W 0 0 0 0 0 0 0 0 I0LE R/W 0 IR0LE W 1 0: INTRX0 edge mode 1: INTRX0 level mode − R/W 0 write “0” I5EDGE W 0 I4EDGE W 0 (Prohibit RMW) 0 ITC7M0 − W 0 Always writ
PAGE 695
TMP92CZ26A (2) Interrupt control (4/4) Symbol Name DMA0V DMA0 start vector DMA1V DMA1 start vector DMA2V DMA2 start vector DMA3V DMA3 start vector DMA4V DMA4 start vector DMA5V DMA5 start vector DMA6V DMA6 start vector DMA7V DMA7 start vector DMAB DMAR Address 7 6 0100H 0101H 0103H 0104H 0105H 0106H 0107H 0108H DMA request 0109H (Prohibit RMW) 4 DMA0V4 1 0 DMA0V3 DMA0V2 R/W 0 0 DMA0 start vector 3 0 0 DMA1V5 DMA1V4 0 0 DMA2V5 DMA2V4 2 DMA0V1 DMA0V0 0 0 DMA
PAGE 696
TMP92CZ26A (3) Memory controller (1/4) Symbol B0CSL B0CSH B1CSL B1CSH B2CSL Name BLOCK0 CS/WAIT control register low BLOCK0 CS/WAIT control register high BLOCK1 CS/WAIT control register low BLOCK1 CS/WAIT control register high BLOCK2 CS/WAIT control register low Address 0140H (Prohibit RMW) 0141H (Prohibit RMW) 0144H (Prohibit RMW) 0145H (Prohibit RMW) 0148H (Prohibit RMW) 7 6 5 B0WW3 B0WW2 B0WW1 0 0 1 4 0 B0WR0 0 1 0 0001: 0 waits 0010: 1 wait 0101: 2 waits 0110: 3 waits 01
PAGE 697
TMP92CZ26A (3) Memory controller (2/4) Symbol Name Address 7 6 5 B3WW3 B3WW2 B3WW1 0 0 1 4 Write waits B3CSL B3CSH BLOCK3 CS/WAIT control register low BLOCK3 CS/WAIT control register high 0001: 0 waits waits waits waits 1011: 8 waits 1101: 10 waits 1111: 16 waits 014CH 0101: 2 (Prohibit 0111: 4 RMW) 1001: 6 014DH (Prohibit RMW) BEXCSL 0010: 1 0110: 3 1000: 5 1010: 7 1100: 9 1110: 12 0100: 20 0001: 0 0101: 2 0111: 4 1001: 6 1011: 8 1101: 10 1111: 16 waits waits waits waits waits wait
PAGE 698
TMP92CZ26A (3) Memory controller (3/4) Symbol Name MAMR0 Memory address mask register 0 MSAR0 Memory start address register 0 MAMR1 Memory address mask register 1 MSAR1 Memory start address register 1 MAMR2 Memory address mask register 2 MSAR2 Memory start address register 2 MAMR3 Memory address mask register 3 MSAR3 Memory start address register 3 Address 0142H 0143H 0146H 0147H 014AH 014BH 014EH 014FH 7 6 5 4 3 2 1 0 M0V20 M0V19 M0V18 M0V17 M0V16 M0V15 M0V14-9 M0V
PAGE 699
TMP92CZ26A (3) Memory controller (4/4) Symbol PMEMCR CSTMGC Name Page ROM control register Adjust for Timing of control signal Address 7 6 5 0166H 4 3 2 1 0 OPGE R/W 0 ROM page access 0: Disable 1: Enable OPWR1 OPWR0 PR1 PR0 WRTMGCRR 00: 1 CLK (n-1-1-1 mode) 01: 2 CLK (n-2-2-2 mode) 10: 3 CLK (n-3-3-3 mode) 11: Reserved TACSEL1 TACSEL0 R/W 0 0 Select area to change timing 00:CS0 01:CS1 10:CS2 11:CS3 0168H TCWSEL1 TCWSEL0 Adjust for Timing of control signal 0 0 Wait number on page 0
PAGE 700
TMP92CZ26A (4) TSI Symbol TSICR0 Name TSI control register0 Address 01F0H 7 6 5 4 3 2 1 0 TSI7 INGE PTST TWIEN PYEN PXEN MYEN MXEN R/W R/W R R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0: Disable Input gate Detection 1: Enable control of condition Port 0: no 96,97 touch 0: Enable 1: touch INT4 interrupt control 0 SPY SPX SMY SMX 0 : OFF 0 : OFF 0 : OFF 0 : OFF 1 : ON 1 : ON 1 : ON 1 : ON 0: Disable 1: Enable 1: Disable DBC7 DB1024 DB256 DB64 DB8 DB4 DB2 DB1
PAGE 701
TMP92CZ26A (5) SDRAM controller Symbol Name Address 7 6 SRDS − 1 0 5 4 SMUXW1 SMUXW0 3 2 1 SPRE 0 SMAC R/W SDACR SDRAM access control register 0250H Read data shift function R/W 0 Always write “0” 0 Address multiplex type 0 0 SDRAM Read/Write commands controller 00: Type A (A9- ) 0: Disable 01: Type B (A10- ) 1: Enable 10: Type C (A11- ) 11: Reserved 0: Without auto precharge 0: Disable 1: Enable 1: With auto precharge SDCISR SDRAM Command Interval Setting Register
PAGE 702
TMP92CZ26A (6) LCD controller (1/6) Symbol Name Address 7 6 RAMTYPE1 RAMTYPE0 0 Display RAM LCD MODE0 LCD mode0 register 0 00: Internal RAM 0280H 01: External SRAM 10: SDRAM 11: Reserved LDC2 5 4 3 2 1 0 SCPW1 SCPW0 MODE3 MODE2 MODE1 MODE0 0 0 R/W 1 1 0 0 LD bus transfer speed Mode setting SCPW2= 0 0000 : Reserved 00: 2-clock 0001 : SR (mono) 01: 4-clock 0010 : SR (4Gray) 10: 8-clock 0011 : Reserved 11: 16-clock SCPW2= 1 00: 6-clock 01: 12-clock 10: 24-clock 11: 48-clock LDC1 LD
PAGE 703
TMP92CZ26A (6) LCD controller (2/6) Symbol LCDCTL1 Name LCD control1 register Address 0286H 6 5 LCP0P R/W 1 LCP0 7 LHSP R/W 0 LHSYNC LVSP R/W 1 LVSYNC LLDP R/W 0 LLOAD 4 3 2 1 0 LVSW1 R/W 0 LVSW0 R/W 0 LVSYNC phase phase phase phase enable time control 0:Rising 0:Rising 0:Rising 0:Rising 00: 1 clock of LHSYNC 1:Falling 1: Falling 1: Falling 1: Falling 01: 2 clocks of LHSYNC 10: 3 clocks of LHSYNC 11: Reserved LGOE2P LCDCTL2 LCDHSP LCD control2 register LHSYNC Pulse r
PAGE 704
TMP92CZ26A (6) LCD controller (3/6) Symbol LCDO0DLY LCDO1DLY LCDO2DLY LCDHSW Name LGOE0 Delay register LGOE1 Delay register LGOE2 Delay register LHSYNC Width Address 7 6 5 4 3 2 1 0 OE0D6 OE0D5 OE0D4 OE0D3 OE0D2 OE0D1 OE0D0 0 0 0 0 0 OE1D6 OE1D5 OE1D4 OE1D1 OE1D0 0 0 OE2D1 OE2D0 0 0 W 0291H 0 0 OE0 delay (bits 6-0) OE1D3 0292H 0 0 0 0 0 OE1 delay (bits 6-0) OE2D6 OE2D5 OE2D4 OE2D3 OE2D2 W 0293H 0 0 0 0 0 OE2 delay (bits 6-0) HSW7 HSW6 HSW5 HSW4 0
PAGE 705
TMP92CZ26A (6) LCD controller (4/6) Symbol Name LSAML Start address register LCD main-L LSAMM Start address register LCD main-M LSAMH Start address register LCD main-H LSASL Start address register LCD sub-L LSASM Start address register LCD sub -M LSASH Start address register LCD sub -H LSAHX Hot point register LCD sub -X LSAHX Hot point register LCD sub -X LSAHY Hot point register LCD sub -Y Address 02A0H 02A1H 02A2H 02A4H 02A5H 02A6H 02A8H 7 6 5 LMSA7 LMSA6 LMSA5 4 0 0 L
PAGE 706
TMP92CZ26A (7) PMC Symbol Name Address 02A0H PMCCTL PMC Control Register 2 1 0 PCM_ON 7 6 5 4 3 − WUTM1 WUTM0 R/W W R/W R/W After system reset 0 0 0 0 After Hot reset Data retained − Data retained Data retained Power Cut Mode Always write “0” 0: Disable Always read as “0” Warm-up time 00: 29 (15.625 ms) 01: 210 (31.25 ms) 1: Enable 92CZ26A-703 10: 211 (62.
PAGE 707
TMP92CZ26A (8) USB controller (1/6) Symbol Name Address Descriptor RAM 0 register 0500H Descriptor RAM1 Descriptor RAM 1 register 0501H Descriptor RAM2 Descriptor RAM 2 register Descriptor RAM3 Descriptor RAM 3 register 0503H : : : : : : Descriptor RAM381 Descriptor RAM 381 register 067DH Descriptor RAM0 Descriptor Descriptor RAM382 RAM 382 register Descriptor RAM383 Endpoint0 Endpoint1 Endpoint2 Endpoint3 Descriptor RAM 383 register Endpoint 0 register Endpoint 1 register 6 5 4
PAGE 708
TMP92CZ26A (8) USB controller (2/6) Symbol EP0_STATUS EP1_STATUS EP2_STATUS EP3_STATUS EP0_SIZE_L_A EP1_SIZE_L_A EP2_SIZE_L_A EP3_SIZE_L_A EP1_SIZE_L_B EP2_SIZE_L_B EP3_SIZE_L_B EP1_SIZE_H_A EP2_SIZE_H_A EP3_SIZE_H_A Name Endpoint 0 status register Endpoint 1 status register Endpoint 2 status register Endpoint 3 status register Endpoint 0 size register Low A Endpoint 0 size register Low A Endpoint 2 size register Low A Endpoint 3 size register Low A Endpoint 1 size register Low B Endpoint 2 si
PAGE 709
TMP92CZ26A (8) USB controller (3/6) Symbol Name Endpoint 1 size EP1_SIZE_H_B register High B Endpoint 2 size EP2_SIZE_H_B register High B Endpoint 0 size EP3_SIZE_H_B register High B bmRequestType bRequest wValue_L wValue_H wIndex_L wIndex_H wLength_L wLength_H bmRequestType register bRequest register wValue register Low wValue register High wIndex register Low Address 6 5 4 3 2 1 0 DATASIZE9 DATASIZE8 DATASIZE7 R 07B1H 0 0 0 DATASIZE9 DATASIZE8 DATASIZE7 R 07B2H 0 0 0 DATA
PAGE 710
TMP92CZ26A (8) USB controller (4/6) Symbol SetupReceived Current_Config Standard Request Name SetupReceived register Current_ Config register Address 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 07C8H W REMOTEWAKEUP 07C9H ALTERNATE[1] ALTERNATE[0] INTERFACE[1] INTERFACE[0] R 07CAH Request register 07CBH 0 0 0 0 0 0 S_INTERFACE G_INTERFACE S_CONFIG G_CONFIG G_DESCRIPT S_FEATURE C_FEATURE G_STATUS 0 0 0 0 0 0 0 0 VENDOR CLASS ExSTANDARD STA
PAGE 711
TMP92CZ26A (8) USB controller (5/6) Symbol Port Status FRAME_L FRAME_H Name Port status register Frame register Low Frame register H ADDRESS Address register USBREADY USB ready register Address 7 6 5 4 3 2 1 0 Reserved7 Reserved6 PaperError Select NotError Reserved2 Reserved1 Reserved0 W 07E0H 0 0 0 1 1 0 0 0 − T[6] T[5] T[4] T[3] T[2] T[1] T[0] 0 0 07E1H R 0 0 0 0 T[10] T[9] T[8] T[7] CREATE 0 0 0 0 0 1 0 A6 A5 A4 A2 A1 A0 0 0 A3 07E3H
PAGE 712
TMP92CZ26A (8) USB controller (6/6) Symbol Name USB interrupt USBINTMR1 mask register 1 USB interrupt USBINTMR2 mask register 2 Address 7 6 5 MSK_URST_STR MSK_URST_END 07F4H 4 MSK_SUS 3 MSK_RESUME MSK_CLKSTOP 2 1 0 MSK_CLKON R/W 1 1 1 1 1 1 EP2_MSK_FA EP2_MSK_EA EP2_MSK_FB EP2_MSK_EB 1 1 1 1 MSK_EP1N MSK_EP2N MSK_EP3N 1 1 1 0: Be not masked 1: Be masked 07F5H EP1_MSK_FA EP1_MSK_EA EP1_MSK_FB EP1_MSK_EB 1 1 1 1 R/W 0: Be not masked 1: Be masked EP3_MSK_FA EP3_
PAGE 713
TMP92CZ26A (9) Symbol SPIC (1/2) Name Address 0820H (Prohibit RMW) SPIMD SPI Mode Setting register 7 6 SWRST XEN W R/W 0 0 Software reset 0: don’t care 1: Reset LOOPBACK 5 4 3 2 SYSCK 0: disable 1: enable MSB1ST 0 1 0821H LOOPBACK Start bit for (Prohibit Test mode Transmit / RMW) CEN Receive 0:LSB 1:MSB SPCS_B 0 R/W 1 0 0 Select Baud Rate 000:Reserved 100: fSYS/8 001: fSYS/2 101: fSYS/16 010: fSYS/3 110: fSYS/64 111: fSYS/256 011: fSYS/4 DOSTAT TCPOL RCPOL R/W 0:disbale 1:e
PAGE 714
TMP92CZ26A (9) SPIC (2/2) Symbol Name Address 0826H SPICR SPI CRC register 7 6 5 4 3 2 1 0 CRCD7 CRCD6 CRCD5 CRCD4 CRCD3 CRCD2 CRCD1 CRCD0 0 0 0 0 0 0 0 0 CRCD11 CRCD10 CRCD9 CRCD8 0 0 0 0 TXD2 TXD1 TXD0 0 0 TXD9 TXD8 0 0 0 TXD3 TXD2 TXD1 TXD0 0 0 0 0 TXD11 TXD10 TXD9 TXD8 0 0 0 0 RXD3 RXD2 RXD1 RXD0 0 0 0 0 RXD11 RXD10 RXD9 RXD8 0 0 0 0 RXD3 RXD2 RXD1 RXD0 0 0 0 0 RXD11 RXD10 RXD9 RXD8 0 0 0 0 R CRC result regist
PAGE 715
TMP92CZ26A (10) MMU (1/8) Symbol LOCALPX Name LOCALX register for program Address 0880H 7 6 5 4 3 2 1 0 X7 X6 X5 X4 X3 X2 X1 X0 0 0 R/W 0 0 0 0 Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.
PAGE 716
TMP92CZ26A (10) MMU (2/8) Symbol Name LOCALLX LOCALX register for LCD 0888H LOCALLX LOCALX register for LCD 0889H Address 7 6 5 4 3 2 1 0 X7 X6 X5 X4 X3 X2 X1 X0 R/W 0 0 0 0 0 0 0 0 Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.
PAGE 717
TMP92CZ26A (10) MMU (3/8) Symbol Name LOCALRX LOCALX register for read 0890H LOCALRX LOCALX register for read 0891H Address 7 6 5 4 3 2 1 0 X7 X6 X5 X4 X3 X2 X1 X0 R/W 0 0 0 0 0 0 0 0 Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.
PAGE 718
TMP92CZ26A (10) MMU (4/8) Symbol Name LOCALWX LOCALX register for write 0898H LOCALWX LOCALX register for write 0899H Address 7 6 5 4 3 2 1 0 X7 X6 X5 X4 X3 X2 X1 X0 R/W 0 0 0 0 0 0 0 0 Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.
PAGE 719
TMP92CZ26A (10) MMU (5/8) Symbol Name LOCALESX LOCALX register for DMA source 08A0H LOCALESX LOCALX register for DMA source 08A1H Address 7 6 5 4 3 2 1 0 X7 X6 X5 X4 X3 X2 X1 X0 R/W 0 0 0 0 0 0 0 0 Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.
PAGE 720
TMP92CZ26A (10) MMU (6/8) Symbol Name LOCALEDX LOCALX register for DMA destination 08A8H LOCALEDX LOCALX register for DMA destination 08A9H Address 7 6 5 4 3 2 1 0 X7 X6 X5 X4 X3 X2 X1 X0 R/W 0 0 0 0 0 0 0 0 Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.
PAGE 721
TMP92CZ26A (10) MMU (7/8) Symbol Name LOCALOSX LOCALX register for DMA source 08B0H LOCALOSX LOCALX register for DMA source 08B1H Address 7 6 5 4 3 2 1 0 X7 X6 X5 X4 X3 X2 X1 X0 R/W 0 0 0 0 0 0 0 0 Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.
PAGE 722
TMP92CZ26A (10) MMU (8/8) Symbol Name LOCALODX LOCALX register for DMA destination 08B8H LOCALODX LOCALX register for DMA destination 08B9H Address 7 6 5 4 3 2 1 0 X7 X6 X5 X4 X3 X2 X1 X0 R/W 0 0 0 0 0 0 0 0 Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.
PAGE 723
TMP92CZ26A (11) NAND-Flash controller (1/4) Symbol Name 7 6 5 4 3 2 1 0 WE ALE CLE CE0 CE1 ECCE BUSY ECCRST 0 0 0 Address R/W WE ALE 08C0H enable control (Prohibit 0: Disable 0: “L” out RMW) 1: Enable 1: “H” out NDFMCR0 CLE 0 CE0 0 CE1 control control control 0: “L” out 0: “H” out 0: “H” out 1: “H” out 1: “L” out 1: “L” out 0 NAND Flash state 0: Disable 1: Busy 1: Enable 0: Ready 0 ECC reset control 0: − 1: Reset *Always read as “0”.
PAGE 724
TMP92CZ26A (11) NAND-Flash controller (2/4) Symbol Name Address 7 6 5 4 3 2 1 0 ECCD7 ECCD6 ECCD5 ECCD4 ECCD3 ECCD2 ECCD1 ECCD0 0 0 0 0 0 ECCD15 ECCD14 ECCD13 ECCD9 ECCD8 0 0 ECCD1 ECCD0 0 0 ECCD9 ECCD8 0 0 ECCD1 ECCD0 0 0 ECCD9 ECCD8 0 0 R 08C8H NANDF NDECCRD2 Code ECC Register2 0 0 0 NAND Flash ECC Register (7-0) ECCD12 08C9H 0 0 0 ECCD7 ECCD6 ECCD5 ECCD4 ECCD3 ECCD2 R 0 0 0 0 0 0 NAND Flash ECC Register (7-0) ECCD15 ECCD14 ECCD13 0 0 0
PAGE 725
TMP92CZ26A (11) NAND-Flash controller (3/4) Symbol Name Address 08D0H NDRSCA0 NDRSCD0 NANDF read solomon Result address Register0 NANDF read solomon Result data Register0 7 6 5 4 3 2 1 0 RS0A7 RS0A6 RS0A5 RS0A4 RS0A3 RS0A2 RS0A1 RS0A0 0 0 0 0 0 0 0 0 R NAND Flash Reed-Solomon Calculation Result Address Register (7-0) RS0A9 R 0 08D1H RS0D7 08D2H NDRSCD1 NANDF read solomon Result data Register1 RS0D6 RS0D5 RS0D4 0 0 0 0 RS1A6 RS1A5 RS1A4 0 RS0D0 0 0 0 0 RS1
PAGE 726
TMP92CZ26A (11) NAND-Flash controller (4/4) Symbol Name Address 7 6 5 4 3 2 1 0 RS3A7 RS3A6 RS3A5 RS3A4 RS3A3 RS3A2 RS3A1 RS3A0 0 0 0 0 0 0 0 0 R 08DCH NDRSCA3 NDRSCD3 NANDF read solomon Result address Register3 NANDF read solomon Result data Register3 NAND Flash Reed-Solomon Calculation Result Address Register (7-0) RS3A9 0 08DDH 0 NAND Flash ReedSolomon Calculation Result Address Register (9-8) RS2D7 RS2D6 RS2D5 RS2D4 RS2D3 RS2D2 RS2D1 RS2D0 0 0 0 0 R 08DE
PAGE 727
TMP92CZ26A (12) DMAC (1/7) Symbol Name Address 0900H 7 6 5 4 3 2 1 0 D0SA7 D0SA6 D0SA5 D0SA4 D0SA3 D0SA2 D0SA1 D0SA0 0 0 0 0 0 0 0 0 D0SA10 D0SA9 D0SA8 0 0 0 D0SA18 D0SA17 D0SA16 0 0 0 D0DA3 D0DA2 D0DA1 D0DA0 0 0 0 0 D0DA10 D0DA9 D0DA8 0 0 0 D0DA18 D0DA17 D0DA16 0 0 0 R/W Source address for DMA0 (7:0) HDMAS0 DMA source address Register0 0901H D0SA15 D0SA14 D0SA13 D0SA12 0 0 0 0 D0SA11 R/W 0 Source address for DMA0 (15:8) D0SA23 0902H
PAGE 728
TMP92CZ26A (12) DMAC (2/7) Symbol Name Address 0910H 7 6 5 4 3 2 1 0 D1SA7 D1SA6 D1SA5 D1SA4 D1SA3 D1SA2 D1SA1 D1SA0 0 0 0 0 0 0 0 0 D1SA10 D1SA9 D1SA8 0 0 0 D1SA18 D1SA17 D1SA16 0 0 0 R/W Set source address for DMA1 (7:0) HDMAS1 DMA source address Register1 0911H D1SA15 D1SA14 D1SA13 D1SA12 0 0 0 0 D1SA11 R/W 0 Set source address for DMA1 (15:8) D1SA23 0912H D1SA22 D1SA21 D1SA20 D1SA19 R/W 0 0 0 0 0 Set source address for DMA1 (23:16) D1DA7 09
PAGE 729
TMP92CZ26A (12) DMAC (3/7) Symbol Name Address 0920H 7 6 5 4 3 2 1 0 D2SA7 D2SA6 D2SA5 D2SA4 D2SA3 D2SA2 D2SA1 D2SA0 0 0 0 0 0 0 0 0 D2SA10 D2SA9 D2SA8 0 0 0 D2SA18 D2SA17 D2SA16 0 0 0 D2DA3 D2DA2 D2DA1 D2DA0 0 0 0 0 D2DA10 D2DA9 D2DA8 0 0 0 D2DA18 D2DA17 D2DA16 0 0 0 R/W Source address for DMA2 (7:0) HDMAS2 DMA source address Register2 0921H D2SA15 D2SA14 D2SA13 D2SA12 0 0 0 0 D2SA11 R/W 0 Source address for DMA2 (15:8) D2SA23 0922H
PAGE 730
TMP92CZ26A (12) DMAC (4/7) Symbol Name Address 0930H 7 6 5 4 3 2 1 0 D3SA7 D3SA6 D3SA5 D3SA4 D3SA3 D3SA2 D3SA1 D3SA0 0 0 0 0 0 0 0 0 D3SA10 D3SA9 D3SA8 0 0 0 D3SA18 D3SA17 D3SA16 0 0 0 R/W Set source address for DMA3 (7:0) HDMAS3 DMA source address Register3 0931H D3SA15 D3SA14 D3SA13 D3SA12 0 0 0 0 D3SA11 R/W 0 Set source address for DMA3 (15:8) D3SA23 0932H D3SA22 D3SA21 D3SA20 D3SA19 R/W 0 0 0 0 0 Set source address for DMA3 (23:16) D3DA7 09
PAGE 731
TMP92CZ26A (12) DMAC (5/7) Symbol Name Address 0940H 7 6 5 4 3 2 1 0 D4SA7 D4SA6 D4SA5 D4SA4 D4SA3 D4SA2 D4SA1 D4SA0 0 0 0 0 0 0 0 0 D4SA10 D4SA9 D4SA8 0 0 0 D4SA18 D4SA17 D4SA16 0 0 0 D4DA3 D4DA2 D4DA1 D4DA0 0 0 0 0 D4DA10 D4DA9 D4DA8 0 0 0 D4DA18 D4DA17 D4DA16 0 0 0 R/W Source address for DMA4 (7:0) HDMAS4 DMA source address Register4 0941H D4SA15 D4SA14 D4SA13 D4SA12 0 0 0 0 D4SA11 R/W 0 Source address for DMA4 (15:8) D4SA23 0942H
PAGE 732
TMP92CZ26A (12) DMAC (6/7) Symbol Name Address 0950H 7 6 5 4 3 2 1 0 D5SA7 D5SA6 D5SA5 D5SA4 D5SA3 D5SA2 D5SA1 D5SA0 0 0 0 0 0 0 0 0 D5SA10 D5SA9 D5SA8 0 0 0 D5SA18 D5SA17 D5SA16 0 0 0 D5DA3 D5DA2 D5DA1 D5DA0 0 0 0 0 D5DA10 D5DA9 D5DA8 0 0 0 D5DA18 D5DA17 D5DA16 0 0 0 R/W Source address for DMA5 (7:0) HDMAS5 DMA source address Register5 0951H D5SA15 D5SA14 D5SA13 D5SA12 0 0 0 0 D5SA11 R/W 0 Source address for DMA5 (15:8) D5SA23 0952H
PAGE 733
TMP92CZ26A (12) DMAC (7/7) Symbol HDMAE Name DMA enable Register Address 7 6 5 4 3 2 1 0 DMAE5 DMAE4 DMAE3 DMAE2 DMAE1 DMAE0 0 0 0 0 0 R/W 097EH 0 DMA channel operation DMATE DMATR6 DMATR5 DMATR4 0: Disable 1: Enable DMATR3 DMATR2 DMATR1 DMATR0 0 0 0 R/W HDMATR DMA timer Register 0 097FH Timer 0 0 0 0 0: Disable Maximum bus occupancy time setting The value to be set in should be obtained by “Maximum bus occupancy time / (256/fSYS)”.
PAGE 734
TMP92CZ26A (13) Clock gear, PLL Symbol SYSCR0 Name System clock control register0 Address 7 6 5 4 XTEN USBCLK1 USBCLK0 1 R/W 0 0 Low -frequency oscillator circuit (fs) 10E0H 0: Stop 1: Oscillation 3 2 1 WUEF R/W 0 Select the clock of USB(fUSB) 0 PRCK R/W 0 Warm-up timer Select Prescaler 00: Disable clock 01: Reserved 0: fSYS/2 10: X1USB 1: fSYS/8 11: fPLLUSB GEAR2 SYSCR1 System clock control register1 GEAR1 GEAR0 R/W 1 0 0 Select gear value of high frequency (fc) 000: fc
PAGE 735
TMP92CZ26A (14) 8-bit timer (1/2) Symbol TA01RUN Name TMRA01 RUN register Address 7 6 5 4 3 TA0RDE R/W 0 1100H I2TA01 0 8-bit timer register 0 1102H (Prohibit RMW) TA1REG 8-bit timer register 1 1103H (Prohibit RMW) TA01MOD TA1FFCR TA23RUN TMRA1 Flip-Flop control register TMRA23 RUN register 1104H Up counter Up counter buffer 0: Stop prescaler (UC1) (UC0) 0: Disable 1: Operate 0: Stop and clear 1: Run (Count up) − W 0 − W 0 TA01M0 0 0 Operation mode 00: 8-bit timer mode 01
PAGE 736
TMP92CZ26A (14) 8-bit timer (1/2) Symbol TA45RUN Name TMRA45 RUN register Address 7 6 5 4 3 TA4RDE R/W 0 1110H I2TA45 0 8-bit timer register 4 1112H (Prohibit RMW) TA5REG 8-bit timer register 5 1113H (Prohibit RMW) TA45MOD TA5FFCR TA67RUN TMRA5 Flip-Flop control register TMRA67 RUN register 1114H Up counter Up counter buffer 0: Stop prescaler (UC5) (UC4) 0: Disable 1: Operate 0: Stop and clear 1: Run (Count up) − W 0 − W 0 TA45M0 0 0 Operation mode 00: 8-bit timer mode 01
PAGE 737
TMP92CZ26A (15) 16-bit timer (1/2) Symbol TB0RUN Name TMRB0 RUN register Address 1180H 7 6 TB0RDE R/W 0 Double buffer 0: disable 1: enable − R/W 0 Always write “0”. − − 3 2 I2TB0 R/W 0 TB0PRUN R/W 0 TMRB0 prescaler IDLE2 0: Stop 1 0 TB0RUN R/W 0 Up counter (UC10) 0: Stop and clear 1: Run (Count up) 0 0 Always write “00”.
PAGE 738
TMP92CZ26A (15) 16-bit timer (2/2) Symbol TB1RUN Name TMRB1 RUN register Address 1190H 7 6 TB1RDE R/W 0 Double buffer 0: disable 1: enable − 3 2 I2TB1 R/W 0 TB1PRUN R/W 0 TMRB0 prescaler IDLE2 0: Stop 1 0 TB1RUN R/W 0 Up counter (UC12) 0: Stop and clear 1: Run (Count up) − 0 0 Always write “00”. TMRB1 MODE register 4 1: Operate R/W TB1MOD 5 − R/W 0 Always write “0”.
PAGE 739
TMP92CZ26A (16) UART/Serial channels Symbol Name SC0BUF Serial channel 0 buffer register SC0CR Serial channel 0 control register Address 1200H (Prohibit RMW) 1201H (Prohibit RMW) 7 6 5 RB7 TB7 RB6 TB6 RB5 TB5 4 3 2 RB4 RB3 RB2 TB4 TB3 TB2 R (Receive) /W (Transmission) Undefined RB8 EVEN PE OERR PERR FERR R R/W R (Cleared to 0 when read) Undefined 0 0 0 0 0 1: Error Received Parity Parity data bit8 addition Overrun Parity Framing 0: Odd 0: Disable 1: Even 1: Enable TB8 CTSE RXE WU SM1
PAGE 740
TMP92CZ26A (17) SBI Symbol Name Address 7 6 BC2 SBICR1 SBIDBR Serial bus interface control register 1 SBI buffer register 5 BC1 4 BC0 R/W 1240H (Prohibit RMW) 1241H (Prohibit RMW) 0 0 0 DB6 ACK − R/W R 0 1 2 SCK2 1 0 SCK1 SCK0 /SWRMON R/W 0 R/W 0 0/1 Acknowledge Always Setting for the divisor value “n” read as “1”.
PAGE 741
TMP92CZ26A (18) AD converter (1/3) Symbol ADREG0L Name AD conversion result register 0 low AD conversion ADREG0H result register 0 high Address 12A0H 12A1H 7 6 ADR01 ADR00 R 0 0 Store Lower 2 bits of AN0 AD conversion result ADR09 ADR08 ADREG1L AD conversion ADREG1H result register 1 high 0 0 ADREG2L AD conversion ADREG2H result register 2 high ADREG3L AD conversion ADREG3H result register 3 high ADREG4L AD conversion result register 4 low AD conversion ADREG4H result register 4high 1
PAGE 742
TMP92CZ26A (18) AD converter (2/3) Symbol ADREGSPL ADREGSPH ADCM0REGL Name High priority Conversion Register SP low High priority Conversion Register SP high AD Conversion Result Compare Criterion Register 0 Low AD Conversion Result ADCM0REGH Compare Criterion Register 0 High ADCM1REGL AD Conversion Result Compare Criterion Register 1 Low AD Conversion Result Compare ADCM1REGH Criterion Register 1 High ADCCLK AD Conversion Clock Setting Register Address 7 6 ADRSP1 ADRSP0 5 4 3 2 R 12B0H
PAGE 743
TMP92CZ26A (18) AD converter (3/3) Symbol Name Address 7 6 4 3 2 1 0 EOS BUSY 5 I2AD ADS HTRGE TSEL1 TSEL0 0 0 0 0 0 R 0 ADMOD0 AD mode control register 0 12B8H Normal AD conversion end flag 0:During conversion sequence or before starting 1:Complete conversion sequence R/W Normal AD conversion BUSY Flag AD conversion Start Normal when AD conversion IDLE2 mode 0: Don’t Care 1:Start 0: Stop AD conversion 1: Operate Always read as”0”.
PAGE 744
TMP92CZ26A (19) Watchdog timer Symbol Name Address 7 6 5 WDTE WDTP1 WDTP0 4 3 2 1 0 I2WDT RESCR − R/W WDMOD WDCR WDT mode register WDT control register 1300H 1301H (Prohibit RMW) 1 WDT control 1: Enable R/W 0 0 Select detecting time 15 00: 2 /fIO 17 01: 2 /fIO 19 10: 2 /fIO 21 11: 2 /fIO − W − B1H: WDT disable code 92CZ26A-741 0 IDLE2 0: Stop 1: Operate 4E: WDT clear code 0 1:Internally connects WDT out to the reset pin 0 Always write “0”.
PAGE 745
TMP92CZ26A (20) RTC (Real-Time Clock) Symbol SECR MINR HOURR Name Second register Minute register Hour register Address 7 6 5 4 SE6 SE5 SE4 “0” is read 40 sec. MI6 20 sec. MI5 10 sec. MI4 “0” is read 40 min. 20 min. HO5 10 min.
PAGE 746
TMP92CZ26A (21) Melody/alarm generator Symbol ALM Name Alarmpattern register Address 1330H 7 6 5 4 3 2 1 0 AL8 AL7 AL6 AL5 AL4 AL3 AL2 AL1 0 0 0 0 0 0 0 0 − − − MELALM 0 0 0 0 Output frequency 0: Alarm 1: Melody ML1 ML0 0 0 ML9 ML8 0 0 R/W Alarm pattern setting FC1 FC0 − ALMINV R/W MELALMC MELFL Melody/ alarm control register Melody frequency L-register 1331H 1332H 0 0 Free run counter control 00: Hold 01: Restart 10: Clear 11: Clear and start ML7 ML6
PAGE 747
TMP92CZ26A (22) I2S (1/2) Symbol Name Address 15 14 13 12 11 10 9 8 B015 B014 B013 B012 B011 B010 B009 B008 7 6 5 4 3 2 1 0 B007 B006 B005 B004 B003 B002 B001 B000 W Undefined I2S I2S0BUF Transmission Buffer Transmission buffer register (FIFO) 1800H (Prohibit RMW) Register0 31 30 29 28 27 26 25 24 B031 B030 B09 B028 B027 B026 B025 B024 23 22 21 20 19 18 17 16 B023 B022 B021 B020 B019 B018 B017 B016 W Undefined Transmission buffer regi
PAGE 748
TMP92CZ26A (22) I2S (2/2) Symbol Name Address 1808H I2S0CTL I2S Control Register0 1809H 7 6 4 3 TXE0 *CNTE0 DIR0 BIT0 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Transmit 0: Stop 1: Start I2S0C 180AH 1819H I2S1C 0 System clock 0:Disable 1:Enable TEMP0 WLVL0 EDGE0 CLKE0 R R/W R/W R/W 0 0 1 0 0 Stereo Condition of WS level /monaural transmission FIFO 0: Stereo 0:low left 0: data 1: Monaural 1:high left 1: None data Source clock 0: fSYS 1: fPLL CK06 CK05 CK04 CK03 C
PAGE 749
TMP92CZ26A (23) MAC (1/2) Symbol MACMA_LL MACMA_LH MACMA_HL MACMA_HH MACMB_LL MACMB_LH MACMB_HL MACMB_HH Name Data register Multiplier A-LL Data register Multiplier A-LH Data register Multiplier A-HL Data register Multiplier A-HH Data register Multiplier B-LL Data register Multiplier B-LH Data register Multiplier B-HL Data register Multiplier B-HH Address Multiply and Accumulate 6 5 4 3 2 1 0 MA6 MA5 MA4 MA3 MA2 MA1 MA0 MA10 MA9 MA8 MA17 MA16 MA25 MA24 MB2 MB1 MB0 MB10 MB
PAGE 750
TMP92CZ26A (23) MAC (2/2) Symbol Name Data register MACOR_HLL Multiply and Accumulate 7 6 5 4 3 2 1 0 OR39 OR38 OR37 OR36 OR35 OR34 OR33 OR32 OR41 OR40 OR49 OR48 OR57 OR56 Address R/W 1BECH Undefined -HLL Multiply and Accumulate data register [39:32] OR47 Data register MACOR_HLH Multiply and Accumulate OR46 Accumulate Multiply and Accumulate data register [47:40] OR54 Accumulate MACCR OR52 OR51 OR50 R/W Undefined Multiply and Accumulate data register [55:48] OR63
PAGE 751
TMP92CZ26A 6. Package P-FBGA228-1515-0.