Datasheet

ManualsBrandsTranscend Manualscomputers & electronicsTS16GPTM510-40V

Transcend Information Inc.

Ver 1.3

Description

DescriptionDescription

Description

With an IDE interface and strong data retention ability,

40-Pin IDE Flash Modules are ideal for use in the

harsh environments where Industrial PCs, Set-Top

Boxes, etc. are used.

Placement

PlacementPlacement

Placement

Features

FeaturesFeatures

Features

• RoHS compliant products

• Storage Capacity: 128MB ~ 16GB

• Operating Voltage: 3.3V ±5% or 5V ±10%

• Operating Temperature: 0°C ~ 70°C

• Operating Humidity (Non condensation): 0% to 95%

• Storage Humidity (Non condensation): 0% to 95%

• Endurance: 2,000,000 Program/Erase cycles

• MTBF: 1,000,000 hours

• Durability of Connector: 10,000 times

• Fully compatible with devices and OS that support the

IDE standard (pitch = 2.54mm)

• Built-in ECC function assures high reliability of data

transfer

• Supports up to Ultra DMA Mode 4

• Supports PIO Mode 6

• Support Wear-Leveling to extend product life

Dimensions

DimensionsDimensions

Dimensions

Side Millimeters Inches

61.00 ± 0.40 2.402 ± 0.016

27.10 ± 0.50 1.067 ± 0.020

7.10 ± 0.20 0.280 ± 0.008

Summary of content (35 pages)

PAGE 1
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S Description Features With an IDE interface and strong data retention ability, • RoHS compliant products 40-Pin IDE Flash Modules are ideal for use in the • Storage Capacity: 128MB ~ 16GB harsh environments where Industrial PCs, Set-Top • Operating Voltage: 3.3V ±5% or 5V ±10% Boxes, etc. are used.
PAGE 2
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S Input Power Pin Assignments Pin No. Pin Name Pin Pin Pin No. Name No. Pin Name Pin No.
PAGE 3
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S Block Diagram With 1 pcs of Flash Memory: With 2 pcs of Flash Memory: Transcend Information Inc. 3 Ver 1.
PAGE 4
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S Absolute Maximum Ratings Ratings Symbol Parameter Min Max Unit VDD-VSS DC Power Supply -0.6 +6 V Ta Operating Temperature 0 +70 °C Tst Storage Temperature -40 +85 °C Recommended Operating Conditions Symbol Parameter Min Max Units VDD Power supply 3.0 5.5 V VIN Input voltage 0 VDD+0.
PAGE 5
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S Transcend Information Inc. 5 Ver 1.
PAGE 6
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S True IDE PIO Mode Read/Write Timing Mode Mode Mode Mode Mode Mode Mode 0 1 2 3 4 5 6 1 t0 Cycle time (min) 600 383 240 180 120 100 80 t1 Address Valid to -IORD/-IOWR setup (min) 70 50 30 30 25 15 10 1 t2 -IORD/-IOWR (min) 165 125 100 80 70 65 55 t2 -IORD/-IOWR (min) Register (8 bit) 290 290 290 80 70 65 55 t2i -IORD/-IOWR recovery time (min) ---70 25 25 20 t3 -IOWR data setup (min) 60 4
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T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S True IDE PIO Mode Timing Diagram Figure 1: True IDE PIO Mode Timing Diagram Notes: (1) Device address consists of -CS0, -CS1, and A[02::00] (2) Data consists of D[15::00] (16-bit) or D[07::00] (8 bit) (3) -IOCS16 is shown for PIO modes 0, 1 and 2. For other modes, this signal is ignored. (4) The negation of IORDY by the device is used to extend the PIO cycle.
PAGE 8
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S True IDE Multiword DMA Mode Read/Write Timing Specification Mode 0 (ns) Mode 1 (ns) Mode 2 (ns) Mode 3 (ns) Mode 4 (ns) 480 150 120 100 80 215 80 70 65 55 150 60 50 50 45 5 5 5 5 5 -IORD/-IOWR data setup (min) 100 30 20 15 10 -IOWR data hold (min) 20 15 10 5 5 DMACK to –IORD/-IOWR setup (min) 0 0 0 0 0 -IORD / -IOWR to -DMACK hold (min) 20 5
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T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S True IDE Multiword DMA Mode Read/Write Timing Diagram Figure 2: True IDE Multiword DMA Mode Read/Write Timing Diagram Notes: (1) If the Card cannot sustain continuous, minimum cycle time DMA transfers, it may negate DMARQ within the time specified from the start of a DMA transfer cycle to suspend the DMA transfers in progress and reassert the signal at a later time to continue the DMA
PAGE 10
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S Ultra DMA Mode Read/Write Timing Specification Ultra DMA is an optional data transfer protocol used with the READ DMA, and WRITE DMA, commands. When this protocol is enabled, the Ultra DMA protocol shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only.
PAGE 11
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S same agent (either host or device) that drives the data onto the bus. Ownership of D[15:00] and this data strobe signal are given either to the device during an Ultra DMA data-in burst or to the host for an Ultra DMA data-out burst.
PAGE 12
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S Ultra DMA Data Burst Timing Requirements Name t2CYCTYP tCYC t2CYC tDS tDH tDVS tDVH tCS tCH tCVS tCVH tZFS tDZFS tFS tLI tMLI tUI tAZ tZAH tZAD tENV tRFS tRP tIORDYZ tZIORDY tACK tSS UDMA Mode 0 UDMA Mode 1 UDMA Mode 2 Min 240 112 230 15.0 5.0 70.0 6.2 15.0 5.0 70.0 6.2 0 70.0 0 20 0 Max 230 150 Min 160 73 153 10.0 5.0 48.0 6.2 10.0 5.0 48.0 6.2 0 48.
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T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S Ultra DMA Data Burst Timing Descriptions Name t2CYCTYP tCYC t2CYC tDS tDH tDVS tDVH tCS tCH tCVS tCVH tZFS tDZFS tFS tLI tMLI tUI tAZ tZAH tZAD tENV tRFS tRP tIORDYZ tZIORDY tACK tSS Comment Notes Typical sustained average two cycle time Cycle time allowing for asymmetry and clock variations (from STROBE edge to STROBE edge) Two cycle time allowing for clock variations (from rising edg
PAGE 14
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S giving it a known state when released. Ultra DMA Sender and Recipient IC Timing Requirements Name UDMA Mode 0 (ns) UDMA Mode 1 (ns) UDMA Mode 2 (ns) UDMA Mode 3 (ns) UDMA Mode 4 (ns) Min tDSIC tDHIC tDVSIC tDVHIC tDSIC tDHIC tDVSIC tDVHIC Max 14.7 4.8 72.9 9.0 Min Max 9.7 4.8 50.9 9.0 Min 6.8 4.8 33.9 9.0 Max Min 6.8 4.8 22.6 9.0 Max Min Max 4.8 4.8 9.5 9.
PAGE 15
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S high level under the defined testing conditions from 100 nsec after 80% of a rising edge until 20% of the subsequent falling edge. Transcend Information Inc. 15 Ver 1.
PAGE 16
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S Initiating an Ultra DMA Data-In Burst (a) An Ultra DMA Data-In burst is initiated by following the steps lettered below. The timing diagram is shown in below: Ultra DMA Data-In Burst Initiation Timing. The associated timing parameters are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra DMA Data Burst Timing Descriptions.
PAGE 17
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH. NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM. Notes: The definitions for the IORDY:-DDMARDY:DSTROBE, -IORD: -HDMARDY:HSTROBE, and -IOWR:STOP signal lines are not in effect until DMARQ and -DMACK are asserted. A[02:00], -CS0 & -CS1 are True IDE mode signal definitions.
PAGE 18
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S Sustaining an Ultra DMA Data-In Burst An Ultra DMA Data-In burst is sustained by following the steps lettered below. The timing diagram is shown in below: Sustained Ultra DMA Data-In Burst Timing. The timing parameters are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra DMA Data Burst Timing Descriptions.
PAGE 19
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S Host Pausing an Ultra DMA Data-In Burst The host pauses a Data-In burst by following the steps lettered below. A timing diagram is shown in below: Ultra DMA Data-In Burst Host Pause Timing. The timing parameters are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra DMA Data Burst Timing Descriptions.
PAGE 20
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S Device Terminating an Ultra DMA Data-In Burst The device terminates an Ultra DMA Data-In burst by following the steps lettered below. The timing diagram is shown in below: Ultra DMA Data-In Burst Device Termination Timing. The timing parameters are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra DMA Data Burst Timing Descriptions.
PAGE 21
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S Host Terminating an Ultra DMA Data-In Burst The host terminates an Ultra DMA Data-In burst by following the steps lettered below. The timing diagram is shown in below: Ultra DMA Data-In Burst Host Termination Timing. The timing parameters are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra DMA Data Burst Timing Descriptions.
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T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S (p) In True IDE mode, the host shall not assert -IORD, -CS0, -CS1, nor A[02:00] until at least tACK after negating DMACK. ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH. NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM.
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T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S Initiating an Ultra DMA Data-Out Burst An Ultra DMA Data-out burst is initiated by following the steps lettered below. The timing diagram is shown in below: Ultra DMA Data-Out Burst Initiation Timing. The timing parameters are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13:Ultra DMA Data Burst Timing Descriptions.
PAGE 24
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH. NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM. Note: The definitions for the STOP, DDMARDY, and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted. A[02:00], -CS0 & -CS1 are True IDE mode signal definitions. Transcend Information Inc. 24 Ver 1.
PAGE 25
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S Sustaining an Ultra DMA Data-Out Burst An Ultra DMA Data-Out burst is sustained by following the steps lettered below. The timing diagram is shown in below: Sustained Ultra DMA Data-Out Burst Timing. The associated timing parameters are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra DMA Data Burst Timing Descriptions.
PAGE 26
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S Device Pausing an Ultra DMA Data-Out Burst The device pauses an Ultra DMA Data-Out burst by following the steps lettered below. The timing diagram is shown in below: Ultra DMA Data-Out Burst Device Pause Timing. The timing parameters are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra DMA Data Burst Timing Descriptions.
PAGE 27
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S Device Terminating an Ultra DMA Data-Out Burst The device terminates an Ultra DMA Data-Out burst by following the steps lettered below. The timing diagram for the operation is shown in below: Ultra DMA Data-Out Burst Device Termination Timing.
PAGE 28
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH. NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM. Note: The definitions for the STOP, DDMARDY, and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. A00-A02, -CS0 & -CS1 are True IDE mode signal definitions. Transcend Information Inc. 28 Ver 1.
PAGE 29
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S Host Terminating an Ultra DMA Data-Out Burst Termination of an Ultra DMA Data-Out burst by the host is shown in below: Ultra DMA Data-Out Burst Host Termination Timing while timing parameters are specified in Page 12: Ultra DMA Data Burst Timing Requirements and timing parameters are described in Page 13: Ultra DMA Data Burst Timing Descriptions.
PAGE 30
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH. NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM. Notes: The definitions for the STOP, DDMARDY, and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. A[02:00], -CS0 & -CS1 are True IDE mode signal definitions. Transcend Information Inc. 30 Ver 1.
PAGE 31
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S IDENTIFY DEVICE information The Identify Device command enables the host to receive parameter information from the device. This command has the same protocol as the Read Sector(s) command. The parameter words in the buffer have the arrangement and meanings defined in Table as below. All reserved bits or words are zero.
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T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S Word Address Default Value Total Bytes 51 52 53 54 55 56 57-58 59 60-61 62 63 64 0200h 0000h 000Xh XXXXh XXXXh XXXXh XXXXh 01XXh XXXXh 0000h 0X0Xh 0003h 2 2 2 2 2 2 4 2 4 2 2 2 65 XXXXh 2 66 XXXXh 2 67 68 69-79 80-81 82-84 85-87 88 89 90 91 92-127 128 129-159 160 161 162 163 164 165-167 168-255 XXXXh XXXXh 0000h 0000h XXXXh XXXXh 001Fh XXXXh XXXXh XXXXh 0000h XXXXh 0000h XX
PAGE 33
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S Transcend Information Inc. 33 Ver 1.
PAGE 34
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S Capacity Specifications: Transcend P/N Capacity Cylinder (C) Head (H) Sector (S) TS128MDOM40V-S 128MB 248 16 63 TS256MDOM40V-S 256MB 496 16 63 TS512MDOM40V-S 512MB 993 16 63 TS1GDOM40V-S 1GB 1942 16 63 TS2GDOM40V-S 2GB 3884 16 63 TS4GDOM40V-S 4GB 7769 16 63 TS8GDOM40V-S 8GB 15538 16 63 TS16GDOM40V-S 16GB 33149 15 63 Transcend Information Inc.
PAGE 35
T Trraan nsscceen nd d 4400--P Piin n IID DE EF Fllaassh hM Mo od du ullee T TS S112288M M ~~ 1166G GD DO OM M4400V V--S S Ordering Information TS XXXX DOM 40 V-S Transcend Product Type: V = Vertical H = Horizontal Capacity: 128M-512M = 128 MB up to 512 MB 1G-16G = 1 GB up to 16 GB Pin Count: 40 = 40 pin 44 = 44 pin IDE Flash Module (Disk On Module) The above technical information is based on industry standard data and has been tested to be reliable.