Datasheet

Bus Signal Line Load
The total capacitance C
L
the CLK line of the SD Memory Card bus is the sum of the bus master capacitance C
HOST
, the bus
capacitance C
BUS
itself and the capacitance C
CARD
of each card connected to this line:
C
L
= C
HOST
+ C
BUS
+ *C
CARD
Where N is the number of connected cards.
Parameter
Symbol
Min.
Max.
Unit
Remark
Pull-up resistance
R
CMD
R
DAT
10
100
k
To prevent bus floating
Bus signal line capacitance
C
L
40
pF
1 card
C
HOST
+C
BUS
shall not exceed
30 pF
Single card capacitance
C
CARD
10
pF
Pull-up resistance inside card (pin1)
R
DAT3
10
90
k
May be used for card detection
Capacity Connected to Power Line
C
C
5
uF
To prevent inrush current
Note that the total capacitance of CMD and DAT lines will be consist of C
HOST
, C
BUS
and one C
CARD
only because they are
connected separately to the SD Memory Card host.
Host should consider total bus capacitance for each signal as the sum of C
HOST
, C
BUS
, and C
CARD
, these parameters are
defined by per signal. The host can determine C
HOST
and C
BUS
so that total bus capacitance is less than the card estimated
capacitance load (C
L
=40 pF). The SD Memory Card guarantees its bus timing when total bus capacitance is less than
maximum value of C
L
(40 pF)