DDR4 TS1GHR72V1Z TS2GHR72V1Z 288Pin DDR4 2133 RDIMM 8GB~16GB Based on 1Gx4 On DIMM Thermal Sensor Pin Identification Symbol A0~A15 BA0, BA1 BG0, BG1 RAS_n CAS_n Description DDR4 Registered DIMM is high-speed, low power memory module that use 1Gx4bits DDR4 SDRAM in FBGA package and a 4Kbits serial EEPROM on a 288-pin printed circuit board. DDR4 Registered DIMM is a Dual In-Line Memory Module and is intended for mounting into 288-pin edge connector sockets.
Dimensions (Unit: millimeter) Note: 1. Tolerances on all dimensions +/-0.15mm unless otherwise specified.
Pin Assignments Pin No 1 Pin Name 12V3,NC Pin No 37 Pin Name VSS Pin No 73 Pin Name VDD Pin No 109 Pin Name VSS Pin No 145 2 VSS 38 DQ24 74 CK0_t 110 3 DQ4 39 VSS 75 CK0_c TDQS12_t, DQS12_t TDQS12_c, DQS12_c 76 VDD 112 VSS 148 TDQS14_t, 146 DQS14_t TDQS14_c, 111 DQS14_c 147 Pin Name 12V3,NC Pin No 181 VREFCA 182 Pin Name DQ29 Pin No 217 Pin Name VDD Pin No 253 Pin Name DQ41 VSS 218 CK1_t 254 VSS VSS 183 DQ25 219 CK1_c 255 DQS5_c DQ5 184 VSS 220 VDD 256
Block Diagram 8GB, 1Gx72 Module(1 Rank x4)
Block Diagram 16GB, 2Gx72 Module(2 Rank x4)
This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes in specifications at any time without prior notice.
Operating Temperature Condition Parameter Symbol Rating Unit Operating Temperature TOPER 0 to 85 ℃ Note: 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. Note 1,2 2. At 0 - 85℃, operation temperature range are the temperature which all DRAM specification will be supported. Absolute Maximum DC Ratings Parameter Symbol Value Unit Note Voltage on VDD relative to Vss VDD -0.3 ~ 1.
Differential AC and DC Input Levels DDR4-1600/1866/2133 Parameter Symbol Unit Note Min Max differential input high DC VIHdiff(DC) +0.150 NOTE 3 V 1 differential input low DC VILdiff(DC) NOTE 3 -0.150 V 1 differential input high AC VIHdiff(AC) 2 x (VIH(AC) - VREF) NOTE 3 V 2 differential input low AC VILdiff(AC) NOTE 3 2 x (VIL(AC) -VREF) V 2 Note: 1. Used to define a differential signal slew-rate. 2. for CK_t - CK_c use VIH.CA/VIL.CA(AC) of ADD/CMD and VREFCA; 3.
IDD Specification parameters Definition( IDD values are for full operating range of Voltage and Temperature) 8GB, 1Gx72 Module(1 Rank x4) Parameter Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating One bank Active-read-Precharge current; IOUT = 0mA; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =
16GB, 2Gx72 Module(2 Rank x4) Parameter Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating One bank Active-read-Precharge current; IOUT = 0mA; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern i
Timing Parameters & Specifications Speed Parameter DDR4 2133 Unit Symbol Min Max Average Clock Period tCK 0.938 <1.071 ns CK high-level width tCH 0.48 0.52 tCK CK low-level width tCL 0.48 0.52 tCK tDQSQ - TBD tCK/2 tDQSQ - TBD tCK/2 tQH TBD - tCK/2 tQH TBD - UI tDQSQ - TBD UI tQH TBD - UI tDQSQ TBD TBD UI tRPRE 0.9 TBD tCK DQS_t, DQS_c differential READ Postamble tRPST TBD TBD tCK DQS_t, DQS_c differential WRITE Preamble tWPRE 0.
WRITE recovery time Mode Register Set command cycle time Speed Parameter CAS_n to CAS_n command delay for same bank group CAS_n to CAS_n command delay for different bank group Auto precharge write recovery + precharge time ACTIVATE to ACTIVATE Command delay to different bank group for 2KB page size ACTIVATE to ACTIVATE Command delay to different bank group for 1KB page size ACTIVATE to ACTIVATE Command delay to different bank group for 1/ 2KB page size ACTIVATE to ACTIVATE Command delay to same bank group f
SERIAL PRESENCE DETECT SPECIFICATION TS1GHR72V1Z Serial Presence Detect Byte No.
122 same bank group Reserved Connector to SDRAM Bit Mapping Reserved Fine Offset for Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Smin), different bank group Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin) Fine Offset for Minimum Row Precharge Delay Time (tRPmin) Fine Offset for Minimum RAS to CAS Delay Time (tRCDmin) 123 Fin
384-551 End User Programmable - - TS2GHR72V1Z Serial Presence Detect Byte No.
60-77 78-116 - 00 - 83 - B5 - CE - 00 - 00 122 Connector to SDRAM Bit Mapping Reserved Fine Offset for Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Smin), different bank group Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin) Fine Offset for Minimum Row Precharge Delay Time (tRPmin) Fine Offset for Minimum RAS to CAS
DDR4 Serial presence detect with EEPROM TS2GHR72V1PL On DIMM Thermal 288Pin DDR4 2133 VLP RDIMM 16GB Based on 2Gx4 DDP Asynchronous reset Pin Identification DDR4 VLP Registered DIMM is high-speed, low power Symbol A0~A17 BA0, BA1 BG0, BG1 RAS_n memory module that use 2Gx4bits DDR4 SDRAM in CAS_n FBGA package and a 4Kbits serial EEPROM on a WE_n CS0_n, CS1_n, CS2_n, CS3_n CKE0, CKE1 Description 288-pin printed circuit board.
EVENT_n VTT RFU SPD signals a thermal event has occurred.
Note: 1. Tolerances on all dimensions +/-0.15mm unless otherwise specified.
Pin Assignments Pin No 1 Pin Name 12V3,NC Pin No 37 Pin Name VSS Pin No 73 Pin Name VDD Pin No 109 Pin Name VSS Pin No 145 2 VSS 38 DQ24 74 CK0_t 110 3 DQ4 39 VSS 75 CK0_c TDQS12_t, DQS12_t TDQS12_c, DQS12_c 76 VDD 112 VSS 148 TDQS14_t, 146 DQS14_t TDQS14_c, 111 DQS14_c 147 Pin Name 12V3,NC Pin No 181 VREFCA 182 Pin Name DQ29 Pin No 217 Pin Name VDD Pin No 253 Pin Name DQ41 VSS 218 CK1_t 254 VSS VSS 183 DQ25 219 CK1_c 255 DQS5_c DQ5 184 VSS 220 VDD 256
Block Diagram 16GB, 2Gx72 Module(2 Rank x4) This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes in specifications at any time without prior notice.
Operating Temperature Condition Parameter Symbol Rating Unit Operating Temperature TOPER 0 to 85 ℃ Note: 3. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. Note 1,2 4. At 0 - 85℃, operation temperature range are the temperature which all DRAM specification will be supported. Absolute Maximum DC Ratings Parameter Symbol Value Unit Note Voltage on VDD relative to Vss VDD -0.3 ~ 1.
Differential AC and DC Input Levels DDR4-1600/1866/2133 Parameter Symbol Unit Note Min Max differential input high DC VIHdiff(DC) +0.150 NOTE 3 V 1 differential input low DC VILdiff(DC) NOTE 3 -0.150 V 1 differential input high AC VIHdiff(AC) 2 x (VIH(AC) - VREF) NOTE 3 V 2 differential input low AC VILdiff(AC) NOTE 3 2 x (VIL(AC) -VREF) V 2 Note: 4. Used to define a differential signal slew-rate. 5. for CK_t - CK_c use VIH.CA/VIL.CA(AC) of ADD/CMD and VREFCA; 6.
IDD Specification parameters Definition( IDD values are for full operating range of Voltage and Temperature) 16GB, 2Gx72 Module(2 Rank x4) Parameter Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating One bank Active-read-Precharge current; IOUT = 0mA; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =
Timing Parameters & Specifications Speed Parameter DDR4 2133 Unit Symbol Min Max Average Clock Period tCK 0.938 <1.071 ns CK high-level width tCH 0.48 0.52 tCK CK low-level width tCL 0.48 0.52 tCK tDQSQ - TBD tCK/2 tDQSQ - TBD tCK/2 tQH TBD - tCK/2 tQH TBD - UI tDQSQ - TBD UI tQH TBD - UI tDQSQ TBD TBD UI tRPRE 0.9 TBD tCK DQS_t, DQS_c differential READ Postamble tRPST TBD TBD tCK DQS_t, DQS_c differential WRITE Preamble tWPRE 0.
Speed Parameter CAS_n to CAS_n command delay for same bank group CAS_n to CAS_n command delay for different bank group Auto precharge write recovery + precharge time ACTIVATE to ACTIVATE Command delay to different bank group for 2KB page size ACTIVATE to ACTIVATE Command delay to different bank group for 1KB page size ACTIVATE to ACTIVATE Command delay to different bank group for 1/ 2KB page size ACTIVATE to ACTIVATE Command delay to same bank group for 2KB page size ACTIVATE to ACTIVATE Command delay to sa
SERIAL PRESENCE DETECT SPECIFICATION TS2GHR72V1PL Serial Presence Detect Byte No.
78-116 117 118 119 120 121 122 123 Reserved Fine Offset for Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Smin), different bank group Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin) Fine Offset for Minimum Row Precharge Delay Time (tRPmin) Fine Offset for Minimum RAS to CAS Delay Time (tRCDmin) - 00 - 83 - B5 - CE - 00
