Data Sheet

4.1.3 Power On or Power Cycle
Followings are requirements for Power on and Power cycle to assure a reliable SD Card hard reset.
(1) Voltage level shall be below 0.5V
(2) Duration shall be at least 1ms.
4.1.4 Power Supply Ramp Up
The power ramp up time is defined from 0.5V threshold level up to the operating supply voltage which is
stable between VDD(min.) and VDD(max.) and host can supply SDCLK.
Followings are recommendation of Power ramp up:
(1) Voltage of power ramp up should be monotonic as much as possible.
(2) The minimum ramp up time should be 0.1ms.
(3) The maximum ramp up time should be 35ms for 2.7-3.6V power supply.
(4) Host shall wait until VDD is stable.
(5) After 1ms VDD stable time, host provides at least 74 clocks before issuing the first command.
4.1.5 Power Down and Power Cycle
When the host shuts down the power, the card VDD shall be lowered to less than 0.5Volt for a minimum
period of 1ms. During power down, DAT, CMD, and CLK should be disconnected or driven to logical 0 by the
host to avoid a situation that the operating current is drawn through the signal lines.
If the host needs to change the operating voltage, a power cycle is required. Power cycle means the power is
turned off and supplied again. Power cycle is also needed for accessing cards that are already in Inactive State.
To create a power cycle the host shall follow the power down description before power up the card (i.e. the
card VDD shall be once lowered to less than 0.5Volt for a minimum period of 1ms).