Datasheet

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EMC210 – 8GB ~ 32GB

e.MMC 4.51 / BGA-153

Transcend’s e.MMC-EMC210, is an

Embedded Flash Drive (EFD) designed

for industrial applications such as

embedded system, vehicle entertainment

system, GPS, games, email, office, etc. It

is a hybrid device combining an

embedded thin flash controller and

standard MLC NAND flash memory,

supporting an industry standard e.MMC

4.51 interface.

The outstanding performance and strict

environment test enable Transcend’s

e.MMC 210 to fulfill the needs of a wide

variety of industrial application devices.

EMC 210 also provide 8~32GB of

capacities in JEDEC compatible form

factor and is an ideal solution for the

vendors who require easy integration, fast

entry to market and high storage capacity.

Features

• Compliant with JEDEC e.MMC Specification

Ver. 4.51

• Supports three data bus widths: 1bit(default),

4bit, 8bit.

• Uses an embedded thin memory controller

and MLC NAND flash

• Mechanical design complies with

JESD84-C44 Specification

• Dual power system

• Core voltage (VCC) 2.7-3.6V

• I/O (VCCQ) voltage, either: 1.7-1.95V or

2.7-3.6V

• Variable clock frequencies of 0-200 MHz

• Supports three data bus widths: 1bit(default),

4bit, 8bit.

• Static global wear leveling

• BCH ECC:53bit/1KB

• Fully cycle environment test

• RoHS compliant

Controller

Flash

Memory

MMC Bus Interface

Transcend e.MMC

Data I/O

CMD

Summary of content (22 pages)

PAGE 1
EMC210 – 8GB ~ 32GB Features • Compliant with JEDEC e.MMC Specification Ver. 4.51 e.MMC 4.51 / BGA-153 • Supports three data bus widths: 1bit(default), 4bit, 8bit. Transcend’s e.MMC-EMC210, is an Embedded Flash Drive (EFD) designed for industrial applications such as embedded system, vehicle entertainment system, GPS, games, email, office, etc. It is a hybrid device combining an embedded thin flash controller and standard MLC NAND flash memory, supporting an industry standard e.MMC 4.51 interface.
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e.MMC Bus and Power Lines Transcend’s e.MMC bus has the following communication and power lines: • CMD: Command is a bidirectional signal. The host and Transcend’s e.MMC operate in two modes, open drain and push-pull. • DAT0-7: Data lines are bidirectional signals. Host and Transcend’s e.MMC operate in push-pull mode. • CLK: Clock input. • RST_n: Hardware Reset Input • VCCQ: VCCQ is the power supply line for host interface. • VCC: VCC is the power supply line for internal flash memory.
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Parameter Min Max Unit Supply voltage (3.3V) 2.7 3.6 V Supply voltage (1.8V) 1.7 1.95 V I/O Leakage current -10 10 uA Remark Open-Drain bus signal level Output high voltage (VOH) VCCQ – 0.2 Output Low voltage (VOL) V 0.3 V IOL = 2mA V IOH = -100uA @ VDD min 0.125 * VCCQ V IOL = 100uA @ VDD min Push-Pull bus signal level (2.7~3.6V) Output high voltage (VOH) 0.75 * VCCQ Output Low voltage (VOL) Input high voltage (VIH) 0.625 * VCCQ VCCQ + 0.
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e.MMC 4.51 selected feature overview • Power Off Notification The host should notify the device before it powers the device off. This allows the device to better prepare itself for being powered off. For more details, refer to section 6.6.36 of the JEDEC Standard Specification NO. JESD84-B451. • Packed Commands Read and write commands can be packed in groups of commands (either all read or all write) that transfer the data for all commands in the group in one transfer on the bus, to reduce overheads.
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unmapped user address space. For more details, refer to section 6.6.13 of the JEDEC Standard Specification NO.JESD84-B451. • Discard The discard is similar operation to Trim. The discard function allows the host to identify data that’s no longer required so that EMC210 can erase the data if necessary during background erase events. For more details, refer to section 6.6.14 of the JEDEC Standard Specification NO.JESD84-B451.
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• High Priority Interrupt (HPI) In some scenarios, different types of data on the device may have different priorities for the host. For example, writing operation may be time consuming and therefore there might be a need to suppress the writing to allow demand paging requests in order launch a process when requested by the user. For more details, refer to section 6.6.26 of the JEDEC Standard Specification NO. JESD84-B451.
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Product Specifications • Specification P/N Package Ball Number Technology TS8GEMC210 11.5 x 13 x 1.0 mm 153 MLC TS16GEMC210 11.5 x 13 x 1.0 mm 153 MLC TS32GEMC210 11.5 x 13 x 1.2 mm 153 MLC • Performance Performance* P/N Seq. Read Seq. Write Ran. Read Ran. Write TS8GEMC210 140 40 2100 IOPS 600 IOPS TS16GEMC210 140 60 2100 IOPS 700 IOPS TS32GEMC210 140 60 2100 IOPS 700 IOPS *Depending on operating condition, the result might be different.
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• Power Consumption Power Consumption (mA , 25°C) P/N VCCQ APS Sleep Write Read TS8GEMC210 0.05 0.05 21 37 TS16GEMC210 0.05 0.05 23 37 TS32GEMC210 0.05 0.05 23 37 *APS: Auto Power Suspend • Power Supply P/N VCC VCCQ TS8GEMC210 2.7-3.6V 1.7-1.95V / 2.7-3.6V TS16GEMC210 2.7-3.6V 1.7-1.95V / 2.7-3.6V TS32GEMC210 2.7-3.6V 1.7-1.95V / 2.7-3.6V *VCCQ (I/O) 3.3V is not supported in HS200 operation.
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Physical Specifications
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Interface Description
PAGE 11
153-Ball AA Device M6 Symbol Type Ball Function CLK Input Clock: Each cycle directs a 1-bit transfer on the command and DAT lines. M5 CMD Input Command: A bidirectional channel used for device initialization and command transfers. Command has two operation modes: • Open-drain for initialization • Push-pull for fast command transfer A3 DAT0 I/O Data I/O0: Bidirectional channel used for data transfer. A4 DAT1 I/O Data I/O1: Bidirectional channel used for data transfer.
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153-Ball AA Device E7, G5, H10, K8 Symbol Type VSS Supply Ball Function VSS: Flash memory I/F and Flash memory ground connection. C4, N2, N5, P4, P6 VSSQ Supply VSSQ: Memory controller core and MMC I/F ground connection. C2 VDDi VDDi: Connect 0.1µF capacitor from VDDi to ground Miscellaneous D4 NC Index ─ Index: Can be connected to ground or left floating. A1, A2, A8, A9, A10, A11, NC ─ A12, A13, A14, B1, B7, No connect: Can be connected to ground or left floating.
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153-Ball AA Device Symbol Type Ball Function J5, K6, K7, K10, P7, P10 Card Register • OCR Register For Transcend e.MMC, the value of 32-bit OCR register is 0xC0FF8080 Note: OCR bit [31] is set to LOW if the card has not finished the power up routine.
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R/W/C_P: Writable after value cleared by power failure and H/W reset assertion (the value not cleared by CMD0 reset) and readable. R/W/E_P: Multiple writable with value reset after power failure, H/W reset assertion and any CMD0 reset and readable. W/E_P: Multiple writable with value reset after power failure, H/W reset assertion and any CMD0 reset and not readable.
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max Max. write current @ VDD min VDD_W_CURR_MIN 3 R 111b [55:53] Max.
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• Extended CSD register R: Read only. W: One time programmable and not readable. R/W: One time programmable and readable. W/E: Multiple writable with value kept after power failure, H/W reset assertion and any CMD0 reset and not readable. R/W/E: Multiple writable with value kept after power failure, H/W reset assertion and any CMD0 reset and readable. R/W/C_P: Writable after value cleared by power failure and H/W reset assertion (the value not cleared by CMD0 reset) and readable.
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Extended partitions attribute support EXT_SUPPORT R 3h [494] Cache size CACHE_SIZE R 20000h [252:249] Generic CMD6 timeout GENERIC_CMD6_TIME R 64h [248] Power off notification(long) timeout POWER_OFF_LONG_TIME R 64h [247] Background operations status BKOPS_STATUS R 0h [246] Number of correctly programmed sectors CORRECTLY_PRG_SECTOR S_NUM R 0h [245:242] 1st initialization time after partitioning INI_TIMEOUT_AP R Ah [241] Power class for 52MHz, DDR at 3.
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Access size ACC_SIZE R 6h [225] High-capacity erase unit size HC_ERASE_GRP_SIZE R 1h [224] High-capacity erase timeout ERASE_TMEOUT_MULT R 2h [223] Reliable write sector count REL_WR_SEC_C R 1h [222] High-capacity write protect group size HC_WP_GRP_SIZE R 10h [221] Sleep current (VCC) S_C_VCC R 7h [220] Sleep current (VCCQ) S_C_VCCQ R 7h [219] Sleep/awake timeout S_A_TIMEOUT R 13h [217] Sector Count SEC_COUNT R Depends on capacity [215:212] Minimum Write Performa
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Power class for 52MHz at PWR_CL_52_360 3.6V 1 R R 0h [202] Power class for 26MHz at PWR_CL_26_195 1.95V 1 R R 0h [201] Power class for 52MHz at PWR_CL_52_195 1.
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& R/W/E_P FW configuration FW_CONFIG R/W 0h [169] RPMB Size RPMB_SIZE_MULT R 20h [168] Write reliability setting register WR_REL_SET R/W 1Fh [167] Write reliability parameter register WR_REL_PARAM R 5h [166] Start Sanitize operation SANITIZE_START W/E_P 0h [165] Manually start background operations BKOPS_START W/E_P 0h [164] Enable background operations handshake BKOPS_EN R/W 0h [163] H/W reset function RST_n_FUNCTION R/W 0h [162] HPI management HPI_MGMT R/W/E_P 0h
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Program CID/CSD in DDR mode support PROGRAM_CID_CSD_DDR_ SUPPORT R 0h [130] Vendor Specific Fields VENDOR_SPECIFIC_FIELD vendor specific Reserved [127:64] UDA Quick Health info UDA_HEALTH_STATUS R 0h [71:68] EUDA Quick Health info EUDA_HEALTH_STATUS R 0h [67:64] Native sector size NATIVE_SECTOR_SIZE R 1h [63] Sector size emulation USE_NATIVE_SECTOR R/W 0h [62] Sector size DATA_SECTOR_SIZE R 0h [61] 1st initialization after disabling sector size emulation INI_TIMEOUT_EMU
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Marking 1st row : 2nd row : 3rd row: 4th row : 5th row : Transcend LOGO Sales P/N Internal use Country of Origin + Date Code Serial number Revision History Modification Content Version Date V0.1 2015/03/23 V0.2 2015/03/31 V1.