User's Manual
Table Of Contents
- Health Limits
- Contents
- Before You Begin
- Developing the Installation Site Plan
- Installing and Configuring the MPI 6000
- Lane Tuning Guidelines
- Optimizing MPI 6000 Reader System Performance
- General Software Information
- Configuration Commands and Responses
- Configuring the MPI 6000
- Required Commands to Set Up MPI 6000 Reader
- System Interface Command Group Commands
- System Identify
- Set Communications Baud Rate
- Get Communications Baud Rate
- Set Time and Date
- Get Time and Date
- Firmware Download
- Reset Reader
- Get Stored Tag Response Message
- Get Number of Stored Tag Response Messages
- Delete All Stored Tag Response Messages
- Get System Startup Status
- Get Lane Controller Interface Status
- Get System Interface Status
- Get DigBrd Hdwr Remote Inventory
- Get DigBrd CPU Boot Fmwr Remote Inventory
- Get DigBrd CPU Appl Fmwr Remote Inventory
- Get DigBrd FPGA UDP/IP Core Fmwr Remote Inventory
- Get UDP/IP Core Lane Controller Parameters
- Set UDP/IP Core IP Address
- Get UDP/IP Core IP Address
- Get UDP/IP Core Port Number
- Configuring the MPI 6000
- Tag Command Processing
- System Diagnostics and Preventive Maintenance
- Acronyms and Glossary
- Block Diagrams
- System Technical Specifications
- Hardware Interfaces
D-3
Appendix D
Hardware Interfaces
This appendix describes the physical interconnections within an MPI
6000 System.
Hardware Interfaces
This appendix describes the hardware interfaces in the MPI 6000 and to external com-
ponents, such as antennas.
Figure D-1 shows the basic hardware interconnections for the MPI 6000.
Figure D-1 MPI 6000 Hardware Interconnection Block Diagram