User Guide
Table Of Contents
- Contents
- Contents
- Introduction to the Mercury6e- Transcore Module
- Functionality of the Embedded Modules
- Overview of the Communication Protocol
- Command Set
- Boot Loader Commands
- Multi-Protocol Tag Commands
- Allegro/Title-21 Tag Commands
- eGo/SeGo Tag Command Set
- ATA Tag Command Set
- Gen2 Tag Commands
- Get Configuration Commands
- Get Hardware Version (10h)
- Get Antenna Configuration (61h)
- Get Read TX Power (62h)
- Get Current Tag Protocol (63h)
- Get Write TX Power (64h)
- Get Frequency Hop Table (65h)
- Get User GPIO Inputs (66h)
- Get Current Region (67h)
- Get Power Mode (68h)
- Get User Mode (69h)
- Get Reader Configuration(6Ah)
- Get Protocol Configuration (6Bh)
- Get Reader Statistics (6Ch)
- Get Available Protocols (70h)
- Get Available Regions (71h)
- Get Current Temperature (72h)
- Set Configuration Commands
- Regulatory Test Commands
- Appendix A: Hardware Details
- Appendix B: Using the ArbSer Application
- Appendix C: Error Messages
- Common Error Messages
- FAULT_MSG_WRONG_NUMBER_OF_DATA – (100h)
- FAULT_INVALID_OPCODE – (101h)
- FAULT_UNIMPLEMENTED_OPCODE – 102h
- FAULT_MSG_POWER_TOO_HIGH – 103h
- FAULT_MSG_INVALID_FREQ_RECEIVED (104h)
- FAULT_MSG_INVALID_PARAMETER_VALUE - (105h)
- FAULT_MSG_POWER_TOO_LOW - (106h)
- FAULT_UNIMPLEMENTED_FEATURE - (109h)
- FAULT_INVALID_BAUD_RATE - (10Ah)
- Bootloader Faults
- FPGA Faults
- Flash Faults
- Protocol Faults
- FAULT_NO_TAGS_FOUND – (400h)
- FAULT_NO_PROTOCOL_DEFINED – 401h
- FAULT_INVALID_PROTOCOL_SPECIFIED – 402h
- FAULT_WRITE_PASSED_LOCK_FAILED – 403h
- FAULT_PROTOCOL_NO_DATA_READ – 404h
- FAULT_AFE_NOT_ON – 405h
- FAULT_PROTOCOL_WRITE_FAILED – 406h
- FAULT_NOT_IMPLEMENTED_FOR_THIS_PROTOCOL – 407h
- FAULT_PROTOCOL_INVALID_WRITE_DATA – 408h
- FAULT_PROTOCOL_INVALID_ADDRESS – 409h
- FAULT_GENERAL_TAG_ERROR – 40Ah
- FAULT_DATA_TOO_LARGE – 40Bh
- FAULT_PROTOCOL_INVALID_KILL_PASSWORD – 40Ch
- FAULT_PROTOCOL_KILL_FAILED - 40Eh
- FAULT_PROTOCOL_BIT_DECODING_FAILED - 40Fh
- FAULT_PROTOCOL_INVALID_EPC – 410h
- FAULT_PROTOCOL_INVALID_NUM_DATA – 411h
- FAULT_GEN2 PROTOCOL_OTHER_ERROR - 420h
- FAULT_GEN2_PROTOCOL_MEMORY_OVERRUN_BAD_PC - 423h
- FAULT_GEN2 PROTOCOL_MEMORY_LOCKED - 424h
- FAULT_GEN2 PROTOCOL_INSUFFICIENT_POWER - 42Bh
- FAULT_GEN2 PROTOCOL_NON_SPECIFIC_ERROR - 42Fh
- FAULT_GEN2 PROTOCOL_UNKNOWN_ERROR - 430h
- Analog Hardware Abstraction Layer Faults
- Tag ID Buffer Faults
- System Errors
- Common Error Messages
- Appendix D: FPGA Support
Appendix D: FPGA Support 203
Appendix D: FPGA Support
This appendix explains how to create and update Field Programmable Gate Array
(FPGA) images for the M6e-TC.
Creating an FPGA Image DAT File
Creating an FPGA Image DAT file requires the use of an Actel programming environment.
In the following instructions the use of Libero 8.4 is assumed. The process for other Libero
versions or Actel programming environments may vary. This process assumes Verilog
files have been pre-compiled and you are at the compiling stage.
In order to create an FPGA image DAT file from STAPL output the following programs are
required:
Libero Designer - Verilog/VHDL complier to build the STAPL (.stp) file.
datgen.exe - Windows command line tool for converting the STAPL output to a .dat
binary format.
Follow these steps to build the DAT file: