Datasheet

TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12
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Read entire documentation; especially the “Supplemental Directives” on page 224.
 MAIN MANUAL 
15. Decoder Unit: Connecting ABN, SSI, or SPI Encoders correctly
TMC4361A is equipped with an encoder input interface for incremental ABN encoders, absolute
SSI or SPI encoders. This chapter provides basic setup information for correct analysis of
connected encoder signals.
Decoder Pins
Pin Names
Type
Remarks
A_SCLK
Input or Output
A signal of ABN encoder or
Serial Clock output for absolute SSI, or SPI encoders.
ANEG_NSCLK
Input or Output
Negated A signal of ABN encoder or
Negated Serial Clock output for SSI encoder or
Low active Chip Select signal for SPI encoders.
B_SDI
Input
B signal of ABN encoder or
Serial Data Input of SSI, or SPI encoders.
BNEG_NSDI
Input or Output
Negated B signal of ABN encoder or
Negated Serial Data Input of SSI encoders or
Serial Data Output of SPI encoder.
N
Input
N signal of ABN encoder.
NNEG
Input
Negated N signal of ABN encoder.
Table 55: Dedicated Decoder Unit Pins
Decoder Unit Registers
Register Name
Register address
Remarks
GENERAL_CONF
0x00
RW
Bit11:10: serial_enc_in_mode, Bit12: diff_enc_in_disable
INPUT_FILT_CONF
0x03
RW
Input filter configuration (SR_ENC_IN, FILT_L_ENC_IN).
ENC_IN_CONF
0x07
RW
Encoder configuration register.
ENC_IN_DATA
0x08
RW
Serial encoder input data structure.
STEP_CONF
0x0A
RW
Motor configurations.
ENC_POS
0x50
RW
Current absolute encoder position in microsteps.
ENC_LATCH
0x51
R
Latched absolute encoder position.
ENC_POS_DEV
0x52
R
Deviation between XACTUAL and ENC_POS .
ENC_CONST
0x54
R
Internally calculated encoder constant.
Encoder Register Set
0x51…58
0x62…63
W
Encoder configuration parameter.
Encoder velocity
0x65
0x66
R
Current encoder velocity (signed).
Current filtered encoder velocity (signed).
ADDR_TO_ENC
DATA_TO_ENC
0x68
0x69
W
Serial encoder request data.
ADDR_FROM_ENC
DATA_FROM_ENC
0x6A
0x6B
R
Serial encoder request data response.
Encoder compensation
0x7D
W
Encoder compensation register set.
Table 56: Dedicated Decoder Unit Registers