Datasheet

TMC4671 Datasheet • IC Version V1.00 | Document Revision V1.03 • 2018-Sept-06
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14 Errata
The Errata of the TMC4671-ES are listed here and in the particular descriptions they apply to.
1. SPI Slave Interface
The SPI Slave Interface in the TMC4671-ES shows following error. During transaction of MSB of read
data might get corrupted. This shows in two different ways. First one is a 40 ns pulse (positive or
negative) on MISO at the beginning of transfer of that particular bit. This pulse can corrupt the MSB
of read data and this error can be avoided when SPI clock frequency is set to 1 MHz. Second error
also corrupts MSB of read data when MSB of regsiter is unstable. For example current measurement
noise around zero. In this case MSB should be ignored when possible. Please also make sure that e.g.
actual torque value can be read from register PID_TORQUE_FLUX_ACTUAL or from INTERIM_DATA
register, where it is showing up in the lower 16 bits. These errors will be fixed in next IC version. SPI
write access is not affected and can be performed at 8 MHz clock frequency.
2. Realtime Monitoring Interface
The TRINAMIC Realtime Monitoring Interface can not be used with galvanic isolation as timing of SPI
communication is too strict. This will be fixed in future version so galvanic isolation of SPI signals will
be possible with defined latency of isolators.
3. PI Controllers
The P Factor in the advanced position controller is not properly scaled. Due to the high gain in Velocity
control loop, the position controller gain should be respectively low. The P Factor normalization of
Q8.8 does not match these needs. This will be changed in a future version of the chip to a different Q
Format. This change will cause changes in user’s application controller software. We recommend to
use the classical PI control structure if performance is not sufficient.
The integrator in the advanced PI controller is not reset when P or I parameters are set to zero. As a
workaround controller can be disabled by switching to stopped mode or to a lower cascade level and
thereby the integrator is reset. This behaviour will be changed in the next IC version.
4. Inbuilt ADCs
The inbuilt Delta Sigma ADCs show an error, where both groups are disturbing each other. When
one group is deactivated, everything is fine, but with both groups being active ADC Data might
be corrupted. This error occurs if clock signals of both groups are not in phase. Clock phase can
be changed by toggling the dsADC_MCLK_B to a non-round figure like 0x30000001 and back to
0x20000000. This toggling has to be repeated until measurement is clean.
If the second ADC Group is not needed, it can be shut down by setting dsADC_MCLK_B to 0.
The distortion can be detected by monitoring measurement at reference voltage. Use register
DS_ANALOG_INPUT_STAGE_CFG to switch on the reference voltage for monitoring.
5. Pins PWM_IDLE_H and PWM_IDLE_L without function
Pins PWM_IDLE_H and PWM_IDLE_L are intended to determine Power on Reset Gate Driver Polarity.
This feature is not working properly as the gate driver polarity always powers up to Low Side Polarity
to be Active Low and High Side Polarity to be active high. This will be corrected in the next version of
the chip.
6. Space Vector PWM does not allow higher voltage utilization
The Space vector PWM does not allow higher voltage utilization. This will be fixed in next version of
the chip.
7. Step Direction Counter not used as Target Position
The step direction interface correctly counts up and down the target position, but the step direction
counter position is not used as the target position for positioning as intended. The TMC4671-ES
always uses the target position written via SPI, RTMI, or UART into the register bank as the target
position for positioning. As a work around for evaluation of step direction target position control,
the user can read out the target position periodically and write it back to the register bank as the
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