Integration Manual

Version 0.94 - 2006-09 11
2.2 Pin Description
2.2.1 J1 Connector
Table 2: Signals on J1
J1
Pin Nr
Pin Name Signal Name Signal
Level
Type Description
1, 2,
16, 17
VSS VSS Ground Power/
Signal
Power supply 0V-terminal and
signal return path
3, 4,
15
VCC_3V3 +Vin 3.3V –
5 V
Power Power supply positive terminal
5 – 9 Reserved for future use,
do not connect
10 RESET Hardware reset CMOS I Active low. Internal pull-up 56kΩ
11 –12 Reserved for future use,
do not connect
13 MOSI SPI - MOSI CMOS I SPI: MOSI (Master Output –
Slave Input)
14 SPI-SS-n SPI-SS-n / SPI - CS0 CMOS I SPI: CS (Chip Select)
18 SPI-CLK SPI-CLK CMOS I SPI clock input.
Max frequency for SPI is 66MHz
19 SPI-ExInt SPI - ExInt CMOS O SPI: Interrupt
20 MISO SPI - MISO CMOS O SPI: MISO (Master Input –
Slave Output)