Integration Manual

ManualsBrandsu-blox ManualsElectronicsJODY-W374-00A and JODY-W374-00B

JODY-W3 series - System integration manual

UBX-19011209 - R07 System description Page 11 of 71

C2-Restricted

Function

Pin name

Pin no.

Power

Type

Description

Active

Power down

See also Configuration pins.

Same function as pin 10.

GPIO_13

65

VIO

I/O

GPIO[13] / UART_DTRn

I/O

Drive high

GPIO_24

66

VIO

I/O

GPIO[24]

I/O

Tristate

GPIO_25

67

VIO

I/O

GPIO[25]

I/O

Drive high

GPIO_26

68

VIO

I/O

GPIO[26]

I/O

Tristate

GPIO_27

69

VIO

I/O

GPIO[27]

I/O

Tristate

GPIO_23

70

VIO

I/O

GPIO[23]

I/O

Drive low

GPIO_22

71

VIO

I/O

GPIO[22]

I/O

Drive high

BT_HOST_WAKE

87

VIO

I/O

Bluetooth wake-up from module /

GPIO[16]

Configuration pin CON[6]

See also Configuration pins.

Same function as pin 12.

I/O

Tristate

GPIO_17

88

VIO

I/O

GPIO[17] /

PTA external radio grant signal (output)

Configuration pin CON[7]

See also Configuration pins.

I/O

Tristate

GPIO_18

89

VIO

I/O

GPIO[18] /

Independent software reset for Wi-Fi

subsystem (input) /

PTA request from the external radio

(input)

I/O

Tristate

GPIO_19

90

VIO

I/O

GPIO[19] /

Independent software reset for

Bluetooth subsystem (input) /

PTA external radio priority signal (input)

I/O

Tristate

GPIO_0

91

VIO

I/O

GPIO[0]

I/O

Drive low

GPIO_1

92

VIO

I/O

GPIO[1] /

Independent software reset for

Bluetooth subsystem (input) /

PTA external radio priority signal (input)

I/O

Tristate

PCIe host

interface

PCIE_PME#

40

VIO

I/O

PCIe wake signal

(input/output, active low)

Note: Pull-up required on host side

I/O

-

PCIE_CLKREQ#

41

VIO

I/O

PCIe clock request

(input/output, active low)

Note: Pull-up required on host side

I

-

PCIE_PERST#

42

VIO

I/O

PCIe host indication to reset the device

(input, active low)

Note: Muxed with GPIO[20]

I/O

Drive high

PCIE_REFCLKN

43

1V8

I

PCIe negative differential clock input

I

-

PCIE_REFCLKP

44

1V8

I

PCIe positive differential clock input

I

-

PCIE_RDN

45

1V8

I

PCIe negative differential data input

Note: place a 220nF coupling capacitor

close to host CPU output.

I

-

PCIE_RDP

46

1V8

I

PCIe positive differential data input

Note: place a 220nF coupling capacitor

close to host CPU output.

I

-

PCIE_TDN

47

1V8

O

PCIe negative differential data output

O

-

PCIE_TDP

48

1V8

O

PCIe positive differential data output

O

-

Host

interface

CONFIG[0]

7

1V8

I

Host interface configuration pin

See also Configuration pins.

I

Tristate

Commented [CT9]: Q. Is it OK to leave these

definitions as “TBD” for Gate 6 releases?