Integration Manual

JODY-W3 series - System integration manual
UBX-19011209 - R07 System description Page 16 of 71
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1.5 Data communication interfaces
JODY-W3 series modules support PCI express v2.0, SDIO 3.0 and high-speed UART host interfaces.
This means that all Wi-Fi traffic is communicated through either PCIe or SDIO by setting the
appropriate boot option. The high-speed UART interface between the host and the JODY-W3 series
module is used for the Bluetooth traffic. For information about the available host interface
configuration options, see also Configuration pins.
1.5.1 SDIO 3.0 interface
JODY-W3 series modules include an SDIO device interface that is compatible with the industry-
standard SDIO 3.0 specification (UHS-I, up to 104 Mbyte/s). The host controller uses the SDIO bus
protocol to access the Wi-Fi functions. The interface supports 4-bit and 1-bit SDIO transfer modes at
the full clock range up to 208 MHz. The modules also support legacy modes like Default Speed (DS)
and High-Speed (HS) modes.
☞ The SDIO signal voltage is fixed to 1.8 V for Default Speed and High-Speed modes.
JODY-W3 modules act as devices on the SDIO bus. Table 8 summarizes the supported bus speed
modes.
Bus speed mode
Max. bus apeed [MB/s]
Max. clock frequency [MHz]
Signal voltage [V]
SDR104
104
208
1.8
SDR50
50
100
1.8
DDR50
50
50
1.8
SDR25
25
50
1.8
SDR12
12.5
25
1.8
HS: High-Speed
25
50
1.8
DS: Default Speed
12.5
25
1.8
Table 8: SDIO bus speeds
Pull-up resistors are required for all SDIO data and command lines. These pull-up resistors can be
provided either externally on the host PCB or internally in the host application processor. Depending
on the routing of the SDIO lines on the host, it might be necessary to connect in-series termination
resistors to these lines. See also Data communication interfaces.
Name
I/O
Description
Remarks
SD_CLK
I
SDIO Clock input
SD_CMD
I/O
SDIO Command line
External PU required
SD_D0
I/O
SDIO Data line bit [0]
External PU required
SD_D1
I/O
SDIO Data line bit [1]
External PU required
SD_D2
I/O
SDIO Data line bit [2]
External PU required
SD_D3
I/O
SDIO Data line bit [3]
External PU required
Table 9: SDIO signal definitions
SDIO interface pins are powered by the 1V8 voltage domain.
1.5.2 PCIe interface
A PCIe v2.0 interface (Gen 2, single lane) is supported in the Wi-Fi section of the chipset. The interface
supports link speeds of 2.5 and 5 Gbps.
Table 10Table 13 shows the description of the chipset pins. The interface data pins are powered from
the 1V8 voltage supply, and the interface GPIOs are powered from VIO.
Commented [CT24]: This must refer to the previous
section 1.4.5. right?
Commented [LB25R24]: Correct
Formatted: Normal Document Reference