Integration Manual
JODY-W3 series - System integration manual
UBX-19011209 - R07 Design-in Page 28 of 71
C2-Restricted
• Low output ripple: The switching regulator peak-to-peak Voltage ripple must not exceed the
specified limits. This requirement applies both to voltage ripple generated by SMPS operating
frequency and to high frequency noise generated by power switching.
• PWM/PFM mode operation: It is preferable to select regulators with fixed Pulse Width Modulation
(PWM) mode. Pulse Frequency Modulation (PFM) mode typically exhibits higher ripple and may
affect RF performance. If power consumption is not a concern, PFM/PWM mode transitions
should be avoided in favor of fixed PWM operation to reduce the peak-to-peak noise on voltage
rails. Switching regulators with mixed PWM/PFM mode can be used provided that the PFM/PWM
modes and transition between modes complies with the requirements.
2.3.1.2 Guidelines for supply circuit design using a Low Drop-Out (LDO) linear
regulator
The use of a linear regulator is suggested when the difference from the available supply rail and the
3V3, 1V8 or VIO value is relatively low. The linear regulators provide acceptable efficiency when
transforming a supply of less than 5 V to a voltage value within the normal operating range of the
module. A linear regulator can be also considered to power the VIO section due to the low current
requirements, especially if cascaded from a SMPS-generated low voltage rail.
The characteristics of the Low Drop-Out (LDO) linear regulator used to power the voltage rails must
meet the following prerequisites to comply with the requirements summarized in Table 4.
• Power capabilities: The LDO linear regulator with its output circuit must be capable of providing a
voltage value to the 3V3, 1V8 or VIO pins within the specified operating range and must be capable
of withstanding and delivering the maximum specified peak current while in connected-mode.
• Power dissipation: The power handling capability of the LDO linear regulator must be checked to
limit its junction temperature to the maximum rated operating range. The worst-case junction
temperature can be estimated as shown below:
Where:
is the junction-to-ambient thermal resistance of the LDO’s package
8
,
is the current
consumption of the given voltage rail in continuous TX/RX mode and
is the maximum operating
temperature of the end product inside the housing.
2.4 Data communication interfaces
2.4.1 PCI Express
The PCI Express (Peripheral Component Interconnect Express) bus of JODY-W3 series modules
support PCIe v2.0 connectivity at transfer rates up to 5 Gbaud. PCIe differential clock and data pairs
are a controlled impedance bus, and the main parameters considered for the track impedance
calculation are depicted in Figure 8.
Figure 8: Differential pair, generic controlled impedance parameters
To guarantee bus signal integrity and avoid EMI issues, the PCIe data lines must follow the
recommendations described in Table 19.
8
Thermal dissipation capability reported on datasheets is usually tested on a reference board with adequate copper area (ref.
to JESD51 [10]). Junction temperature on a typical PCB may be higher than the estimated value due to the limited space to
dissipate the heat. Thermal reliefs on pads also affect the capability of a device to dissipate the heat.