Integration Manual

JODY-W3 series - System integration manual
UBX-19011209 - R07 Design-in Page 31 of 71
C2-Restricted
☞ The HCI command complete event is generated at the old baud rate. Once the host receives
the command complete at the old baud rate, it can switch to the new baud rate and should wait
for 5 ms or more before sending any new command.
2.5 Other interfaces and notes
All digital pins have internal keeper resistors and can be left open if they are not used.
2.6 General high-speed layout guidelines
These general design guidelines are considered as best practices and are valid for any bus present in
JODY-W3 modules; the designer should prioritize the layout of higher speed busses. Low-frequency
signals are generally not layout critical.
⚠ One exception is represented by high-impedance traces (such as signals driven by weak pull
resistors) that may be affected by crosstalk. For those traces, a supplementary isolation of 4*W
from other busses is recommended.
2.6.1 General considerations for schematic design and PCB floor-planning
• Verify which signal bus requires termination and add series resistor terminations to the
schematics.
• Carefully consider the placement of the module with respect to antenna position and host
processor; RF trace length should be minimized first, followed by SDIO bus length.
• SDIO bus routing shall be planned to minimize layer-to-layer transition to a minimum.
• Verify with PCB manufacturer allowable stack-ups and controlled impedance dimensioning for
antenna traces and busses.
• Verify that the power supply design and power sequence are compliant with JODY-W3
specifications described in System function interfaces.
2.6.2 Component placement
• Accessory parts like bypass capacitors shall be placed as close as possible to the module to
improve filtering capability, prioritizing the placement of the smallest size capacitor close to
module pins.
• Do not place components close to the antenna area. The designer should carefully follow the
recommendations of the antenna manufacturer concerning the distance of the antenna in
relation to other parts of the system. The designer should also maximize the distance of the
antenna to High-frequency busses like DDRs and related components or consider an optional
metal shield to reduce interferences that could be picked up by the antenna and subsequently
reduce module sensitivity.
2.6.3 Layout and manufacturing
• Avoid stubs on high-speed signals. Test points or component pads should be placed over the PCB
trace.
• Verify the recommended maximum signal skew for differential pairs and length matching of
buses.
• Minimize the routing length; longer traces degrade signal performance. Ensure that maximum
allowable length for high-speed busses is not exceeded.
• Ensure to track your impedance matched traces. Consult early with your PCB manufacturer for
proper stack-up definition.
• RF, analog and digital sections should have dedicated and clearly separated areas on the board.
• No digital routing is allowed in the GND reference plane area of RF traces (ANT pins and Antenna).
Commented [CT42]: Ambiguous.
See earlier comment ^
Is this referring to the “hcitool” command given in
the example.
Commented [CT43R42]: ROLLOVER
Commented [CT44]: What does “it” refer to exactly?
Commented [LB45R44]: This refers to un-used pins.