Integration Manual

JODY-W3 series - System integration manual
UBX-19011209 - R07 Design-in Page 34 of 71
C2-Restricted
Ground vias density under the module: 
, thermal vias can be placed in gaps between
the thermal pads of the module.
Minimum layer count and copper thickness: , .
Minimum board size: .
Power planes and signal traces should not cross the layers beneath the module to maximize heat
flow from the module.
Those recommendations allow the design to achieve a thermal characterization parameter of

, where  refers to the “module’s junction to main PCB bottom side.
The following additional hardware techniques can be used to improve the thermal performance of the
module in customer applications:
Maximize the return loss of the antenna to reduce reflected RF power to the module.
Improve the efficiency and the thermal design of any component that generates heat in the
application, including power supplies and processor, to spread the generated heat distribution
over the application device.
Design the mechanical enclosure of the application device properly to provide ventilation and good
thermal dissipation.
For continuous operation at high temperatures, high-power density applications, or reduced PCB
size, the designer can consider including a heat sink on main bottom side of the PCB. The heat sink
should be connected using electrically insulated / high thermal conductivity adhesive
12
.
2.9 ESD guidelines
JODY-W3 modules are manufactured through a highly automated process, which complies with
IEC61340-5-1 [6] (STM5.2-1999 Class M1 devices) standard. A manufacturing process on
customer’s manufacturing site that implements a basic ESD control program is considered sufficient
to guarantee the necessary precautions
13
for handling the modules. The ESD ratings of JODY-W3
module pins are stated in Table 23Table 24.
Applicability
Immunity level
14
All pins except ANTx
Human Body Model (HBM), ANSA/ESDA/JEDEC JS-001-2014
15
.
±1000 V
Charged Device Model (CDM), JESD22-C101.
±250 V
ANTx pins
Human Body Model (HBM), AEC-Q200-002 Rev B.
±1000 V
Charged Device Model (CDM), JESD22-C101.
±500V
Table 23: ESD immunity rating for pins of the JODY-W3 module
The designer must implement proper measures to protect from ESD events on any pin that may be
exposed to the end user in compliance with the following European regulations:
ESD testing standard CENELEC EN 61000-4-2 [4]
Radio equipment standard ETSI EN 301 489-1 [5]
The minimum requirements as per these European regulations are summarized in Table 24Table
25.
Application
Category
Immunity level
All exposed surfaces of the radio equipment and ancillary
equipment in a representative configuration of the end product.
Contact discharge
4 kV
Air discharge
8 kV
12
Typically not required.
13
Minimum ESD protection level for safe handling is specified in JEDEC JEP155 (HBM) and JEP157 (CDM) for ±500 V and
±250 V respectively.
14
Target values.
15
In compliance with AEC-Q100-002 Rev E requirements.
Commented [MZ51]: TBD
Commented [LB52R51]: To be included when
simulation results are available
Commented [CT53R51]: This is an old comment Can
this be resolved?
Commented [MZ54R51]: This is a reminder that
TBD needs to be replaced with some value.
ROLLOVER
Commented [CT55R51]: Can we set the value here
now?
Commented [CT56R51]: Lars has resolved the open
comments in 2.4.2, 2.8. and 4.3
Formatted: Normal Document Reference
Commented [CT57]: Table data for ESD immunity
and ESD sensitivity are not shown in table 24.
Commented [CT58R57]: ESD immunity: Values are
in table 24. These are different from the standard
values shown in host-based modules.
Formatted: Normal Document Reference