User's Manual

LISA-U1/LISA-H1 series - System Integration Manual
3G.G2-HW-10002-2 Advance Information System description
Page 49 of 116
Every subsequent character received during the active-mode, resets and restarts the timer; hence the active-
mode duration can be extended indefinitely.
The behavior of hardware flow-control output (CTS line) during normal module operations with power-saving
and HW flow control enabled (cyclic idle-mode and active-mode) is illustrated in Figure 24.
Figure 24: CTS behavior with power saving enabled: the CTS line indicates when the module is able (CTS = ON = low level) or
not able (CTS = OFF = high level) to accept data from the DTE and communicate through the UART interface
AT+UPSV=2: power saving enabled and controlled by the RTS line
If the RTS line is set to OFF by the DTE the module is allowed to enter the idle-mode as for UPSV=1 case.
Instead, the UART is disabled as long as RTS line is set to OFF.
If the RTS line is set to ON by the DTE the module is not allowed to enter the idle-mode and the UART is kept
enabled until the RTS line is set to OFF.
When an OFF-to-ON transition occurs on the RTS input line, the UART is re-enabled and the module switches
from idle-mode to active-mode in 20 ms. This configuration can only be enabled with the module HW flow
control disabled.
Since HW flow control is disabled, the CTS line is always set to ON by the module.
When the RTS line is set to OFF by the DTE, the timeout to enter idle-mode from the last data received
at the serial port during the active-mode is the one previously set with the AT+UPSV=1 configuration or
it is the default value.
If the module has to transmit some data (e.g. URC), the UART is temporary enabled even if the RTS line
is set to OFF; UART wake-up in case of RTS line set to OFF is also possible via data reception (as
described in the following).
If the USB is connected and active, the module is forced to stay in active-mode, therefore +UPSV=1 and
+UPSV=2 modes are overruled, but in any case they have effect on the UART behavior (they configure
UART power saving mode (when it is enabled/disabled)).
Wake up from idle-mode to active-mode via data reception
If a data is transmitted by the DTE during the module idle-mode, it will be lost (not correctly received by the
module) in the following cases:
 +UPSV=1 with hardware flow control disabled
 +UPSV=2 with hardware flow control disabled and RTS line set to OFF
When the module is in idle-mode, the TxD input line of the module is always configured to wake up the module
from idle-mode to active-mode via data reception: when a low-to-high transition occurs on the TxD input line, it
causes the wake-up of the system. The module switches from idle-mode to active-mode in 20 ms from the first
data reception: this is the “wake up time” of the module. As a consequence, the first character sent when the
module is in idle-mode (i.e. the wake up character) won’t be a valid communication character because it can’t be
time [s]
CTS ON
CTS OFF
max ~2.1 s
UART disabled
min ~11 ms
UART enabled
~9.2 s (default)
UART enabled
Data input
time [s]
CTS ON
CTS OFF
max ~2.1 s
UART disabled
min ~11 ms
UART enabled
~9.2 s (default)
UART enabled