Installation Instructions
LISA-U2 series - System Integration Manual
UBX-13001118 - R19 Early Production Information System description
Page 70 of 175
If a 3.0 V Application Processor is used, appropriate unidirectional voltage translators must be provided using the
module V_INT output as 1.8 V supply, as described in Figure 36.
4
V_INT
TxD
Application processor
(3.0V DTE)
RxD
RTS
CTS
DTR
DSR
RI
DCD
GND
LISA-U2 series
(1.8V DCE)
15
TXD
12
DTR
16
RXD
13
RTS
14
CTS
9
DSR
10
RI
11
DCD
GND
0 Ω
0 Ω
TP
TP
0 Ω
0 Ω
TP
TP
1V8
B1 A1
GND
U1
B3A3
VCCBVCCA
Unidirectional
Voltage Translator
C1
C2
3V0
DIR3
DIR2 OE
DIR1
VCC
B2 A2
B4A4
DIR4
Figure 36: UART interface application circuit with partial V.24 link (5-wire) in DTE/DCE serial communication (3.0 V DTE)
Reference
Description
Part Number - Manufacturer
C1, C2
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R61A104KA01 - Murata
U1
Unidirectional Voltage Translator
SN74AVC4T774 - Texas Instruments
Table 31: Component for UART application circuit with partial V.24 link (5-wire) in DTE/DCE serial communication (3.0 V DTE)
If only TxD, RxD, RTS and CTS lines are provided, as implemented in Figure 35 and in Figure 36, and if HW
flow-control is enabled (AT&K3, default setting), the power saving can be activated in this way:
AT+UPSV=1: the module automatically enters the low power idle-mode whenever possible and the UART
interface is periodically enabled, as described in section 1.9.2.3, reaching low current consumption.
With this configuration, when the module is in idle-mode, data transmitted by the DTE will be buffered by
the DTE and will be correctly received by the module when active-mode is entered.
If the HW flow-control is disabled (AT&K0), it is recommended to enable the power saving in this way:
AT+UPSV=2: the module automatically enters the low power idle-mode whenever possible and the UART
interface is enabled by the RTS line, as described in section 1.9.2.3, reaching very low current consumption.
With this configuration, when the module is in idle-mode, the UART is re-enabled 20 ms after RTS has been
set ON, and the recognition of subsequent characters is guaranteed until the module is in active-mode.
Providing the TxD and RxD lines only (not using the complete V24 link)
If the functionality of the CTS, RTS, DSR, DCD, RI and DTR lines is not required in the application, or the lines
are not available:
Connect the module RTS input line to GND or to the CTS output line of the module: since the module
requires RTS active (low electrical level) if HW flow-control is enabled (AT&K3, that is the default setting),
the pin can be connected using a 0 Ω series resistor to GND or to the active module CTS (low electrical level)
when the module is in active mode, the UART interface is enabled and the HW flow-control is enabled
Connect the module DTR input line to GND, to robustly fix the logic level
Leave DSR, DCD and RI lines of the module unconnected and floating